CN107065336B - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN107065336B CN107065336B CN201710441509.3A CN201710441509A CN107065336B CN 107065336 B CN107065336 B CN 107065336B CN 201710441509 A CN201710441509 A CN 201710441509A CN 107065336 B CN107065336 B CN 107065336B
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- 239000000758 substrate Substances 0.000 title claims abstract description 44
- 239000002184 metal Substances 0.000 claims description 23
- 238000001514 detection method Methods 0.000 claims description 11
- 230000000007 visual effect Effects 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 abstract description 15
- 238000010586 diagram Methods 0.000 description 15
- 230000009286 beneficial effect Effects 0.000 description 7
- 239000010409 thin film Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 101150015395 TAF12B gene Proteins 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
The invention discloses an array substrate, a display panel and a display device, and belongs to the technical field of display, wherein the array substrate comprises a display area and a non-display area; a plurality of first pads located in the non-display area; a plurality of shift register control signal lines positioned in the non-display area, wherein one end of each shift register control signal line is electrically connected with a corresponding first bonding pad, and the other end of each shift register control signal line is electrically connected with a shift register positioned in the non-display area; the data signal lines are positioned in the non-display area, one end of each data signal line is electrically connected with a corresponding first bonding pad, and the other end of each data signal line is electrically connected with the data lines positioned in the display area; one end of at least part of the shift register control signal lines electrically connected with the first bonding pad is positioned between two adjacent data signal lines. According to the technical scheme, the layout space of the data signal lines in the peripheral circuit area of the lower frame of the display panel is increased, the height of the fan-out area corresponding to the data signal lines is reduced, and the narrowing of the lower frame of the display panel is facilitated.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
Currently, display devices such as Liquid Crystal Displays (LCDs) and Organic Light-Emitting diodes (OLEDs) are widely used in electronic devices such as televisions and portable computer systems. The display panel generally comprises a display area and a peripheral circuit area surrounding the display area, a plurality of data signal lines are generally arranged on the peripheral circuit area of a lower frame of the display panel, one end of each data signal line is electrically connected with a driving chip on the flexible circuit board, the other end of each data signal line is electrically connected with a data line which is positioned in the display area and connected with each pixel unit, the driving chip on the flexible circuit board transmits data signals to the data lines which are positioned in the display area and connected with each pixel unit through the data signal lines, normal display of the display panel is achieved, and an area where the data signal lines positioned on the lower frame of the display panel are positioned is called a fan-.
However, the peripheral circuit area of the lower frame of the display panel is generally provided with more control signal lines, and these control signal lines generally need to be electrically connected with the driving IC on the flexible circuit board, so as to realize that the driving IC transmits control signals to the display panel, and further realize the control of the display panel, thus greatly reducing the layout space of the peripheral circuit area data signal lines which are also located on the lower frame of the display panel, increasing the height of the fan-out area corresponding to the data signal lines, and being not beneficial to realizing the narrowing of the lower frame of the display panel.
Disclosure of Invention
In view of this, the present invention provides an array substrate, a display panel and a display device, which increase the layout space of data signal lines in the peripheral circuit region of the lower frame of the display panel, reduce the height of the fan-out region corresponding to the data signal lines, and facilitate the narrowing of the lower frame of the display panel.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
a display area and a non-display area surrounding the display area;
a plurality of first pads located in the non-display area;
a plurality of shift register control signal lines located in the non-display area, wherein one end of each shift register control signal line is electrically connected with a corresponding first bonding pad, and the other end of each shift register control signal line is electrically connected with a shift register located in the non-display area;
the data signal lines are positioned in the non-display area, one end of each data signal line is electrically connected with the corresponding first bonding pad, and the other end of each data signal line is electrically connected with the data line positioned in the display area;
one end of at least part of the shift register control signal lines electrically connected with the first bonding pad is positioned between two adjacent data signal lines.
In a second aspect, an embodiment of the present invention further provides a display panel, including the array substrate according to the first aspect.
In a third aspect, an embodiment of the present invention further provides a display device, including the display panel according to the second aspect.
The embodiment of the invention provides an array substrate, a display panel and a display device, wherein a plurality of first bonding pads are arranged in a non-display area of the array substrate; one end of each shift register control signal line is electrically connected with a corresponding first bonding pad, and the other end of each shift register control signal line is electrically connected with a shift register positioned in the non-display area; one end of each data signal line is electrically connected with a corresponding first bonding pad, and the other end of each data signal line is electrically connected with the data line positioned in the display area; and one end of at least part of the shift register control signal lines electrically connected with the first bonding pad is positioned between two adjacent data signal lines, and compared with the prior art that all the first bonding pads electrically connected with the shift register signal control lines are positioned at the edge position of the first bonding pad area, the technical scheme provided by the embodiment of the invention enables the connecting positions of the shift register control signal lines and the first bonding pads to move to the central position of the first bonding pad area, thereby realizing the movement of the connecting positions of the data signal lines and the first bonding pads to the edge position of the first bonding pad area, greatly increasing the layout space of the data signal lines positioned in the peripheral circuit area of the lower frame of the display panel, reducing the height of the fan-out area corresponding to the data signal lines and being beneficial to realizing the narrowing of the lower frame of the display panel.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a relationship between a connection position of a data signal line and a first pad and a height of a fan-out region according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a multiplexer according to an embodiment of the present invention;
fig. 4 is a schematic top view of another array substrate according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a touch electrode according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another touch electrode according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of an array substrate according to an embodiment of the present invention;
FIG. 8a is a schematic cross-sectional view taken along AA' in FIG. 1 according to an embodiment of the present invention;
FIG. 8b is a schematic cross-sectional view along AA' of FIG. 1 according to an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view taken along AA' of FIG. 1 according to another embodiment of the present invention;
FIG. 10a is a schematic cross-sectional view along AA' in FIG. 1 according to an embodiment of the present invention;
FIG. 10b is a schematic cross-sectional view taken along AA' of FIG. 1 according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures. Throughout this specification, the same or similar reference numbers refer to the same or similar structures, elements, or processes. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The embodiment of the invention provides an array substrate, which comprises a display area, a non-display area surrounding the display area, a plurality of first bonding pads positioned in the non-display area, a plurality of shift register control signal lines positioned in the non-display area and a plurality of data signal lines positioned in the non-display area. One end of each shift register control signal line is electrically connected with a corresponding first bonding pad, and the other end of each shift register control signal line is electrically connected with a shift register positioned in the non-display area; one end of each data signal line is electrically connected with a corresponding first bonding pad, and the other end of each data signal line is electrically connected with the data line positioned in the display area; one end of at least part of the shift register control signal lines electrically connected with the first bonding pad is positioned between two adjacent data signal lines.
A plurality of data signal lines and a plurality of shift register control signal lines are generally disposed in a peripheral circuit region of a lower frame of the display panel, a region where the data signal lines are located constitutes a fan-out region of the display panel, and a plurality of first pads are disposed in the peripheral circuit region of the lower frame of the display panel. At present, the position of the shift register control signal line electrically connected with the first pad is generally located at the edge of the first pad area, and the position of the data signal line electrically connected with the first pad is generally closer to the central position of the first pad area relative to the shift register signal line, so that certain limitation is formed on the layout space of the data signal line, the layout space of the data signal line in the peripheral circuit area of the lower frame of the display panel is greatly reduced, the height of a fan-out area corresponding to the data signal line is increased, and the narrowing of the lower frame of the display panel is not facilitated.
In the embodiment of the invention, a plurality of first bonding pads are arranged in the non-display area of the array substrate; one end of each shift register control signal line is electrically connected with a corresponding first bonding pad, and the other end of each shift register control signal line is electrically connected with a shift register positioned in the non-display area; one end of each data signal line is electrically connected with a corresponding first bonding pad, and the other end of each data signal line is electrically connected with the data line positioned in the display area; and one end of at least part of the shift register control signal lines electrically connected with the first bonding pad is positioned between two adjacent data signal lines, and compared with the prior art that all the first bonding pads electrically connected with the shift register signal control lines are positioned at the edge position of the first bonding pad area, the technical scheme provided by the embodiment of the invention enables the connecting positions of the shift register control signal lines and the first bonding pads to move to the center position of the first bonding pad area, thereby realizing the movement of the connecting positions of the data signal lines and the first bonding pads to the edge position of the first bonding pad area, greatly increasing the layout space of the data signal lines in the peripheral circuit area of the lower frame of the display panel, reducing the height of the fan-out area corresponding to the data signal lines, and being beneficial to realizing the narrowing of the lower frame of the display panel.
The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention. As shown in fig. 1, the array substrate includes a display area AA, a non-display area surrounding the display area, a plurality of first pads 10 located in the non-display area, a plurality of shift register control signal lines 11 located in the non-display area, and a plurality of data signal lines 13 located in the non-display area. One end of each shift register control signal line 11 is electrically connected with a corresponding first bonding pad 10, and the other end is electrically connected with a shift register 12 positioned in the non-display area; one end of each data signal line 13 is electrically connected with a corresponding first bonding pad 10, and the other end is electrically connected with a data line 14 positioned in the display area AA; one end of at least a part of the shift register control signal lines 11 electrically connected to the first pads 10 is located between two adjacent data signal lines 13. It should be noted that fig. 1 is only an example in which one end of all the shift register control signal lines 11 electrically connected to the first pad 10 is disposed between two adjacent data signal lines 13, and the embodiment of the present invention is not limited thereto.
Specifically, fig. 2 is a schematic diagram of a relationship between a connection position of a data signal line and a first pad and a height of a fan-out region provided by an embodiment of the present invention, and with reference to fig. 1 and fig. 2, F2 is a second fan-out region (left side of fig. 2) formed by a data signal line 13 in the prior art, F1 is a second fan-out region (right side of fig. 2) formed by at least a part of a shift register control signal line 11 and a first pad 10 in the present application, where one end of the shift register control signal line electrically connected to the first pad is located between two adjacent data signal lines 13, the first fan-out region (right side of fig. 2) formed by the data signal line 13, a height of a first fan-out region F1 is H1, a height of a second fan-out region F2 is H2, a width of a lower frame of a display panel in the prior art (left. The first bonding pad 10 is located in a first bonding pad region 101 having a central axis BB', by having at least part of the shift register control signal line 11 electrically connected to one end of the first pad 10 between two adjacent data signal lines 13, the position of the shift register control signal line 11 electrically connected to the first pad 10 is moved in the direction of the center axis BB 'of the first pad region 101, and the position of the data signal line 13 connected to the first pad 10 is moved away from the center axis BB' of the first pad region 101, reducing the height of the fan-out region formed by the data signal line 13, i.e., h1< h2, greatly increases the layout space of the data signal lines 13 in the peripheral circuit region located on the lower frame of the display panel, reduces the height of the fan-out region corresponding to the data signal lines 13, meanwhile, the width of the lower frame of the display panel is reduced, namely H1< H2, and the lower frame of the display panel is narrowed.
Alternatively, as shown in fig. 1, the array substrate may include a plurality of multiplexers 15 located in the non-display area, the multiplexers 15 are located on a side of the first pads 10 adjacent to the display area AA, and each data signal line 13 may be electrically connected to the data lines 14 located in the display area AA through one multiplexer 15. By thus disposing each data signal line 13 to be electrically connected to the data line 14 located in the display area through a multiplexer 15, the number of pins of the driving chip 20 for outputting data signals can be effectively reduced.
Optionally, as shown in fig. 1, the array substrate may further include a plurality of clock signal lines 19 located in the non-display area, one end of each clock signal line 19 is electrically connected to the first pad 10, the other end of each clock signal line 19 is electrically connected to the multiplexer 15, and one end of at least a part of the clock signal lines 19 electrically connected to the first pad 10 may be located between two adjacent data signal lines 13.
Specifically, with reference to fig. 1 and fig. 2, by disposing at least a portion of the end of the clock signal line 19 electrically connected to the first pad 10 between two adjacent data signal lines 13, the position where the clock signal line 19 is connected to the first pad 10 is moved to the position of the central axis BB 'of the first pad region 101, so that more space is left in the region of the first pad region 101 away from the position of the central axis BB' to electrically connect the data signal line 13 to the first pad 10, thereby reducing the height of the fan-out region formed by the data signal lines 13, and facilitating the narrowing of the lower frame of the display panel. It should be noted that fig. 1 is only exemplary to provide 1 clock signal line, and the number of the clock signal lines 19 is not limited in the embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a multiplexer according to an embodiment of the present invention. Alternatively, in conjunction with fig. 1 and 3, each multiplexer 15 may include a plurality of clock signal terminals, an input terminal and a plurality of output terminals, and fig. 3 exemplarily sets one multiplexer 15 to include three clock signal terminals CKH1, CKH2 and CKH3, one input terminal and three output terminals OUT1, OUT2 and OUT 3. The clock signal terminals are electrically connected to the clock signal lines 19 one by one, the input terminals IN are electrically connected to the data signal lines 13 one by one, and the output terminals are electrically connected to the data lines 14 of the display area one by one. Illustratively, the output terminal of one multiplexer 15 may be electrically connected to the red, green and blue sub-pixels R, G and B through the data line 14, respectively, and the multiplexer 15 may include three parallel thin film transistors T1, T2 and T3. The multiplexer 15 controls one of the tfts to be turned on according to the clock signal transmitted through the clock signal line 19, and the output terminal corresponding to the turned-on tft transmits a data signal to the data line 14 electrically connected to the output terminal, so as to supply the pixel unit located in the display region to perform normal display.
It should be noted that fig. 3 only exemplarily shows that the multiplexer 15 includes 3 thin film transistors and 3 corresponding clock signal lines and 3 output terminals, and the number of the thin film transistors in the multiplexer 15 may also be adjusted according to actual requirements, which is not limited in the embodiment of the present invention. In addition, fig. 1 and 2 only show one multiplexer by way of example and are indicated by reference numeral 15, and those skilled in the art can understand that the multiplexer 15 in fig. 1 and 2 can indicate a plurality of multiplexers, and the number of multiplexers in the array substrate is not limited by the embodiment of the present invention.
Alternatively, as shown in fig. 1, the first pads 10 (not fully shown in the figure) may be electrically connected to the second pads 17 on the flexible printed circuit 16 in a one-to-one correspondence, and the second pads 17 are electrically connected to the driving chip 20 bound on the flexible printed circuit 16. The second pads 17 may be electrically connected to corresponding pins of the driver chip 20 bound to the flexible wiring board 16 through wires (not shown) provided in the flexible wiring board 16. For example, as shown in fig. 1, the second pad 17 may be pressed on the first pad 10 by an optically conductive adhesive (not shown), that is, a part of the first pad 10 in fig. 1 is covered to achieve electrical connection with the first pad 10. Specifically, the first bonding pads 10 are electrically connected with the second bonding pads 17 arranged on the flexible circuit board 16 in a one-to-one correspondence manner, and the second bonding pads 17 are electrically connected with the driving chip 20 bound on the flexible circuit board 16, so that the driving chip 20 can accurately convey corresponding electric signals to the leads electrically connected with the first bonding pads 10 through the leads in the flexible circuit board 16 electrically connected with the pins of the driving chip 20 in a one-to-one correspondence manner, and the display panel can normally work under the driving of the driving chip 20. In addition, the driving chip 20 is bound on the flexible circuit board 16 to provide signals for the display panel, and due to the bendable characteristic of the flexible circuit board, compared with the situation that the driving chip 20 directly provides signals for the display panel, the space of the frame of the display panel can be saved, so that the frame width of the display panel is reduced, and the realization of a narrow frame is facilitated.
Optionally, fig. 4 is a schematic top view structure diagram of another array substrate according to an embodiment of the present invention. As shown in fig. 4, the array substrate may further include a visual detection module 21 located in the non-display area and a plurality of switch control signal lines 22, wherein one end of each switch control signal line 22 is electrically connected to the first pad 10, the other end of each switch control signal line 22 is electrically connected to the visual detection module 21, and one end of at least a portion of the switch control signal lines 22 electrically connected to the first pad 10 is located between two adjacent data signal lines 13. Illustratively, in conjunction with fig. 1 and 4, the switch control signal line 22 may be disposed in the same manner as the clock signal line 19, and fig. 4 does not show the clock signal line 19 for clarity of the connection position relationship between the visual detection module 21 and the switch control signal line 22, and those skilled in the art will understand that the array substrate provided by the present invention may include both the clock signal line and the switch control signal line.
Specifically, referring to fig. 2 and 4, due to the requirement of performing visual detection on the display panel after the display panel is manufactured, a visual detection module 21 and a plurality of switch control signal lines 22 are generally disposed in the non-display area, and the driving chip 20 on the flexible circuit board 16 may transmit the switch control signal to the visual detection module 21 through the switch control signal lines 22, so as to implement the detection function of the visual detection module 21. One end of at least part of the switch control signal line 22 electrically connected with the first pad 10 is arranged between two adjacent data signal lines 13, so that the position where the switch control signal line 22 is connected with the first pad 10 moves towards the direction of the central axis BB 'of the first pad area 101, and more space is reserved in the area of the first pad area 101 far away from the central axis BB' to electrically connect the data signal lines 13 with the first pad 10, thereby reducing the height of the fan-out area formed by the data signal lines 13, greatly increasing the layout space of the data signal lines 13 in the peripheral circuit area of the lower frame of the display panel, reducing the height of the fan-out area corresponding to the data signal lines 13, and being beneficial to realizing the narrowing of the lower frame of the display panel.
Optionally, with reference to fig. 1 and fig. 2, the array substrate may further include a plurality of touch signal lines 18, where one end of each touch signal line 18 is electrically connected to the first pad 10, and the other end of each touch signal line 18 is electrically connected to a touch electrode located in the display area; one end of at least a part of the touch signal lines 18 electrically connected with the first bonding pads 10 is located between two adjacent data signal lines 13. For example, some of the touch signal lines 18 and the data signal lines may be arranged alternately, as shown in fig. 1. Specifically, by arranging that at least part of the end of the touch signal line 18 electrically connected with the first pad 10 is located between two adjacent data signal lines 13, the position where the touch signal line 18 is connected with the first pad 10 moves towards the central axis BB 'of the first pad area, so that more space is left in the area of the first pad area away from the central axis BB' to electrically connect the data signal line 13 with the first pad 10, the height of the fan-out area formed by the data signal line 13 is reduced, the layout space of the data signal line 13 in the peripheral circuit area of the lower frame of the display panel is greatly increased, the height of the fan-out area corresponding to the data signal line 13 is reduced, and the narrowing of the lower frame of the display panel is facilitated.
Note that, in order to indicate the difference between the signal lines and avoid misleading, the dotted lines in fig. 1 all indicate the signal lines that actually exist.
Optionally, fig. 5 is a schematic structural diagram of a touch electrode according to an embodiment of the present invention. With reference to fig. 1 and fig. 5, the touch signal lines 18 may include mutually-capacitive touch driving signal lines 181 and mutually-capacitive touch sensing signal lines 182, the mutually-capacitive touch driving signal lines 181 are electrically connected to the strip-shaped touch driving electrodes 231, the mutually-capacitive touch sensing signal lines 182 are electrically connected to the strip-shaped touch driving electrodes 232, and the touch driving electrodes 231 and the touch sensing electrodes 232 are arranged in an insulated and crossed manner. Specifically, the touch driving electrodes 231 and the touch sensing electrodes 232 form a capacitor, a touch driving signal is sequentially input to the touch driving electrodes 231, and the touch sensing electrodes 232 simultaneously output a touch detection signal, so that the capacitance value of the intersection point of all the touch driving electrodes 231 and the touch sensing electrodes 232, that is, the capacitance value of the whole two-dimensional plane, can be obtained, and the coordinates of the touch point can be calculated according to the capacitance variation data of the two-dimensional plane.
Optionally, fig. 6 is a schematic structural diagram of another touch electrode according to an embodiment of the present invention. With reference to fig. 1 and fig. 6, the touch signal lines 18 may also include self-capacitance touch signal lines 183, each self-capacitance touch signal line 183 is electrically connected to one touch electrode 233, and the touch electrodes 233 are arranged in an array. Specifically, each touch electrode 233 forms a capacitance with the ground, and the touch position is determined by detecting the capacitance value fed back from the plurality of touch electrodes 233.
For example, fig. 7 is a schematic circuit structure diagram of an array substrate according to an embodiment of the present invention. As shown in fig. 7, the array substrate may include a plurality of data lines 14 and scan lines 26, the data lines 14 and the scan lines 26 are arranged to intersect to form a plurality of pixel units 27, each pixel unit 27 includes a pixel driving circuit 28, a pixel electrode 25 and a common electrode 24, the pixel driving circuit 28 is electrically connected to the pixel electrode 25, and the data lines 14 provide data signals to the pixel electrodes 25 in the corresponding pixel units 27 through the pixel driving circuit 28, so that a certain voltage difference is formed between the pixel electrodes 25 and the common electrode 24, and a display function of the display panel is achieved. Alternatively, with reference to fig. 6 and fig. 7, the touch electrode 233 may be reused as the common electrode 24, that is, the touch electrode 233 is used as the common electrode 24 of the display panel. When the display panel displays, a common electrode signal is input to the touch electrode 233 to realize a display function; when the display panel is used for touch control, a touch control signal is input to the touch control electrode 233 to realize a touch control function, that is, the touch control electrode 233 can be controlled in a time-sharing manner to realize a display function and a touch control function, so that the manufacturing process of the touch control display panel is simplified, and the manufacturing cost of the touch control display panel is reduced.
Optionally, fig. 8a is a schematic cross-sectional view along AA' in fig. 1 according to an embodiment of the present invention. With reference to fig. 1 and fig. 8a, the data signal line 13 may include a first type data signal line 131 and a second type data signal line 132, the first type data signal line 131 and the second type data signal line 132 are disposed in different layers, a partial section of the same shift register control signal line 11 is disposed in the same layer as the first type data signal line 131, the shift register control signal line 11 is routed to the first metal layer 201 at a position overlapping the same layer as the first type data signal line 131, and the partial section of the shift register control signal line 11 included in the first metal layer 201 is disposed in a different layer from the first type data signal line 131 and the second type data signal line 132. Specifically, since there is a partial section of the same shift register control signal line 11 disposed on the same layer as the first type data signal line 131, there is a same-layer overlapping position between the shift register control signal line 11 and the first type data signal line 131, i.e. a dotted line region shown in fig. 8a, where the shift register control signal line 11 can be routed to the first metal layer 201 by using the first via hole 111.
Optionally, with reference to fig. 1 and fig. 8a, the first metal layer 201 may include the touch signal line 18. Specifically, one end of the touch signal line 18 is electrically connected to the driving chip 20, and the other end is electrically connected to the touch electrode located in the display area AA, and is configured to provide a touch signal to the corresponding touch electrode, so as to implement a touch function of the display panel. For example, the touch signal lines 18 may include mutually-capacitive touch driving signal lines and mutually-capacitive touch sensing signal lines, and may also include self-capacitive touch signal lines.
Optionally, fig. 8b is a schematic cross-sectional view along AA' in fig. 1 according to another embodiment of the present invention. With reference to fig. 1 and fig. 8b, the data signal line 13 may include a first type data signal line 131 and a second type data signal line 132, the first type data signal line 131 and the second type data signal line 132 are disposed in different layers, a partial section of the same shift register control signal line 11 is disposed in the same layer as the second type data signal line 132, the shift register control signal line 11 is switched to the first metal layer 201 at a position overlapping the second type data signal line 132 in the same layer, and the partial section of the shift register control signal line 11 included in the first metal layer 201 and the first type data signal line 131 or the second type data signal line 132 are disposed in different layers. Specifically, since there is a partial section of the same shift register control signal line 11 and the second type data signal line 132 are disposed on the same layer, there is a same-layer overlapping position between the shift register control signal line 11 and the second type data signal line 132, i.e. a dotted line region shown in fig. 8b, where the shift register control signal line 11 can be routed to the first metal layer 201 by using the second via 112.
Optionally, with reference to fig. 1 and fig. 8b, the first metal layer 201 may include the touch signal line 18. Specifically, one end of the touch signal line 18 is electrically connected to the driving chip 20, and the other end is electrically connected to the touch electrode located in the display area AA, and is configured to provide a touch signal to the corresponding touch electrode, so as to implement a touch function of the display panel. For example, the touch signal lines 18 may include mutually-capacitive touch driving signal lines and mutually-capacitive touch sensing signal lines, and may also include self-capacitive touch signal lines.
The data signal lines arranged in fig. 8a and 8b include a first type data signal line 131 and a second type data signal line 132, so that the two metal layers are used for routing the data signal lines, the layout space available for routing the data signal lines is increased to a certain extent, the height of the fan-out area corresponding to the data signal lines can be reduced, and the narrowing of the lower frame of the display panel is facilitated.
Optionally, fig. 9 is a schematic cross-sectional view along AA' in fig. 1 according to another embodiment of the present invention. With reference to fig. 1 and 9, the data signal line 13 may be disposed on the same layer as the shift register control signal line 11, and the array substrate further includes a bridge structure 21. The bridge structure 21 may be located at an overlapping position of the shift register control signal line 11 and the data signal line 13, the bridge structure 21 is connected in series with the shift register control signal line 11, and the bridge structure 21 is insulated from the data signal line 13. Specifically, the bridge structure 21 may be insulated from the data signal line 13 by an insulating layer covering the data signal line 13 and the shift register control signal line 11.
Optionally, fig. 10a is a schematic cross-sectional view along AA' in fig. 1 according to another embodiment of the present invention. With reference to fig. 1 and 10a, there may be a partial section of the shift register control signal line 11 disposed on the same layer as the data signal line 13, and the shift register control signal line 11 is switched to the first metal layer 201 at a position overlapping with the data signal line 13 on the same layer, and the partial section of the shift register control signal line 11 and the data signal line 13 included in the first metal layer 201 are located on different layers.
Optionally, the first metal layer 201 may include the touch signal line 18, and the shift register control signal line 11 is switched to the first metal layer 201 at a position overlapping with the data signal line 13 on the same layer, i.e., in a dotted area shown in fig. 10a, i.e., to a metal layer where the touch signal line 18 is located. One end of the touch signal line 18 is electrically connected to the driving chip 20, and the other end is electrically connected to the touch electrode located in the display area AA, and is configured to provide a touch signal to the corresponding touch electrode, so as to implement a touch function of the display panel. For example, the touch signal lines 18 may include mutually-capacitive touch driving signal lines and mutually-capacitive touch sensing signal lines, and may also include self-capacitive touch signal lines.
Optionally, fig. 10b is a schematic cross-sectional view along AA' in fig. 1 according to another embodiment of the present invention. Unlike the structure shown in fig. 10a, the first metal layer 201 may also include a gate signal line, and the shift register control signal line 11 is switched to the first metal layer 201 at the overlapping position with the data signal line 13, i.e., the dotted area shown in fig. 10b, i.e., the metal layer where the gate signal line is located. The array substrate may include a plurality of thin film transistors, each of which is electrically connected to a corresponding pixel unit, each of the thin film transistors generally includes a gate, a source, and a drain, and the gate signal line is correspondingly connected to the gate of the thin film transistor to provide a scan signal to the pixel unit.
In the above fig. 10a and 10b, the shift register control signal line 11 is arranged at the overlapping position of the same layer as the data signal line 13, and the line is changed to the first metal layer which is located at a different layer from the data signal line 13, so that the layout space available for routing the data signal line 13 is increased to a certain extent, the height of the fan-out area corresponding to the data signal line 13 can be reduced, and the narrowing of the lower frame of the display panel is facilitated.
It should be noted that the drawings of the embodiments of the present invention only show the size of each element and the thickness of each film layer by way of example, and do not represent the actual size of each element and each film layer in the display panel.
In the embodiment of the invention, a plurality of first bonding pads are arranged in the non-display area of the array substrate; one end of each shift register control signal line is electrically connected with a corresponding first bonding pad, and the other end of each shift register control signal line is electrically connected with a shift register positioned in the non-display area; one end of each data signal line is electrically connected with a corresponding first bonding pad, and the other end of each data signal line is electrically connected with the data line positioned in the display area; and one end of at least part of the shift register control signal lines electrically connected with the first bonding pad is positioned between two adjacent data signal lines, and compared with the prior art that all the first bonding pads electrically connected with the shift register signal control lines are positioned at the edge position of the first bonding pad area, the technical scheme provided by the embodiment of the invention enables the connecting positions of the shift register control signal lines and the first bonding pads to move to the center position of the first bonding pad area, thereby realizing the movement of the connecting positions of the data signal lines and the first bonding pads to the edge position of the first bonding pad area, greatly increasing the layout space of the data signal lines in the peripheral circuit area of the lower frame of the display panel, reducing the height of the fan-out area corresponding to the data signal lines, and being beneficial to realizing the narrowing of the lower frame of the display panel.
The embodiment of the invention also provides a display panel, and fig. 11 is a schematic structural diagram of the display panel provided by the embodiment of the invention. As shown in fig. 11, the display panel 30 includes the array substrate 301 in the above embodiments, so that the display panel 30 provided in the embodiment of the present invention also has the beneficial effects described in the above embodiments, and the details are not repeated herein. The display panel 30 may be an organic light emitting display panel or a liquid crystal display panel, for example.
Fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 12, the display device 3 includes the display panel 30 in the above embodiment, so that the display device 3 provided in the embodiment of the present invention also has the beneficial effects described in the above embodiment, and further description is omitted here. The display device 3 may be an electronic display device such as a mobile phone, a computer, or a television.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (15)
1. An array substrate, comprising:
a display area and a non-display area surrounding the display area;
a plurality of first pads located in the non-display area;
a plurality of shift register control signal lines located in the non-display area, wherein one end of each shift register control signal line is electrically connected with a corresponding first bonding pad, and the other end of each shift register control signal line is electrically connected with a shift register located in the non-display area;
the data signal lines are positioned in the non-display area, one end of each data signal line is electrically connected with the corresponding first bonding pad, and the other end of each data signal line is electrically connected with the data line positioned in the display area;
along the arrangement direction of the first bonding pads, the first bonding pads comprise a middle first bonding pad area and edge first bonding pad areas positioned on two sides of the middle first bonding pad area, and one end, electrically connected with the first bonding pads, of at least part of the shift register control signal lines is positioned between two adjacent data signal lines of the edge first bonding pad areas;
the data signal lines comprise a first type data signal line and a second type data signal line, and the first type data signal line and the second type data signal line are arranged in different layers;
for the same shift register control signal line, a partial section is arranged in the same layer with the first type data signal line, and the shift register control signal line is switched to the first metal layer at the overlapping position of the partial section and the first type data signal line in the same layer, or for the same shift register control signal line, a partial section is arranged in the same layer with the second type data signal line, and the shift register control signal line is switched to the first metal layer at the overlapping position of the partial section and the second type data signal line in the same layer;
the shift register control signal line, the first type data signal line and the second type data signal line in a partial section included in the first metal layer are located in different layers.
2. The array substrate of claim 1, further comprising:
a plurality of multiplexers located in the non-display area, the multiplexers being located on a side of the first pads adjacent to the display area;
each data signal line is electrically connected with the data line positioned in the display area through one multiplexer.
3. The array substrate of claim 1, wherein the first pads are electrically connected to the second pads on the flexible circuit board in a one-to-one correspondence;
the second bonding pad is electrically connected with the driving chip bound on the flexible circuit board.
4. The array substrate of claim 3, wherein the second pads are electrically connected to pins of a driver chip bound on the flexible circuit board through wires arranged in the flexible circuit board.
5. The array substrate of claim 2, further comprising:
a plurality of clock signal lines located in the non-display area, wherein one end of each clock signal line is electrically connected with the first bonding pad, and the other end of each clock signal line is electrically connected with the multiplexer;
one end of at least part of the clock signal lines electrically connected with the first bonding pads is positioned between two adjacent data signal lines.
6. The array substrate of claim 1, further comprising:
one end of each touch signal line is electrically connected with the corresponding first bonding pad, and the other end of each touch signal line is electrically connected with the corresponding touch electrode in the display area;
at least one end of the touch signal line electrically connected with the first bonding pad is positioned between two adjacent data signal lines.
7. The array substrate of claim 6, wherein the touch signal lines comprise mutually-capacitive touch driving signal lines and mutually-capacitive touch sensing signal lines, the mutually-capacitive touch driving signal lines are electrically connected with the strip-shaped touch driving electrodes, the mutually-capacitive touch sensing signal lines are electrically connected with the strip-shaped touch sensing electrodes, and the touch driving electrodes and the touch sensing electrodes are arranged in an insulated and crossed manner.
8. The array substrate of claim 6, wherein the touch signal lines comprise self-contained touch signal lines, each of the self-contained touch signal lines is electrically connected to a touch electrode, and the touch electrodes are arranged in an array.
9. The array substrate of claim 8, wherein the touch electrodes are multiplexed as a common electrode.
10. The array substrate of claim 1, further comprising:
the visual detection module and the plurality of switch control signal lines are positioned in the non-display area;
one end of each switch control signal line is electrically connected with the first bonding pad, and the other end of each switch control signal line is electrically connected with the visual detection module;
one end of at least part of the switch control signal lines electrically connected with the first bonding pad is positioned between two adjacent data signal lines.
11. The array substrate of claim 1, wherein the first metal layer comprises a touch signal line.
12. The array substrate of claim 1, wherein the first metal layer comprises a gate signal line.
13. The array substrate of claim 2, wherein each of the multiplexers comprises a plurality of clock signal terminals, an input terminal and a plurality of output terminals;
the clock signal ends are electrically connected with the clock signal lines one by one, the input ends are electrically connected with the data signal lines one by one, and the output ends are electrically connected with the data lines of the display area one by one.
14. A display panel comprising the array substrate according to any one of claims 1 to 13.
15. A display device characterized by comprising the display panel according to claim 14.
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