CN111708238B

CN111708238B - Array substrate and display panel

Info

Publication number: CN111708238B
Application number: CN202010622466.0A
Authority: CN
Inventors: 金慧俊; 简守甫; 秦丹丹; 王听海
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2023-06-13
Anticipated expiration: 2040-06-30
Also published as: CN111708238A

Abstract

The embodiment of the invention describes an array substrate and a display panel comprising the same, wherein the array substrate comprises a display area and a non-display area surrounding the display area, and a first pin, a second pin and a third pin are arranged on one non-display side; the second pins are arranged on two sides of the first pin, and the first pin and the second pin are arranged opposite to the third pin; wherein two non-adjacent pins of the plurality of first pins are at a distance from any one of the plurality of third pins in the second direction that is less than a distance from at least one first pin located intermediate the two non-adjacent first pins to any one of the plurality of third pins; in the second direction, there are at least two second pins, wherein a distance between the second pin near the first pin and any one of the plurality of third pins is smaller than a distance between the second pin far from the first pin and any one of the plurality of third pins.

Description

Array substrate and display panel

Technical Field

The present invention relates to the field of display, and in particular, to an array substrate and a display panel including the same.

Background

With the continuous development of display markets, consumers have increasingly stringent requirements on visual effects of display screens, and not only have diversified requirements on appearance designs of the display screens, but also have increasingly higher requirements on screen occupation ratios. The trend of the comprehensive screen technology is that through the design of ultra-narrow frames and even no frames, the screen occupation ratio of more than or equal to 90% is pursued, and under the condition that the total area of the machine body is unchanged, the display area is maximized, and the visual effect is more attractive.

The integrated circuit Chip is bound On Glass (COG, chip On Glass) which is a technology used in the current display module, but the direct binding of the integrated circuit Chip (IC) to the Glass of the display panel occupies the area of the non-display area of the display panel, which is not beneficial to further realizing the design of the narrow-frame full-screen of the liquid crystal display panel.

Disclosure of Invention

In view of the above, the present invention provides an array substrate and a display panel.

The embodiment of the invention provides an array substrate, which comprises: the display area comprises a plurality of scanning lines extending along a first direction and arranged along a second direction, and a plurality of data lines extending along the second direction and extending along the first direction; adjacent two scanning lines and adjacent two data lines are crossed to form a pixel area; the display area comprises a plurality of pixel areas which are arranged in an array; a non-display area disposed around the display area; the non-display area comprises a first non-display area, a second non-display area, a third non-display area and a fourth non-display area, wherein the first non-display area and the second non-display area are oppositely arranged, and the third non-display area and the fourth non-display area are oppositely arranged; the third non-display area and the fourth non-display area are provided with gate driving circuits, and the gate driving circuits comprise a plurality of driving signal lines; the first non-display area comprises an IC setting area and an FPC setting area; the IC arrangement area comprises a plurality of first pins, a plurality of second pins and a plurality of third pins; the plurality of first pins are electrically connected with the plurality of data lines; the plurality of second pins are electrically connected with the plurality of driving signal lines; the first pins and the third pins are oppositely arranged; the distance between the first pins and any one of the third pins is smaller than the distance between at least one first pin positioned in the middle of the two non-adjacent first pins and any one of the third pins in the second direction; the plurality of second pins are located at two sides of the plurality of first pins, and at least two second pins are located in the second direction, wherein the distance between the second pins close to the first pins and any one of the plurality of third pins is smaller than the distance between the second pins far away from the first pins and any one of the plurality of third pins.

The embodiment of the invention provides a display panel, which can comprise the array substrate.

According to the array substrate and the display panel provided by the embodiment of the invention, under the condition that the first pins, the second pins and the third pins are arranged, the display performance can be ensured, namely, the first safety distance, the second safety distance and the third safety distance are ensured, so that the first pins and the third pins are arranged closer to the display area, namely, compared with the prior art, the width of the first non-display area in the second direction can be reduced, the display area occupation ratio can be further improved, and the display effect is improved.

Drawings

FIG. 1 is a schematic top view of an array substrate according to the prior art;

FIG. 2 is a schematic top view of an IC corresponding to FIG. 1;

FIG. 3 is an enlarged schematic view of the first non-display area in FIG. 1;

FIG. 4 is a schematic top view of an alternative embodiment of an IC corresponding to the IC shown in FIG. 1;

FIG. 5 is a schematic view of another enlarged structure of the first non-display area in FIG. 1;

fig. 6 is a schematic top view of an array substrate according to an embodiment of the present invention;

fig. 7 is a schematic top view of an IC corresponding to fig. 6 according to an embodiment of the present invention;

FIG. 8 is an enlarged schematic view of the first non-display area in FIG. 6;

FIG. 9 is a schematic view of another enlarged structure of the first non-display area in FIG. 6;

FIG. 10 is a schematic view of another enlarged structure of the first non-display area in FIG. 6;

FIG. 11 is a schematic view of another enlarged structure of the first non-display area in FIG. 6.

Detailed Description

In order that the above objects, features and advantages of the invention will be readily understood, a further description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

It is noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than those herein described, and those skilled in the art may readily devise numerous other arrangements that do not depart from the spirit of the invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

In order to better understand the inventive concept of the present invention, the prior art will be described with reference to fig. 1 to 3, which are schematic top views of an array substrate and related structures in the prior art, specifically, fig. 1 is a schematic top view of an array substrate in the prior art, fig. 2 is a schematic top view of an IC (integrated circuit) corresponding to fig. 1, and fig. 3 is an enlarged schematic top view of a first non-display area in fig. 1.

Referring to fig. 1 to 3 in combination, in the prior art, an array substrate includes a display area 230', in which a plurality of scan lines extending in a first direction (horizontal direction in the drawing) and a plurality of data lines extending in a second direction (vertical direction in the drawing) are disposed, and two adjacent scan lines and two adjacent data lines intersect to form a pixel area; in each pixel region, a driving transistor or the like is further included to drive each pixel to perform light-emitting display. All pixel areas of the display area are arranged in an array.

In the prior art, the array substrate further includes a non-display area 240' surrounding the display area 230', wherein the non-display area 240' includes a first non-display area 241', a second non-display area 242', a third non-display area 243' and a fourth non-display area 244'. Wherein the first non-display area 241 'and the second non-display area 242' are disposed opposite each other, and the third non-display area 243 'and the fourth non-display area 244' are disposed opposite each other. In the related art shown in fig. 1, the first non-display region 241 'is generally referred to as a step region because the first non-display region 241' is generally not covered by the opposite substrate after the array substrate is attached thereto, but is formed in a step-like shape, and thus is generally referred to as a "step region". The step region, i.e., the first non-display region 241', is generally provided with a display chip for driving, and is generally provided with a flexible printed circuit board (Flexible Printed Circuit, FPC) connected to a main board or the like. Referring to fig. 1, in the related art, an IC arrangement region 200' and an FPC arrangement region 220' are provided in a first non-display region 241', a plurality of pins for connection with an IC are provided on the IC arrangement region 200', and a plurality of pins for connection with an FPC are provided on the FPC arrangement region 220 '. In the third and fourth non-display regions 243' and 244', a gate driving circuit driving the scan lines in the display region 230' to operate is generally provided, and the gate driving circuit generally includes a plurality of driving signal lines, for example, a clock signal line, a high-low level signal line, a start control line, a reset control line, and the like.

Referring to fig. 2, in the prior art, an IC is generally provided with pins on both sides thereof, for example, a data line driving output pin 102' is provided on the upper side of the drawing, and is used for outputting a driving signal to a data line after electrically connecting with a corresponding first pin of a driving data line on an array substrate. Since a large number of data lines are disposed on the array substrate, the data line driving output pins 102' typically occupy one side of the entire IC and are arranged in a plurality of rows. On the lower side of the illustrated IC, an IC drive input pin 106' is provided for electrically connecting to a third pin on the array substrate, and inputting a drive signal to the IC. Since the number of the driving input pins 106' is small, driving signal output pins 104' are further provided on both sides of the driving input pins 106' for electrically connecting with the second pins of the array substrate to transmit driving signals to the driving signal lines.

Referring to fig. 3, in the prior art, corresponding to the pins on the IC, in the first non-display area of the array substrate, a first pin 202', a second pin 204', and a third pin 206' are disposed, wherein the positions of the first pin 202', the second pin 204', and the third pin 206' correspond to the positions of the data line driving output pin 102', the driving signal output pin 104', and the IC driving input pin 106' of the IC in fig. 2. That is, the first pin 202' is disposed opposite to the third pin 206', and the second pin 204' is disposed opposite to the first pin 202' on both sides of the third pin 206 '. The first pin 202', the second pin 204', and the third pin 206 'are located in the IC arrangement region 200'.

With continued reference to fig. 3, in the prior art, the first pins 202 'are electrically connected to the data lines 210', i.e., each of the first pins 202 'is electrically connected to one of the data lines 210'. Since the display area is located above the illustrated IC arrangement area 200 'and has a width in the first direction (horizontal direction) that is substantially greater than the width of the IC in the first direction, the leads connecting the first pins 202' and the data lines 210 'form a fan-shaped area, called a "fan-out area", which generally includes a plurality of parallel diagonal lines, and the area closest to the edge has a longer diagonal line during the extending from the first pins 202' to the display area. To ensure good connection of the IC, a third safe distance DC is provided between the diagonal of the fan-out area and the first pin 202'.

With continued reference to fig. 3, in the prior art, the second pin 204 'is electrically connected to the driving signal line 212', and the driving signal line 212 'extends from the IC arrangement region 200' to the third non-display region and the fourth non-display region. As shown, the driving signal line 212 'extends downward from the second pin 204', and then bends upward, i.e. the driving signal line 212 'extends from the second pin 204' in a direction away from the display area 230 'and then bends toward the display area 230'. The third pin 206 'is electrically connected to the fourth pin 226' through a signal line, the fifth pin 224 'is disposed on both sides of the fourth pin 226', and the fourth pin 226 'and the fifth pin 224' are disposed in the FPC-set area for electrical connection with the FPC.

In the prior art, in order to ensure the transmission of each signal and the performance of each component, a second safety distance DB is required between the first pin 202 'and the third pin 206'. In the process of leading out the driving signal line far from the display area 230', the first safety distance DA is ensured between the driving signal line and the fourth pin 226' and the fifth pin 224 '.

Due to the first, second and third safety distances DA, DB and DC, the width of the first non-display area 241' in the second direction (vertical direction in the drawing) is inevitably too wide, which is not conducive to narrowing the frame, providing the screen ratio, and improving the display effect.

For this reason, in the prior art, a researcher proposes another array substrate, please refer to fig. 1, fig. 4 and fig. 5, fig. 4 is another schematic top view of an IC (Integrated Circuit ) corresponding to fig. 1, and fig. 5 is another schematic enlarged schematic view of the first non-display area in fig. 1.

Referring to fig. 4, in the prior art, a data line driving output pin 102' is disposed at the upper side of the diagram, and is configured to electrically connect with a corresponding first pin of a driving data line on the array substrate, and then output a driving signal to the data line. On the lower side of the illustrated IC, an IC drive input pin 106' is provided for electrically connecting to a third pin on the array substrate, and inputting a drive signal to the IC. On both sides of the data line driving output pin 102', a driving signal output pin 104' is further provided for electrically connecting with a second pin of the array substrate to transmit a driving signal to the driving signal line.

Referring to fig. 5, in the prior art, corresponding to the pins on the IC, in the first non-display area of the array substrate, a first pin 202', a second pin 204', and a third pin 206' are disposed, wherein the positions of the first pin 202', the second pin 204', and the third pin 206' correspond to the positions of the data line driving output pin 102', the driving signal output pin 104', and the IC driving input pin 106' of the IC in fig. 4. That is, the first pin 202' is disposed opposite to the third pin 206', and the second pin 204' is disposed opposite to the third pin 206' on both sides of the first pin 202 '. The first pin 202', the second pin 204', and the third pin 206 'are located in the IC arrangement region 200'.

With continued reference to fig. 5, in the prior art, the first pins 202 'are electrically connected to the data lines 210', i.e., each of the first pins 202 'is electrically connected to one of the data lines 210'. Since the display area is located above the illustrated IC arrangement area 200 'and has a width in the first direction (horizontal direction) that is substantially greater than the width of the IC in the first direction, the leads connecting the first pins 202' and the data lines 210 'form a fan-shaped area, called a "fan-out area", which generally includes a plurality of parallel diagonal lines, and the area closest to the edge has a longer diagonal line during the extending from the first pins 202' to the display area.

With continued reference to fig. 5, in the prior art, the second pin 204 'is electrically connected to the driving signal line 212', and the driving signal line 212 'extends from the IC arrangement region 200' to the third non-display region and the fourth non-display region. As shown, the driving signal line 212 'extends upward from the second pin 204', and the driving signal line 212 'extends from the second pin 204' in a direction approaching the display area 230 'and in a direction approaching the display area 230'. That is, in the prior art, the driving signal line 212 'is located at two sides of the data line and also includes a fanout area, and at this time, in order to ensure a good connection of the IC, a third safety distance DC is provided between the diagonal line of the fanout area and the first pin 202'. The third safety distance DC is determined by a diagonal line closest to the edge, i.e. a driving signal line closest to the edge.

The third pin 206 'is electrically connected to the fourth pin 226' through a signal line, the fifth pin 224 'is disposed on both sides of the fourth pin 226', and the fourth pin 226 'and the fifth pin 224' are disposed in the FPC-set area for electrical connection with the FPC.

In the prior art, in order to ensure the transmission of each signal and the performance of each component, a second safety distance DB is required between the first pin 202 'and the third pin 206'.

In the prior art shown in fig. 4 and 5, the first safety distance DA is determined by the distance between the third pin 206' and the fourth pin 226' and the fifth pin 224 '. At this time, the distance between the third pin 206 'and the fourth pin 226' and the fifth pin 224 'in fig. 5 has been greatly reduced, and the width of the first non-display region 241' in the second direction (vertical direction in the drawing) has been greatly improved, compared to the prior art of fig. 3. However, since the driving signal line 212 'is disposed close to the data line 210', electrostatic discharge is easily caused, and poor display is finally caused.

In order to improve the display duty ratio and improve the display effect, an embodiment of the present invention provides an array substrate, including: the display area comprises a plurality of scanning lines extending along a first direction and arranged along a second direction, and a plurality of data lines extending along the second direction and extending along the first direction; adjacent two scanning lines and adjacent two data lines are crossed to form a pixel area; the display area comprises a plurality of pixel areas which are arranged in an array; a non-display area disposed around the display area; the non-display area comprises a first non-display area, a second non-display area, a third non-display area and a fourth non-display area, wherein the first non-display area and the second non-display area are oppositely arranged, and the third non-display area and the fourth non-display area are oppositely arranged; the third non-display area and the fourth non-display area are provided with gate driving circuits, and the gate driving circuits comprise a plurality of driving signal lines; the first non-display area comprises an IC setting area and an FPC setting area; the IC arrangement area comprises a plurality of first pins, a plurality of second pins and a plurality of third pins; the plurality of first pins are electrically connected with the plurality of data lines; the plurality of second pins are electrically connected with the plurality of driving signal lines; the first pins and the third pins are oppositely arranged; the distance between the first pins and any one of the third pins is smaller than the distance between at least one first pin positioned in the middle of the two non-adjacent first pins and any one of the third pins in the second direction; the plurality of second pins are located at two sides of the plurality of first pins, and at least two second pins are located in the second direction, wherein the distance between the second pins close to the first pins and any one of the plurality of third pins is smaller than the distance between the second pins far away from the first pins and any one of the plurality of third pins.

The following detailed description will be given with reference to the accompanying drawings. Referring to fig. 6 to fig. 8, fig. 6 is a schematic top view of an array substrate according to an embodiment of the present invention, fig. 7 is a schematic top view of an IC corresponding to fig. 6, and fig. 8 is an enlarged schematic view of a first non-display area in fig. 6.

In this embodiment, the array substrate includes a display area 230, in which a plurality of scan lines extending in a first direction (horizontal direction in the drawing) and a plurality of data lines extending in a second direction (vertical direction in the drawing) are disposed in the display area 230, and two adjacent scan lines and two adjacent data lines intersect to form a pixel area; in each pixel region, a driving transistor or the like is further included to drive each pixel to perform light-emitting display. All pixel areas of the display area are arranged in an array.

Referring to fig. 6, an array substrate provided in an embodiment of the present invention includes a display area 230 and a non-display area 240 surrounding the display area 230, wherein the non-display area 240 includes a first non-display area 241, a second non-display area 242, a third non-display area 243 and a fourth non-display area 244. Wherein the first non-display area 241 and the second non-display area 242 are disposed opposite to each other, and the third non-display area 243 and the fourth non-display area 244' are disposed opposite to each other. Similar to the related art shown in fig. 1, in the present embodiment, in the first non-display region 241, the IC setting region 200 and the FPC setting region 220 are provided, a plurality of pins for connection with an IC are provided on the IC setting region 200, and a plurality of pins for connection with an FPC are provided on the FPC setting region 220. In the third and fourth

non-display regions

243 and 244, a gate driving circuit driving the scan lines in the display region 230 to operate is provided, and generally includes a plurality of driving signal lines, for example, a clock signal line, a high-low level signal line, a start control line, a reset control line, and the like.

Referring to fig. 7, in this embodiment, the IC10 is provided with pins on both sides thereof, for example, a data line driving output pin 102 is provided on the upper side in the drawing, and is used for outputting a driving signal to a data line after being electrically connected to a first pin of a corresponding driving data line on the array substrate. Since a very large number of data lines are provided on the array substrate as above. An IC drive input pin 106 is provided on the lower side of the illustrated IC, and is electrically connected to a third pin on the array substrate, and inputs a drive signal to the IC. A driving signal output pin 104 is further disposed on two sides of the data line driving output pin 102, and is electrically connected to the second pin of the array substrate, and transmits a driving signal to the driving signal line. In this embodiment, two non-adjacent ones of the plurality of data line drive output pins 102 are located at a distance from any one of the plurality of IC drive input pins 106 in the second direction (vertical direction in the drawing) that is smaller than a distance between at least one data line drive output pin 102 located intermediate the two non-adjacent data line drive output pins 102 and any one of the plurality of IC drive input pins 106. That is, in the IC10 corresponding to the array substrate provided in the present embodiment, the data line driving output pins 102, which are located at both sides, are closer to the IC driving input pins 106 than the pins located in the middle.

In this embodiment, the data line driving output pins 102 are divided into a first group including all the data line driving output pins 102 located on one side of the center of symmetry of the IC10 and a second group including all the data line driving output pins 102 located on the other side of the center of symmetry of the IC10, with the center of symmetry of the IC10 along the second direction (vertical direction in the drawing). Wherein in the first/second group the data line drive output pins 102 are offset away from the center of symmetry of the IC towards the display area, i.e. away from the center of symmetry of the IC towards the near IC drive input pins 106. In other embodiments of the present invention, the data line driving output pins 102 further include a third group, the third group being located between the first group of data line driving output pins 102 and the second group of data line driving output pins 102, the third group of data line driving output pins 102 being located at an equal distance from the IC driving input pins 106 than the first group of data line driving output pins 102 and the second group of data line driving output pins 102, and being greater than the distance from the IC driving input pins 106 between the first/second group of data line driving output pins 102.

In this embodiment, the plurality of driving signal output pins 104 are located at two sides of the plurality of data line driving output pins 102, and in the second direction (vertical direction in the drawing), at least two driving signal output pins 104 are present, wherein the distance between the driving signal output pin 104 near the data line driving output pin 102 and any one of the plurality of IC driving input pins 106 is smaller than the distance between the driving signal output pin 104 far from the data line driving output pin 102 and any one of the plurality of IC driving input pins 106. That is, in the present embodiment, the driving signal output pin 104 located outside the data line driving output pin 102 is offset toward the display area, that is, toward the direction away from the IC driving input pin 106, as it is further away from the data line driving output pin 102. In this embodiment, the driving signal output pins 104 located at both sides of the data line driving output pin 102 are divided into a fourth group and a fifth group, and in the fourth group/the fifth group of driving signal output pins 104, as they are away from the center of symmetry of the IC, the driving signal output pins are shifted toward the display area, that is, as they are away from the center of symmetry of the IC, the driving signal output pins are shifted toward the driving signal input pins 106 away from the IC.

Referring to fig. 8, in the present embodiment, corresponding to the pins on the IC, in the first non-display area of the array substrate, a first pin 202, a second pin 204 and a third pin 206 are disposed, wherein the positions of the first pin 202, the second pin 204 and the third pin 206 correspond to the positions of the data line driving output pin 102, the driving signal output pin 104 and the IC driving input pin 106 of the IC in fig. 7. That is, the first pin 202 is disposed opposite to the third pin 206, and the second pin 204 is disposed opposite to the third pin 206 and on both sides of the first pin 202. The first pin 202, the second pin 204, and the third pin 206 are all located in the IC arrangement region 200.

With continued reference to fig. 8, in the present embodiment, the first pins 202 are electrically connected to the data lines 210, that is, each of the first pins 202 is electrically connected to one of the data lines 210. Since the display area is located above the illustrated IC arrangement area 200 and the width of the display area in the first direction Dx is much greater than the width of the IC in the first direction Dx, a fan-shaped area, called "fan-out area", is formed by the wires connecting the first pins 202 and the data lines 210 during the process of extending from the first pins 202 to the display area. That is, the first non-display area includes a plurality of data leads, and both ends of the plurality of data leads are electrically connected to the plurality of data lines and the plurality of first lead corners, respectively; at least one of the plurality of data leads includes an inclined section extending in a direction intersecting both the first direction Dx and the second direction Dy. Generally, the fan-out area will contain many diagonal lines arranged in parallel, and the area closest to the edge will have a longer diagonal line. To ensure good connection of the IC, a third safe distance DC is provided between the diagonal of the fan-out area and the first pin 202.

In this embodiment, there are two non-adjacent pins in the plurality of first pins 202, and the distance between the first pin 202 and any one of the plurality of third pins 206 in the second direction Dy is smaller than the distance between the first pin 202 and any one of the plurality of third pins 206 located in the middle of the two non-adjacent pins 202. That is, in the array substrate provided in this embodiment, the first pins 202 are located on two sides of the array substrate, and are closer to the third pins 206 than the middle pins.

In this embodiment, the first pins 202 are divided into a first group and a second group by the symmetry center of the array substrate along the second direction Dy, wherein the first group includes all the first pins 202 located at one side of the symmetry center of the array substrate, and the second group includes all the first pins 202 located at the other side of the symmetry center of the array substrate. Wherein in the first/second group, the first pins 202 are offset away from the center of symmetry of the array substrate, i.e., toward the third pins 206 as they are away from the center of symmetry of the array substrate. In other embodiments of the present invention, the first pins 202 further comprise a third set of first pins, the third set of first pins being located between the first set of first pins and the second set of first pins, the third set of first pins 202 being equidistant from the third pins 206 and being greater than the first/second set of first pins 202 and the third pins 206. In other embodiments of the present invention, the first pins may include a plurality of first groups and a plurality of second groups, and when the array substrate is provided with a plurality of IC arrangement regions, there may be a set of first pins corresponding to each IC arrangement region, where the set of first pins includes a first group of first pins and a second group of second pins, and the set of first pins is centered on a symmetry center of the set of first pins, and the further from the symmetry center, the further the pins are from the display region. Further, each set of first pins includes a third set of first pins located between the first set of first pins and the second set of first pins in addition to one first set of first pins and one second set of first pins.

In this embodiment, the plurality of second pins 204 are located at two sides of the plurality of first pins 202, and at least two second pins 204 exist in the second direction Dy, wherein a distance between the second pin 204 near the first pin 202 and any one of the plurality of third pins 206 is smaller than a distance between the second pin 204 far from the first pin 202 and any one of the plurality of third pins 206. That is, in the present embodiment, the second pin 204 located outside the first pin 202 is offset toward the display area, that is, toward the direction away from the third pin 206, the farther it is from the first pin 202. In this embodiment, the second pins 204 located at two sides of the first pin 202 are divided into a fourth group and a fifth group, and in the fourth group/the fifth group of the second pins 204, the second pins are shifted toward the display area as they are away from the center of symmetry of the array substrate, that is, the second pins are shifted toward the third pins 206 as they are away from the center of symmetry of the array substrate. In other embodiments of the present invention, when the array substrate includes a plurality of sets of first pins, the second pins are located on two sides of all the first pins.

Referring to fig. 8, in the present embodiment, in the second direction Dy, the direction of extraction of the first pins 202 and the data lines 210 is the direction shown in the drawing upwards, and the direction of extraction of the second pins 204 and the driving signal lines 212 is the direction shown in the drawing downwards, that is, the direction of extraction of the first pins 202 electrically connected to the plurality of data lines 210 is opposite to the direction of extraction of the plurality of second pins 204 electrically connected to the plurality of driving signal lines 212. Since the extraction direction of the driving signal line 212 is opposite to that of the data line in the present embodiment, the third safety distance DC between the diagonal line of the fan-out area and the first pin 202 is limited only by the diagonal line of the data line electrically connected to the data line, not by the driving signal line in the present embodiment. Because of the widths of the display area and the IC arrangement area of the array substrate, the straight line area from the first pin to the fan-out area is generally in a shape with a middle wide and two narrow ends, and the third safety distance DC is the width of the area with two narrow sides of the straight line area. And the width of the straight line area is wider at the middle part of the outgoing line. In this embodiment, compared with the prior art shown in fig. 3 or fig. 5, the first pin 202 of the middle area in this embodiment is retracted toward the display area. Since the middle portion of the lead-out wire itself has a relatively wide width in the straight area, the setback of the first pin 202 does not affect the setting of the third safety distance DC, i.e., the setback of the first pin 202 does not affect the width setting of the first pin 202 to the non-display area in the display area.

Further, referring to fig. 8, the second pins 204 and the driving signal lines 212 are led out in a direction away from the display area, and then bent to extend in a direction close to the display area, so that the driving signal lines 212 occupy a part of space in a downward position area of the driving signal lines 212 during bending. In the present embodiment, the second pins 204 are offset toward the direction approaching the display area as they are farther from the symmetry center of the array substrate in the second direction Dy. Therefore, the outermost lead line may be shifted toward the display area during bending of the lead line of the driving signal line 212. Therefore, the space occupied by all the lead-out wires of the drive signal lines below the second pins is much smaller than the space occupied by the lead-out wires of the drive signal lines 212 'below the second pins 204' in fig. 3. In addition, in this embodiment, the second pin 204 is located near the position of the display area where the display area is cheap, and corresponds to the fan-out area of the data line, where the area is the bevel edge area of the fan-out lead, and the second pin is also arranged in the direction similar to the bevel edge in the process of upwards shifting, so that the occupied position is the blank area under the fan-out area originally, and no additional layout improvement of other components is needed.

Further, since the lead lines of the first pin 202 and the data line 210 are led out in the upward direction as shown in the drawing, the lead lines of the second pin 204 and the driving signal line 212 are led out in the downward direction as shown in the drawing. The driving signal line 212 may be bent at a position close to the frame region. Objectively, the distance between the signal line 210 and the driving signal line 212 is increased, and thus, the problem that static electricity is easily generated or parasitic capacitance is easily generated between the data line 210 'and the driving signal line 212' as in the prior art in fig. 5 is solved.

With continued reference to fig. 8, in the present embodiment, in the IC arrangement region, a third pin 206 is provided at a position opposite to the first pin 202. The third pin 206 is electrically connected to the fourth pin 226 of the FPC-provided area to receive a driving signal for driving the IC from the FPC. In this embodiment, the number of the third pins 206 is much smaller than the number of the first pins 202, so that the extending width of the plurality of third pins 206 in the first direction Dx of the IC arrangement area 200 is much smaller than the extending width of the plurality of first pins 202 in the first direction Dx. In this embodiment, since the plurality of first pins 202 are retracted toward the display area, the second pins 206 of this embodiment may be closer to the display area than the prior art in fig. 3 or 5, while ensuring the second safety distance DB between the first pins 202 and the third pins 206. This is because, in the present embodiment, since the extension width of the plurality of third pins 206 in the first direction Dx is much smaller than the extension width of the plurality of first pins 202 in the first direction Dx, and the plurality of first pins are located further from the center of symmetry of the array substrate, the plurality of first pins are offset toward the display area. Thus, in the present embodiment, the second safety distance is the distance between the third pins 206 on the two most sides and one of the first pins 202 adjacent thereto in the second direction. And because of the plurality of first pins 202 opposite the third pins 206, they are closer to the display area than the first pins 202 not opposite the third pins 206, and accordingly, all of the third pins are also retracted a partial distance from the display area than in the prior art. The first pin 202, which is not opposite to the third pin, is not limited by the second safety distance DB because the other pins are not disposed on the opposite side thereof, and may be closer to the edge of the IC arrangement region away from the display region than the first pin opposite to the third pin 206.

Still further, referring to fig. 8, in the present embodiment, the FPC-set area is located on a side of the IC-set area 200 away from the display area, and a plurality of fourth pins 226 and a plurality of fifth pins 224 are disposed in the FPC-set area. The fourth pin 226 is disposed opposite to the third pin 206 for providing a driving signal to the third pin 206, and the fourth pin is used for being connected with other pins of the FPC, inputting other signals, and may be electrically connected with some other elements on the array substrate. Between the third pin 206 and the fourth pin 226, a first safety distance DA is to be ensured.

Through the first pin, the second pin and the third pin that this embodiment provided, can guarantee the display performance, guarantee promptly under the prerequisite of first safe distance, second safe distance and third safe distance for first pin 202, third pin 206 are closer to the display area setting, promptly, compare prior art promptly, can reduce the width of first non-display area 241 in the second direction Dy, can further improve the display area and take up an account the ratio, improve the display effect.

Further, in this embodiment, the first non-display area includes a plurality of data wires, and two ends of the plurality of data wires are electrically connected to the plurality of data wires and the plurality of first wires, respectively; at least one of the plurality of first leads includes an inclined section, an extending direction of the inclined section intersecting both the first direction and the second direction; an included angle exists between the arrangement direction of the second pin direction of the fourth group or the fifth group and the extending direction of the inclined section, and the included angle is more than or equal to 0 degrees and less than 45 degrees. Referring to fig. 8, the extending direction of the fourth set of third pins 206 is Do, where the extending direction of the fourth set of third pins 206 is defined as the extending direction of the connecting line of the corresponding positions of the plurality of third pins 206, such as the geometric center of the third pins or the connecting line of the edge corresponding to the vertex, and the extending direction of the fourth set of third pins 206 is Do and intersects both the first direction Dx and the second direction Dy. The data lead is a fan-out area part, and the extending direction of the fan-out inclined section is crossed with the first direction Dx and the second direction Dy. In fig. 8, the extending direction of the third pins 206 of the fourth group is Do and the extending direction of the inclined section of the fan-out area is θ, where the included angle θ is greater than or equal to 0 ° and less than 45 °. By such arrangement, the space below the fan-out area can be fully utilized, and the positions of the third pins 206 can be reasonably arranged to provide a space for arranging the driving signal lines 212 and the lead wires of the third pins 206.

Further, in the present embodiment, any one of the plurality of first pins 202 and any one of the plurality of second pins 204 are identical in size and shape. Thus, the signal transmitted from the IC to the array substrate can be ensured to have the same transmission effect. And the first pins 202 and the second pins 204 can be uniformly distributed, so that excessive difference between wires is avoided. In this embodiment, the width of the driving signal line 212 is generally 5-10 times as wide as the data line 210 for transmitting the driving signal of the gate driving circuit.

Referring to fig. 9, fig. 9 is an enlarged schematic view of the first non-display area in fig. 6. In this embodiment, the same structure as in the embodiment shown in fig. 8 is partially referred to in the related description of fig. 8, and only the differences will be described in detail here. In this embodiment, the distance between any two adjacent first pins is smaller than the distance between two adjacent first pins and the second pin. In this embodiment, in the first non-display area of the array substrate, a first pin 202, a second pin 204, and a third pin 206 are disposed. The first pin 202 is disposed opposite to the third pin 206, and the second pin 204 is disposed opposite to the third pin 206 and on both sides of the first pin 202. The first pin 202, the second pin 204, and the third pin 206 are all located in the IC arrangement region 200.

In this embodiment, two non-adjacent pins of the plurality of first pins 202 are located at a distance from any one of the plurality of third pins 206 in the second direction (vertical direction in the drawing) that is smaller than a distance between at least one first pin 202 located in the middle of the two non-adjacent first pins 202 and any one of the plurality of third pins 206. That is, in the array substrate provided in this embodiment, the first pins 202 are located on two sides of the array substrate, and are closer to the third pins 206 than the middle pins.

In this embodiment, the plurality of second pins 204 are located at two sides of the plurality of first pins 202, and in the second direction, at least two second pins 204 are present, wherein a distance between the second pin 204 near the first pin 202 and any one of the plurality of third pins 206 is smaller than a distance between the second pin 204 far from the first pin 202 and any one of the plurality of third pins 206. That is, in the present embodiment, the second pin 204 located outside the first pin 202 is offset toward the display area, that is, toward the direction away from the third pin 206, the farther it is from the first pin 202. In this embodiment, the second pins 204 located at two sides of the first pin 202 are divided into a fourth group and a fifth group, and in the fourth group/the fifth group of the second pins 204, the second pins are shifted toward the display area as they are away from the center of symmetry of the array substrate, that is, the second pins are shifted toward the third pins 206 as they are away from the center of symmetry of the array substrate.

In this embodiment, the size and shape of any one of the plurality of first pins 202 and any one of the plurality of second pins 204 are the same. In this embodiment, the distance between any two adjacent first pins is smaller than the distance between two adjacent first pins and second pins, as compared with the embodiment of fig. 8.

In this embodiment, the first pin 202 is used for transmitting the data line driving signal, and the second pin 204 is used for transmitting the driving signal of the gate driving circuit. Generally, the driving signal of the gate driving circuit has a voltage greater than that of the data line, and thus the width of the driving signal line 212 is also greater than that of the data line 210. The first pin 202 and the second pin 204 have the same size and shape, and the signals transmitted by the pins are different when the pins are the same, so that electrostatic discharge or parasitic capacitance is easily generated. Thus, the distance between the first pins 202 and the second pins should be set to be greater than the distance between any adjacent two first pins 202. More specifically, the width of the driving signal line 212 is 5-10 times that of the data line 210, and thus, the interval between the adjacent first pins 202 and the second pins 204 should be 5-10 times that between the adjacent first pins 202, so as to secure static electricity and capacitance between the adjacent first pins 202 and the adjacent second pins 204. Further, since the second pins 204 transmit signals higher than the first pins 202, the distance between any adjacent second pins 204 is greater than the distance between any adjacent first pins 202. Thereby ensuring the safety of static electricity and parasitic capacitance between the adjacent second pins 204 and ensuring the display effect.

Under the condition that the first pin, the second pin and the third pin are arranged, the display performance can be guaranteed, namely, the first pin 202 and the third pin 206 are arranged closer to the display area on the premise that the first safety distance, the second safety distance and the third safety distance are guaranteed, namely, compared with the prior art, the width of the first non-display area 241 in the second direction Dy can be reduced, the display area occupation ratio can be further improved, and the display effect is improved.

Referring to fig. 10, fig. 10 is an enlarged schematic view of the first non-display area in fig. 6. In this embodiment, the same structure as in the embodiment shown in fig. 8 is partially referred to in the related description of fig. 8, and only the differences will be described in detail here. In fig. 10, elements such as data lines and driving signal lines are omitted, and only the first, second, and third pins are shown in order to more clearly illustrate the relationship among the first, second, and third pins. In this embodiment, in the first non-display area of the array substrate, a first pin 202, a second pin 204, and a third pin 206 are disposed. The first pin 202 is disposed opposite to the third pin 206, and the second pin 204 is disposed opposite to the third pin 206 and on both sides of the first pin 202. The first pin 202, the second pin 204, and the third pin 206 are all located in the IC arrangement region 200.

Further, in the present embodiment, the boundary in the second direction of one second lead 204 closest to the plurality of first leads 202 does not exceed the boundary in the second direction of the two first leads closest thereto. Please continue to refer to fig. 10. In this embodiment, the first pins 202 are arranged in two rows, and the second pins 204 are arranged in one row. The boundaries of the closest two first pins in the second direction (vertical direction in the drawing) are indicated by dashed lines in the drawing, which are defined by the upper boundary of the first pin 202 close to the display area and the lower boundary of the first pin 202 of the principle display area among the two first pins 202. In this embodiment, the upper boundary of the second pin 204 closest to the first pin 202 does not exceed the upper boundary of the first pin 202 closest to the second pin 204 in the row of the first pins 202 closest to the display area, and the lower boundary of the second pin 202 closest to the second pin 204 in the row of the first pins 202 furthest from the display area. In other embodiments of the present invention, the plurality of first pins may be arranged in a plurality of rows, and the plurality of second pins may be arranged in a plurality of rows, where the number of rows of the first pins is greater than the number of rows of the first pins. When the first pins and the second pins each include a plurality of rows, an upper boundary of one of the second pins closest to the first pins of a row closest to the display area does not exceed an upper boundary of one of the first pins closest to the second pins of a row closest to the display area; the lower boundary of one of the second pins closest to the first pin of a row farthest from the display area does not exceed the lower boundary of one of the first pins closest to the second pin of a row farthest from the display area. That is, in the embodiment of the present invention, the extension width of the plurality of first pins 202 in the second direction (vertical direction in the drawing) is larger than the extension width of the plurality of second pins 204 in the second direction. This is because, in the array substrate, the data lines are generally in the range of approximately thousands to thousands, and the driving signal lines are generally in the range of several to tens of twenty, and the first pins 202 electrically connected to the data lines are arranged in a plurality of rows in order to closely arrange the data lines. Also, referring to fig. 8 and 10, in the embodiment of the present invention, in the second direction, the direction of extraction of the first pins 202 and the data lines 210 is the direction shown in the drawing upwards, and the direction of extraction of the second pins 204 and the driving signal lines 212 is the direction shown in the drawing downwards, that is, the direction of extraction of the first pins 202 electrically connected to the plurality of data lines 210 is opposite to the direction of extraction of the plurality of second pins 204 electrically connected to the plurality of driving signal lines 212. Thus, the upper boundary of one of the second pins closest to the first pins of a row closest to the display area is set to not exceed the upper boundary of one of the first pins closest to the second pins of a row closest to the display area when the first pins and the second pins each include a plurality of rows. Therefore, a lead setting area of the fan-out area of the data line is reserved above the second pin, so that the second pin and the fan-out area of the data line keep a proper distance. A setting area of the driving signal line is reserved under the second lead, so that enough space is provided for setting the turning-out line of the driving signal line.

Referring to fig. 11, fig. 11 is an enlarged schematic view of the first non-display area in fig. 6. In this embodiment, the same structure as in the embodiment shown in fig. 8 is partially referred to in the description related to fig. 8, and only the differences will be described in detail here.

In this embodiment, in the first non-display area of the array substrate, a first pin 202, a second pin 204, and a third pin 206 are disposed. The first pin 202 is disposed opposite to the third pin 206, and the second pin 204 is disposed opposite to the third pin 206 and on both sides of the first pin 202. The first pin 202, the second pin 204, and the third pin 206 are all located in the IC arrangement region 200.

In this embodiment, the distance between two non-adjacent pins of the plurality of first pins 202 and any one of the plurality of third pins 206 in the second direction Dy is smaller than the distance between at least one first pin 202 located in the middle of the two non-adjacent pins 202 and any one of the plurality of third pins 206. That is, in the array substrate provided in this embodiment, the first pins 202 are located on two sides of the array substrate, and are closer to the third pins 206 than the middle pins.

Further, referring to fig. 11, in the present embodiment, in the first non-display area, a sixth pin 205 is further provided, and the sixth pin 205 is not electrically connected to any lead. In the IC arrangement area 200 of the first non-display area, an IC is finally required to be arranged, and corresponding pins on the IC are electrically connected with various pins of the IC arrangement area 200. Generally, various types of pins, such as the first pin 202, the second pin 204, and the third pin 206, are provided by conductors, which are typically of a certain thickness to ensure conductive connection performance. These pins, besides having the function of transmitting new energy, also have the function of supporting in the process of binding the ICs, and can be used as supporting pads to bear the ICs. Besides the pins, various leads can also play a certain bearing role. In the IC setting area, in the blank area, that is, the positions where various pins are not set and the positions where various leads are not set, the corresponding elements capable of playing a supporting role may be lacking, and after the subsequent IC binding may be caused, the IC lacks support, which causes problems of loosening, poor contact and the like of the IC.

Therefore, in the present embodiment, in the first non-display area, the sixth pin 205 is further provided, and the sixth pin 205 is not electrically connected to any other lead, and only plays a supporting role. The sixth pin 205 is prepared in the same layer as the first pin 202, the second pin 204, and the third pin 206. Further, in the present embodiment, a plurality of sixth pins 205 are included, which are located at both sides of the third pin 206 in the IC arrangement area 200 and are disposed opposite to the second pin 204. Thus, since the number of the third pins 206 is smaller, only the leads of the driving signal lines 212 are disposed below the third pins, the IC may lack support at a position opposite to the third pins 206, and the sixth pins 205 are disposed at this position, which is beneficial to improving stability after binding of subsequent ICs, and ensuring display effects.

The embodiment of the invention further comprises a display panel, wherein the display panel can comprise the array substrate according to the embodiment, and the first pin, the second pin and the third pin are arranged in the first non-display area of the array substrate. The first pin and the third pin are oppositely arranged, and the second pin is positioned on two sides of the first pin and is oppositely arranged with the third pin. The first pin, the second pin and the third pin are all positioned in the IC setting area.

In this embodiment, a distance between two non-adjacent pins of the plurality of first pins and any one of the plurality of third pins in the second direction is smaller than a distance between at least one first pin located between the two non-adjacent pins and any one of the plurality of third pins. That is, in the array substrate provided in this embodiment, the first pins are located at the pins on two sides, and are closer to the third pins than the pins located in the middle.

In this embodiment, the plurality of second pins are located at two sides of the plurality of first pins, and in the second direction, at least two second pins exist, where a distance between the second pin close to the first pin and any one of the plurality of third pins is smaller than a distance between the second pin far from the first pin and any one of the plurality of third pins. That is, in the present embodiment, the second pin located outside the first pin is offset toward the display area, that is, toward the direction away from the third pin, the further it is from the first pin. In this embodiment, the second pins on both sides of the first pin are divided into a fourth group and a fifth group, and in the second pins of the fourth group/the fifth group, the second pins are shifted toward a direction approaching the display area as they are away from the center of symmetry of the array substrate, that is, the second pins are shifted toward a direction away from the third pin as they are away from the center of symmetry of the array substrate.

The display panel provided by this embodiment, under the circumstances that sets up through first pin, second pin and third pin, can guarantee the display performance, guarantee promptly under first safe distance, second safe distance and the third safe distance's the prerequisite for first pin, third pin are close to the display area setting, promptly, compare prior art promptly, can reduce the first non-display area width in the second direction, can further improve the display area and take up an account the ratio, improve the display effect.

The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims

1. An array substrate includes:

the display area comprises a plurality of scanning lines extending along a first direction and arranged along a second direction, and a plurality of data lines extending along the second direction and extending along the first direction; adjacent two scanning lines and adjacent two data lines are crossed to form a pixel area; the display area comprises a plurality of pixel areas which are arranged in an array;

A non-display area disposed around the display area; the non-display area comprises a first non-display area, a second non-display area, a third non-display area and a fourth non-display area, wherein the first non-display area and the second non-display area are oppositely arranged, and the third non-display area and the fourth non-display area are oppositely arranged; the third non-display area and the fourth non-display area are provided with gate driving circuits, and the gate driving circuits comprise a plurality of driving signal lines;

the first non-display area comprises an IC setting area and an FPC setting area; the IC arrangement area comprises a plurality of first pins, a plurality of second pins and a plurality of third pins; the plurality of first pins are electrically connected with the plurality of data lines; the plurality of second pins are electrically connected with the plurality of driving signal lines; the first pins and the third pins are oppositely arranged; the distance between the first pins and any one of the third pins is smaller than the distance between at least one first pin positioned in the middle of the two non-adjacent first pins and any one of the third pins in the second direction; the plurality of second pins are located at two sides of the plurality of first pins, and at least two second pins are located in the second direction, wherein the distance between the second pins close to the first pins and any one of the plurality of third pins is smaller than the distance between the second pins far away from the first pins and any one of the plurality of third pins.

2. The array substrate of claim 1, wherein:

in the second direction, the lead-out direction of the plurality of first pins electrically connected with the plurality of data lines is opposite to the lead-out direction of the plurality of second pins electrically connected with the plurality of driving signal lines.

3. The array substrate of claim 1, wherein:

the plurality of first pins comprise a plurality of first groups which are arranged continuously and a plurality of second groups which are arranged continuously; in the first group and the second group, the arrangement direction of the plurality of first pins is offset toward a direction away from the display area as it is away from the symmetry center of the first non-display area.

4. The array substrate of claim 3, wherein:

the first pins further comprise a plurality of third groups which are arranged continuously, and the third groups are located between the first groups and the second groups.

5. The array substrate of claim 1, wherein:

the plurality of second pins comprise a plurality of fourth groups which are continuously arranged and a plurality of fifth groups which are continuously arranged; the fourth group and the fifth group are respectively positioned at two sides of the first pins; in the fourth group and the fifth group, the arrangement direction of the plurality of second pins is offset toward a direction approaching the display area as it is away from the center of symmetry of the first non-display area.

6. The array substrate of claim 5, wherein:

the first non-display area comprises a plurality of data leads, and two ends of the data leads are respectively and electrically connected with the data lines and the first pins; at least one of the plurality of data leads includes an inclined section, an extending direction of the inclined section intersecting both the first direction and the second direction; an included angle exists between the arrangement direction of the second pin direction of the fourth group or the fifth group and the extending direction of the inclined section, and the included angle is more than or equal to 0 degrees and less than 45 degrees.

7. The array substrate of claim 1, wherein:

the FPC setting area is provided with a plurality of fourth pins and a plurality of fifth pins, and the fourth pins are electrically connected with the third pins.

8. The array substrate of claim 1, wherein:

any one of the plurality of first pins and any one of the plurality of second pins are the same in size and shape.

9. The array substrate of claim 1, wherein:

the distance between any two adjacent first pins is smaller than the distance between the adjacent two first pins and the adjacent second pins.

10. The array substrate of claim 1, wherein:

the boundary in the second direction of one of the second pins closest to the plurality of first pins does not exceed the boundary in the second direction of the two first pins closest to the second pin.

11. The array substrate of claim 1, wherein:

and a sixth pin is also arranged in the first non-display area, and the sixth pin is not electrically connected with any lead.

12. A display panel comprising the array substrate according to any one of claims 1 to 11.