WO2024032210A1

WO2024032210A1 - Display panel and display apparatus

Info

Publication number: WO2024032210A1
Application number: PCT/CN2023/103631
Authority: WO
Inventors: 吴洋
Original assignee: 武汉华星光电半导体显示技术有限公司
Priority date: 2022-08-09
Filing date: 2023-06-29
Publication date: 2024-02-15
Also published as: CN115311975A

Abstract

Disclosed are a display panel and a display apparatus. The display panel comprises: a driving circuit layer comprising a plurality of pixel driving circuits arranged in a display area and a plurality of multiplexing circuits arranged in a first frame area, one end of one multiplexing circuit being electrically connected to the plurality of pixel driving circuits; signal terminals located in a second frame area; and a first metal layer comprising a plurality of patch cords, one ends of the patch cords being electrically connected to the signal terminals, and the other ends of the patch cords being electrically connected to the other ends of the multiplexing circuits.

Description

A display panel and display device

Technical field

The present application relates to the field of display technology, and specifically to a display panel and a display device.

Background technique

In existing display panels, the data driver chip is directly electrically connected to the data lines through signal terminals provided at the lower frame to output pixel voltages to the light-emitting pixels, which results in a large number of signal terminals. In order to reduce the number of signal terminals, in the related art, a multiplexing circuit (Demux) is set up between the data driver chip and the data line to decompose one signal channel of the data driver chip into multiple signal channels, and then communicate with each signal channel. The data lines correspond to electrical connections.

Since the current display technology is developing in the direction of high screen-to-body ratio, the lower border of the display panel needs to be smaller and smaller. The multiplexer installed on the lower border of the display panel takes up more space in the lower border, hindering the high screen-to-body ratio of the display panel. The realization of comparison.

Summary of the invention

The present application provides a display panel and a display device, which can effectively solve the technical problems of large lower frame width and dense wiring layout caused by multiplexing circuits occupying the lower frame space in existing display panels.

On the one hand, the present application provides a display panel having a display area and a frame area, and the frame area includes a first frame area and a second frame area located on opposite sides of the display area,

The display panel includes:

substrate;

A driving circuit layer is provided on one side of the substrate. The driving circuit layer includes: a plurality of pixel driving circuits provided in the display area and a plurality of multiplexing circuits provided in the first frame area. One end of the multiplexing circuit is electrically connected to a plurality of the pixel driving circuits;

A signal terminal is provided on one side of the substrate and located in the second frame area;

A first metal layer is provided on the side of the driving circuit layer away from the substrate. The first metal layer includes a plurality of transfer lines, one end of the transfer lines is electrically connected to the corresponding signal terminal. The other end of the transfer line is electrically connected to the corresponding other end of the multiplexing circuit.

Optionally, the driving circuit layer further includes: a plurality of virtual pixel driving circuits provided in the first frame area,

The display panel also includes:

A light-emitting layer is provided on a side of the first metal layer away from the substrate. The light-emitting layer includes: a plurality of light-emitting pixels provided in the display area. The pixel driving circuit is connected to the corresponding light-emitting pixel circuit. electrically connected, the virtual pixel driving circuit is not electrically connected to the light-emitting pixels in the display area;

Wherein, the dummy pixel driving circuit and the multiplexing circuit are both arranged adjacent to the pixel driving circuit in the display area.

Optionally, the multiplexing circuit is disposed in a gap area between two adjacent virtual pixel driving circuits.

Optionally, the driving circuit layer does not include a dummy pixel driving circuit, and the multiplexing circuit is arranged adjacent to the pixel driving circuit in the display area.

Optionally, the driving circuit layer also includes:

A semiconductor layer is provided on one side of the substrate. The semiconductor layer includes: a first semiconductor located in the display area and corresponding to the pixel driving circuit, located in the first frame area and connected to the multi-channel a second semiconductor provided corresponding to the multiplexing circuit;

A second metal layer is provided on a side of the semiconductor layer away from the substrate. The second metal layer includes: a first gate located in the display area and corresponding to the pixel driving circuit, located in the third a second gate in a frame area and corresponding to the multiplexing circuit;

A third metal layer is provided on a side of the second metal layer away from the substrate. The third metal layer includes: a first source electrode and a first source electrode located in the display area and corresponding to the pixel driving circuit. A drain electrode, a second source electrode and a second drain electrode located in the first frame area and corresponding to the multiplexing circuit;

Wherein, the first metal layer is disposed on a side of the third metal layer away from the substrate, and the transfer line at least partially overlaps with the pixel driving circuit.

Optionally, the driving circuit layer further includes a fourth metal layer, which is disposed on a side of the third metal layer away from the substrate. The fourth metal layer includes: a plurality of data lines in the display area. , one end of the multiplexing circuit is electrically connected to the pixel driving circuit through the data line.

Optionally, each of the multiplexing circuits includes a data bus, a plurality of data branch lines and a plurality of switch units. The data bus is provided on the second metal layer, and the data branch lines are provided on the second metal layer. The third metal layer, the switch unit includes the second semiconductor, the second gate, the second source and the second drain;

Wherein, one end of the data bus is electrically connected to the other end of the transfer line, the other end of the data bus is electrically connected to one end of a plurality of the data branch lines, and the other end of the data branch line is electrically connected. The second drain electrode is electrically connected to the second source electrode, and the second drain electrode is electrically connected to the data line.

Optionally, the driving circuit layer further includes a fifth metal layer, the fifth metal layer is disposed on a side of the second metal layer away from the substrate, and the third metal layer is disposed on the fifth the side of the metal layer away from the substrate;

Each of the multiplexing circuits further includes a plurality of electrostatic protection circuits, and the second drain is electrically connected to the data line through the electrostatic protection circuits;

Wherein, the electrostatic protection circuit includes a first part, and in two adjacent electrostatic protection circuits in the multiplexing circuit, the first part of one of the electrostatic protection circuits is located on the second metal layer, and the first part of the other electrostatic protection circuit is located on the fifth metal layer.

Optionally, each of the multiplexing circuits includes a data bus, four data branch lines and four switch units, wherein,

The light-emitting pixels include: a first light-emitting pixel with a first light-emitting color, a second light-emitting pixel with a second light-emitting color, and a third light-emitting pixel with a third light-emitting color,

Wherein, the four data branch lines in each of the multiplexing circuits respectively pass through different data lines and communicate with one column of the first light-emitting pixels, one column of the second light-emitting pixels, and one column of the third light-emitting pixels. The pixels and the second light-emitting pixels in another column are electrically connected.

On the other hand, the present application provides a display device, which includes a housing and any of the above display panels, wherein the housing has an accommodation space, and the display panel is disposed on the within the accommodation space.

beneficial effects

The present application provides a display panel and a display device. In this application, a multiplexing circuit is arranged in a first frame area, and a signal terminal arranged in the second frame area is connected to a multiplex circuit arranged in the first frame area through an adapter wire. The circuit multiplexer is electrically connected, thereby greatly reducing the frame width and wiring density of the second frame area, and improving the screen-to-body ratio and production yield of the display panel.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

FIG. 1 is a schematic plan view of a pixel driving circuit and a multiplexing circuit electrically connected through data lines in a display panel according to Embodiment 1 of the present application.

FIG. 2 is a schematic plan view illustrating the electrical connection between signal terminals and multiplexing circuits in a display panel through adapter wires according to Embodiment 1 of the present application.

FIG. 3 is a schematic diagram of the film structure of the display panel provided in Embodiment 1 of the present application.

FIG. 4 is a schematic plan view of a multiplexing circuit provided in Embodiment 1 of the present application.

FIG. 5 is a schematic plan view of a multiplexing circuit provided in Embodiment 2 of the present application.

Embodiments of the invention

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of this application. In addition, it should be understood that the specific embodiments described here are only used to illustrate and explain the application, and are not used to limit the application. In this application, unless otherwise specified, the directional words used such as "upper" and "lower" usually refer to the upper and lower positions of the device in actual use or working conditions, specifically the direction of the drawing in the drawings. ; while “inside” and “outside” refer to the outline of the device.

The following disclosure provides many different embodiments or examples for implementing the various structures of the present application. To simplify the disclosure of the present application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the application. Furthermore, this application may repeat reference numbers and/or reference letters in different examples, such repetition being for the purposes of simplicity and clarity and does not by itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, this application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials. Detailed descriptions are provided below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

Embodiment 1

FIG. 1 is a schematic plan view of a pixel drive circuit and a multiplexing circuit in a display panel provided by Embodiment 1 of the present application and are electrically connected through data lines; FIG. 2 is a schematic diagram of signal terminals and multiplexing circuits in a display panel provided by Embodiment 1 of the present application. A schematic plan view of a circuit electrically connected through an adapter wire; FIG. 3 is a schematic diagram of the film structure of a display panel provided by an embodiment of the present application. Referring to Figures 1, 2 and 3, Embodiment 1 of the present application provides a display panel. The display panel has a display area 01 and a frame area 02. The frame area 02 includes a frame located opposite to the display area 01. On both sides of the first frame area 021 and the second frame area 022, the display panel includes: a substrate 10; and a drive circuit layer 20, which is provided on one side of the substrate 10. The drive circuit layer 20 includes: There are a plurality of pixel driving circuits 21 in the display area 01 and a plurality of multiplexing circuits 22 provided in the first frame area 021. One end of one of the multiplexing circuits 22 is electrically connected to the plurality of pixel driving circuits 21. The signal terminal A is provided on one side of the substrate 10 and located in the second frame area 022; the first metal layer 30 is provided on the side of the driving circuit layer 20 away from the substrate 10, so The first metal layer 30 includes a plurality of transfer wires 31. One end of the transfer wire 31 is electrically connected to the corresponding signal terminal A, and the other end of the transfer wire 31 is connected to the corresponding multiplexing circuit. The other end of 22 is electrically connected.

In the prior art, the signal terminal A is used to receive the data signal output by the data driver chip (source IC), and the signal terminal A and the multiplexing circuit are both arranged in the second frame area, so that the second frame area The frame width and trace density are both larger.

In the display panel provided by this application, the adapter line 31 spans the second frame area 022, the display area 01 and the first frame area 021, and is connected to the second frame area 022 respectively. The signal terminal A is electrically connected to the multiplexing circuit 22 of the first frame area 021, so that the multiplexing circuit 22 can be disposed in the second frame area 022 of the display panel, And the data signal output by the signal terminal A is received through the adapter wire 31, thereby greatly reducing the frame width and wiring density of the second frame area 022 while ensuring the normal transmission of the data signal, and improving the Display panel screen-to-body ratio and production yield.

Specifically, the first frame area 021 is located on the upper side of the display area 01 , and the second frame area 022 is located on the lower side of the display area 01 . The second frame area 022 is provided with the signal terminal A, gate drive circuit windings, VDD lines, test lines and other lines. Therefore, the circuit layout of the second frame area 022 is relatively dense. This application passes The multiplexing circuit 22 is moved to the first frame area 021 with a relatively loose circuit layout, thereby avoiding the second frame area 022 caused by arranging the multiplexing circuit 22 in the second frame area 022 Problems with large width and too dense line layout.

Further, the third frame area 023 is located on the left side of the display area 01 , and the fourth frame area 024 is located on the right side of the display area 01 . A gate driving circuit is provided on at least one of the third frame region 023 and the fourth frame region 024, and the gate driving circuit winding is electrically connected to the gate driving circuit.

In some embodiments of the present application, the driving circuit layer 20 further includes: a plurality of virtual pixel driving circuits (not shown in the figure) provided in the first frame area 021, and the display panel further includes: light emitting Layer 404 is provided on the side of the first metal layer 30 away from the substrate 10 . The light-emitting layer 404 includes: a plurality of light-emitting pixels provided in the display area 01 . The pixel driving circuit 21 and the corresponding The light-emitting pixels are electrically connected, and the dummy pixel driving circuit is not electrically connected to the light-emitting pixels in the display area 01; wherein, the dummy pixel driving circuit and the multiplexing circuit 22 are adjacent to the The pixel driving circuit 21 of the display area 01 is provided.

In the display panel provided by the present application, the virtual pixel driving circuit is arranged adjacent to the pixel driving circuit 21 of the display area 01, and its function is to prevent external static electricity from directly damaging the pixel driving circuit of the display area 01. circuit 21, and during the preparation process of the display panel, the patterned structure of the pixel driving circuit 21 in the display area 01 can be etched more uniformly to ensure film formation quality. In this application, the dummy pixel driving circuit and the multiplexing circuit 22 are both arranged adjacent to the pixel driving circuit 21 in the display area 01, so that the multiplexing circuit 22 can also play the role of It has the effect of preventing external static electricity from directly damaging the pixel driving circuit 21 of the display area 01 and making the patterned structure of the pixel driving circuit 21 of the display area 01 etched more uniformly.

Further, the multiplexing circuit 22 is disposed in a gap area between two adjacent virtual pixel driving circuits.

In the display panel provided by this application, since the virtual pixel driving circuit will occupy part of the space of the first frame area 021, this application disposes the multiplexing circuit 22 in two adjacent areas. In the gap area between the dummy pixel driving circuits, the gap area between the two adjacent dummy pixel driving circuits can be fully utilized without increasing the width of the first frame area 021, so as to The setting of the multiplexing circuit 22 is completed.

Of course, this application does not require that the first frame area 021 must be provided with the virtual pixel driving circuit. In other embodiments of the application, the driving circuit layer 20 does not include a virtual pixel driving circuit. The multiplexing circuit 22 is disposed adjacent to the pixel driving circuit 21 of the display area 01 . The multiplexing circuit 22 adjacent to the pixel driving circuit 21 can also prevent external static electricity from directly damaging the pixel driving circuit 21 of the display area 01 and causing the pixels of the display area 01 to be damaged. The patterned structure of the driving circuit 21 is etched more uniformly, and therefore, the dummy pixel driving circuit in the first frame area 021 can be omitted.

FIG. 4 is a schematic plan view of the multiplexing circuit in the first frame area provided by Embodiment 1 of the present application. Referring to FIGS. 3 and 4 , in some embodiments of the present application, the driving circuit layer 20 further includes: a first via hole 24 , through which the transfer line 31 communicates with the multiplexed wire 31 . The multiplexing circuit 22 is electrically connected. Wherein, in order to arrange the multiplexing circuit 22 close to the pixel driving circuit 21 of the display area 01 , the first via hole 24 is arranged in the multiplexing circuit 22 away from the display area 01 side.

In some embodiments of the present application, the driving circuit layer 20 further includes: a semiconductor layer 203, which is disposed on one side of the substrate 10. The semiconductor layer 203 includes: located in the display area 01 and connected to the pixel. The first semiconductor provided corresponding to the driving circuit 21 is located in the first frame area 021 and the second semiconductor provided corresponding to the multiplexing circuit 22; the second metal layer 205 is provided away from the semiconductor layer 203. On one side of the substrate 10, the second metal layer 205 includes: a first gate located in the display area 01 and corresponding to the pixel driving circuit 21, a first gate located in the first frame area 021 and connected to the multi-pixel drive circuit 21. The second gate electrode is provided correspondingly to the multiplexing circuit 22; a third metal layer 213 is provided on the side of the second metal layer 205 away from the substrate 10, and the third metal layer 213 includes: on the display The first source electrode and the first drain electrode in the region 01 and corresponding to the pixel driving circuit 21, the second source electrode and the second drain electrode in the first frame region 021 and corresponding to the multiplexing circuit 22. Drain; wherein, the first metal layer 30 is provided on a side of the third metal layer 213 away from the substrate 10 , and the transfer line 31 is at least partially overlapped with the pixel driving circuit 21 .

In some embodiments of the present application, the driving circuit layer 20 further includes a fourth metal layer 215, which is disposed on the side of the third metal layer 213 away from the substrate 10. The fourth metal layer 215 includes: Among the plurality of data lines 23 in the display area 01, one end of the multiplexing circuit 22 is electrically connected to the pixel driving circuit 21 through the data lines 23.

Continuing to refer to Figures 3 and 4, in some embodiments of the present application, each multiplexing circuit 22 includes a data bus 221, a plurality of data branch lines 222 and a plurality of switch units 223. The data bus 221 is provided on the second metal layer 205, the data branch line 222 is provided on the third metal layer 213, and the switch unit 223 includes the second semiconductor, the second gate, the second The source electrode and the second drain electrode; wherein, one end of the data bus 221 is electrically connected to the other end of the transfer line 31 , and the other end of the data bus 221 is connected to a plurality of the data branch lines 222 One end is electrically connected, the other end of the data branch line 222 is electrically connected to the second source, and the second drain is electrically connected to the data line 23 .

Further, one end of the data bus 221 is electrically connected to the other end of the adapter line 31 through the first via hole 24 .

In some embodiments of the present application, each of the multiplexing circuits 22 includes one data bus 221 , four data branch lines 222 and four switch units 223 .

Among them, in conventional technology, each multiplexing circuit only includes three data branch lines and three switch units. That is, the multiplexing circuit 22 provided by the present application has a larger number of wirings and a more complex structure. For complexity. In this application, the multiplexing circuit 22 with a larger number of wirings and a more complex structure is arranged in the first frame area 021, and the multiplexing circuit 22 is adjacent to all parts of the display area 01. The pixel driving circuit 21 is configured to greatly reduce the frame width and wiring density of the second frame area 022, improve the screen-to-body ratio and production yield of the display panel, and at the same time prevent direct damage to the second frame area 022 by external static electricity. The pixel driving circuit 21 in the display area 01 and the patterned structure of the pixel driving circuit 21 in the display area 01 are etched more uniformly.

In some embodiments of the present application, the light-emitting pixels include: a first light-emitting pixel with a first light-emitting color, a second light-emitting pixel with a second light-emitting color, and a third light-emitting pixel with a third light-emitting color, wherein each The four data branch lines 222 in each of the multiplexing circuits 22 respectively pass through different data lines 23 and communicate with a column of the first luminescent pixels, a column of the second luminescent pixels, and a column of the third luminescent pixels. The pixels and the second light-emitting pixels in another column are electrically connected.

Further, the luminescent color of the first luminescent pixel is red, the luminescent color of the second luminescent pixel is green, and the luminescent color of the third luminescent pixel is blue.

Further, the type of the display panel is, for example, an organic light-emitting diode (OLED) display panel. Of course, this application does not limit the type of the display panel. In other embodiments of the application, the type of the display panel may also be a liquid crystal display panel or an inorganic light-emitting diode display panel.

The film layer structure of the display area 01 of the display panel will be further introduced below. Continuing to refer to FIG. 3 , in some embodiments of the present application, the substrate 10 includes a first substrate substrate 101 , a first buffer layer 102 and a second substrate substrate 103 that are stacked in sequence. The drive circuit layer 20 includes The light-shielding metal layer 201, the second buffer layer 202, the semiconductor layer 203, the first gate insulating layer 204, and the The second metal layer 205, the second gate insulation layer 206, the fifth metal layer 207, the interlayer dielectric layer 208, the active layer 209, the third gate insulation layer 210, the sixth metal layer 211, the passivation layer 212, The third metal layer 213, the first flat layer 214, the fourth metal layer 215 and the second flat layer 216; the first metal layer 30 is disposed on the second flat layer 216 away from the substrate. 10; the surface of the first metal layer 30 on the side facing away from the substrate 10 is covered with a third flat layer 301; the third flat layer 301 on the side facing away from the substrate 10 A light-emitting functional layer 40 is formed on the surface. The light-emitting functional layer 40 includes a first electrode layer 401 and a pixel definition layer that are sequentially stacked in the direction of the second base substrate 103 away from the first base substrate 101. 402. Spacer layer 403, the light-emitting layer 404 and the cathode layer 405. Of course, in other embodiments of the present application, the pixel definition layer 402 and the spacer layer 403 can be formed using one film forming process.

Further, the first via hole 24 penetrates the second planarization layer 216, the first planarization layer 214, the passivation layer 212, the third gate insulating layer 210, and the interlayer dielectric layer. 208 and the second gate insulating layer 206, so that the transfer line 31 located in the first metal layer 30 passes through the first via hole 24 and the data located in the second metal layer Bus 221 is electrically connected. It should be noted that the first via hole 24 is formed through at least one etching process.

On the other hand, the present application also provides a display device, which includes a housing and any of the above display panels, wherein the housing has an accommodation space, and the display panel is disposed on the display panel. described in the accommodation space.

Embodiment 2

FIG. 5 is a schematic plan view of the multiplexing circuit in the first frame area provided in Embodiment 2 of the present application. Referring to FIGS. 1-3 and 5 , Embodiment 2 of the present application provides a display panel. The display panel has a display area 01 and a frame area 02 . The frame area 02 includes two opposite sides of the display area 01 . The display panel includes: a substrate 10; a drive circuit layer 20, which is provided on one side of the substrate 10; the drive circuit layer 20 includes: There are a plurality of pixel driving circuits 21 in the display area 01 and a plurality of multiplexing circuits 22 provided in the first frame area 021. One end of one of the multiplexing circuits 22 is electrically connected to the plurality of pixel driving circuits 21. Connection; signal terminal A, disposed on one side of the substrate 10 and located in the second frame area 022; first metal layer 30, disposed on the side of the drive circuit layer 20 away from the substrate 10, the The first metal layer 30 includes a plurality of transfer wires 31 , one end of the transfer wire 31 is electrically connected to the corresponding signal terminal A, and the other end of the transfer wire 31 is electrically connected to the corresponding multiplexing circuit 22 The other end is electrically connected.

The structure of the display panel provided in Embodiment 2 of the present application is similar to that of the display panel in Embodiment 1, and the same parts will not be described again in this application. The difference is that the driving circuit layer 20 also includes a fifth metal layer 207 , the fifth metal layer 207 is disposed on the side of the second metal layer 205 away from the substrate 10 , and the third metal layer 213 is disposed on the side of the fifth metal layer 207 away from the substrate 10 On one side; each of the multiplexing circuits 22 also includes a plurality of electrostatic protection circuits 224, and the second drain is electrically connected to the data line 23 through the electrostatic protection circuits 224; wherein, the electrostatic The protection circuit 224 includes a first part 2241. In the two adjacent electrostatic protection circuits 224 in the multiplexing circuit 22, the first part 2241 of one of the electrostatic protection circuits 224 is located in the second In the metal layer 205 , the first part 2241 of the other electrostatic protection circuit 224 is located in the fifth metal layer 207 .

In the display panel provided by this application, since each of the multiplexing circuits 22 also includes a plurality of electrostatic protection circuits 224, the arrangement of the electrostatic protection circuits 224 can further enhance the performance of the multiplexing circuits 22. Static electricity protection capability. Moreover, among the two adjacent electrostatic protection circuits 224 of the multiplexing circuit 22, the first portion 2241 of one of the electrostatic protection circuits 224 is located on the second metal layer 205, and the other one is located on the second metal layer 205. The first part 2241 of the electrostatic protection circuit 224 is located on the fifth metal layer 207, thereby further improving the electrostatic protection capability of the electrostatic protection circuit 224 and reducing the number of adjacent two parts of the multiplexing circuit 22. interference of the electrostatic protection circuit 224.

To sum up, the present application provides a display panel and a display device. The display panel has a display area and a frame area. The frame area includes a first frame area and a second frame located on opposite sides of the display area. area, the display panel includes: a substrate; a driving circuit layer provided on one side of the substrate; the driving circuit layer includes: a plurality of pixel driving circuits provided in the display area and a first frame area. A plurality of multiplexing circuits, one end of which is electrically connected to a plurality of pixel driving circuits; a signal terminal, which is provided on one side of the substrate and located in the second frame area; A first metal layer is provided on the side of the driving circuit layer away from the substrate. The first metal layer includes a plurality of transfer lines, one end of the transfer lines is electrically connected to the corresponding signal terminal. The other end of the transfer line is electrically connected to the corresponding other end of the multiplexing circuit. In this application, the multiplexing circuit is arranged in the first frame area, and the signal terminal arranged in the second frame area is electrically connected to the multiplexer arranged in the first frame area through a transfer line, thereby greatly reducing the number of The frame width and wiring density of the second frame area improve the screen-to-body ratio and production yield of the display panel.

The above is a detailed introduction to a display panel and a display device provided by the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the present application. The method and its core idea; at the same time, for those skilled in the art, there will be changes in the specific implementation and scope of application based on the ideas of this application. In summary, the content of this specification should not be understood as a reference to this application. Application restrictions.

Claims

A display panel, wherein the display panel has a display area and a frame area, and the frame area includes a first frame area and a second frame area located on opposite sides of the display area,

The display panel includes:

substrate;

A driving circuit layer is provided on one side of the substrate. The driving circuit layer includes: a plurality of pixel driving circuits provided in the display area and a plurality of multiplexing circuits provided in the first frame area. One end of the multiplexing circuit is electrically connected to a plurality of the pixel driving circuits;

A signal terminal is provided on one side of the substrate and located in the second frame area;

A first metal layer is provided on the side of the driving circuit layer away from the substrate. The first metal layer includes a plurality of transfer lines, one end of the transfer lines is electrically connected to the corresponding signal terminal. The other end of the transfer line is electrically connected to the corresponding other end of the multiplexing circuit.
The display panel according to claim 1, wherein the driving circuit layer further includes: a plurality of virtual pixel driving circuits provided in the first frame area,

The display panel also includes:

A light-emitting layer is provided on a side of the first metal layer away from the substrate. The light-emitting layer includes: a plurality of light-emitting pixels provided in the display area. The pixel driving circuit is connected to the corresponding light-emitting pixel circuit. electrically connected, the virtual pixel driving circuit is not electrically connected to the light-emitting pixels in the display area;

Wherein, the dummy pixel driving circuit and the multiplexing circuit are both arranged adjacent to the pixel driving circuit in the display area.
The display panel according to claim 2, wherein the multiplexing circuit is disposed in a gap area between two adjacent dummy pixel driving circuits.
The display panel of claim 1, wherein the driving circuit layer does not include a dummy pixel driving circuit, and the multiplexing circuit is disposed adjacent to the pixel driving circuit in the display area.
The display panel according to claim 1, wherein the driving circuit layer further includes:

A semiconductor layer is provided on one side of the substrate. The semiconductor layer includes: a first semiconductor located in the display area and corresponding to the pixel driving circuit, located in the first frame area and connected to the multi-channel A second semiconductor provided corresponding to the multiplexing circuit;

A second metal layer is provided on a side of the semiconductor layer away from the substrate. The second metal layer includes: a first gate located in the display area and corresponding to the pixel driving circuit, located in the third a second gate in a frame area and corresponding to the multiplexing circuit;

A third metal layer is provided on a side of the second metal layer away from the substrate. The third metal layer includes: a first source electrode and a first source electrode located in the display area and corresponding to the pixel driving circuit. A drain electrode, a second source electrode and a second drain electrode located in the first frame area and corresponding to the multiplexing circuit;

Wherein, the first metal layer is disposed on a side of the third metal layer away from the substrate, and the transfer line at least partially overlaps with the pixel driving circuit.
The display panel of claim 5, wherein the driving circuit layer further includes a fourth metal layer disposed on a side of the third metal layer away from the substrate, and the fourth metal layer includes: Among the multiple data lines in the display area, one end of the multiplexing circuit is electrically connected to the pixel driving circuit through the data lines.
The display panel according to claim 6, wherein each of the multiplexing circuits includes a data bus, a plurality of data branch lines and a plurality of switch units, the data bus being disposed on the second metal layer, The data branch line is provided on the third metal layer, and the switch unit includes the second semiconductor, the second gate, the second source and the second drain;

Wherein, one end of the data bus is electrically connected to the other end of the transfer line, the other end of the data bus is electrically connected to one end of a plurality of the data branch lines, and the other end of the data branch line is electrically connected. The second drain electrode is electrically connected to the second source electrode, and the second drain electrode is electrically connected to the data line.
The display panel according to claim 7, wherein the driving circuit layer further includes a fifth metal layer, the fifth metal layer is disposed on a side of the second metal layer away from the substrate, and the third The metal layer is disposed on a side of the fifth metal layer away from the substrate;

Each of the multiplexing circuits further includes a plurality of electrostatic protection circuits, and the second drain is electrically connected to the data line through the electrostatic protection circuits;

Wherein, the electrostatic protection circuit includes a first part, and in two adjacent electrostatic protection circuits in the multiplexing circuit, the first part of one of the electrostatic protection circuits is located on the second metal layer, and the first part of the other electrostatic protection circuit is located on the fifth metal layer.
The display panel according to claim 6, wherein each of the multiplexing circuits includes one data bus, four data branch lines and four switch units, wherein,

The light-emitting pixels include: a first light-emitting pixel with a first light-emitting color, a second light-emitting pixel with a second light-emitting color, and a third light-emitting pixel with a third light-emitting color,

Wherein, the four data branch lines in each of the multiplexing circuits respectively pass through different data lines and communicate with one column of the first light-emitting pixels, one column of the second light-emitting pixels, and one column of the third light-emitting pixels. The pixels and the second light-emitting pixels in another column are electrically connected.
The display panel according to claim 1, wherein the driving circuit layer further includes a first via hole, and the transfer line is electrically connected to the multiplexing circuit through the first via hole, wherein the The first via hole is provided on a side of the multiplexing circuit away from the display area.
A display device, wherein the display device includes a housing and a display panel, wherein the housing has an accommodating space, the display panel is disposed in the accommodating space, and the display panel has a display area and a frame area, the frame area including a first frame area and a second frame area located on opposite sides of the display area,

The display panel includes:

substrate;

A driving circuit layer is provided on one side of the substrate. The driving circuit layer includes: a plurality of pixel driving circuits provided in the display area and a plurality of multiplexing circuits provided in the first frame area. One end of the multiplexing circuit is electrically connected to a plurality of the pixel driving circuits;

A signal terminal is provided on one side of the substrate and located in the second frame area;

A first metal layer is provided on the side of the driving circuit layer away from the substrate. The first metal layer includes a plurality of transfer lines, one end of the transfer lines is electrically connected to the corresponding signal terminal. The other end of the transfer line is electrically connected to the corresponding other end of the multiplexing circuit.
The display device according to claim 11, wherein the driving circuit layer further includes: a plurality of virtual pixel driving circuits provided in the first frame area,

The display panel also includes:

A light-emitting layer is provided on a side of the first metal layer away from the substrate. The light-emitting layer includes: a plurality of light-emitting pixels provided in the display area. The pixel driving circuit is connected to the corresponding light-emitting pixel circuit. electrically connected, the virtual pixel driving circuit is not electrically connected to the light-emitting pixels in the display area;

Wherein, the dummy pixel driving circuit and the multiplexing circuit are both arranged adjacent to the pixel driving circuit in the display area.
The display device according to claim 12, wherein the multiplexing circuit is disposed in a gap area between two adjacent dummy pixel driving circuits.
The display device according to claim 11, wherein the driving circuit layer does not include a dummy pixel driving circuit, and the multiplexing circuit is disposed adjacent to the pixel driving circuit in the display area.
The display device according to claim 11, wherein the driving circuit layer further includes:

A semiconductor layer is provided on one side of the substrate. The semiconductor layer includes: a first semiconductor located in the display area and corresponding to the pixel driving circuit, located in the first frame area and connected to the multi-channel A second semiconductor provided corresponding to the multiplexing circuit;

A second metal layer is provided on a side of the semiconductor layer away from the substrate. The second metal layer includes: a first gate located in the display area and corresponding to the pixel driving circuit, located in the third a second gate in a frame area and corresponding to the multiplexing circuit;

A third metal layer is provided on a side of the second metal layer away from the substrate. The third metal layer includes: a first source electrode and a first source electrode located in the display area and corresponding to the pixel driving circuit. A drain electrode, a second source electrode and a second drain electrode located in the first frame area and corresponding to the multiplexing circuit;

Wherein, the first metal layer is disposed on a side of the third metal layer away from the substrate, and the transfer line at least partially overlaps with the pixel driving circuit.
The display device according to claim 15, wherein the driving circuit layer further includes a fourth metal layer disposed on a side of the third metal layer away from the substrate, and the fourth metal layer includes: Among the multiple data lines in the display area, one end of the multiplexing circuit is electrically connected to the pixel driving circuit through the data lines.
The display device according to claim 16, wherein each of the multiplexing circuits includes a data bus, a plurality of data branch lines and a plurality of switch units, the data bus being disposed on the second metal layer, The data branch line is provided on the third metal layer, and the switch unit includes the second semiconductor, the second gate, the second source and the second drain;

Wherein, one end of the data bus is electrically connected to the other end of the transfer line, the other end of the data bus is electrically connected to one end of a plurality of the data branch lines, and the other end of the data branch line is electrically connected. The second drain electrode is electrically connected to the second source electrode, and the second drain electrode is electrically connected to the data line.
The display device according to claim 17, wherein the driving circuit layer further includes a fifth metal layer, the fifth metal layer is disposed on a side of the second metal layer away from the substrate, and the third The metal layer is disposed on a side of the fifth metal layer away from the substrate;

Each of the multiplexing circuits further includes a plurality of electrostatic protection circuits, and the second drain is electrically connected to the data line through the electrostatic protection circuits;

Wherein, the electrostatic protection circuit includes a first part, and in two adjacent electrostatic protection circuits in the multiplexing circuit, the first part of one of the electrostatic protection circuits is located on the second metal layer, and the first part of the other electrostatic protection circuit is located on the fifth metal layer.
The display device according to claim 16, wherein each of the multiplexing circuits includes one data bus, four data branch lines and four switch units, wherein,

The light-emitting pixels include: a first light-emitting pixel with a first light-emitting color, a second light-emitting pixel with a second light-emitting color, and a third light-emitting pixel with a third light-emitting color,

Wherein, the four data branch lines in each of the multiplexing circuits respectively pass through different data lines and communicate with one column of the first light-emitting pixels, one column of the second light-emitting pixels, and one column of the third light-emitting pixels. The pixels and the second light-emitting pixels in another column are electrically connected.
The display device according to claim 11, wherein the driving circuit layer further includes a first via hole, and the transfer line is electrically connected to the multiplexing circuit through the first via hole, wherein the The first via hole is provided on a side of the multiplexing circuit away from the display area.