CN110197636A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN110197636A CN110197636A CN201910580584.7A CN201910580584A CN110197636A CN 110197636 A CN110197636 A CN 110197636A CN 201910580584 A CN201910580584 A CN 201910580584A CN 110197636 A CN110197636 A CN 110197636A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The embodiment of the invention provides a kind of display panel and display devices, it include at least one the first transistor in multiple transistors of the demultplexer circuit of the display panel, the first transistor includes two coordination electrodes, the second coordination electrode in two coordination electrodes can be connect by the first connecting line with the first coordination electrode, and first coordination electrode be electrically connected with a clock control signal line by the second connecting line, so as to increase the length of the first transistor in the orientation of data signal line, be conducive to reduce the width of the first transistor on data signal line extending direction, to reduce the area occupied of demultplexer circuit, and then reduce the size of non-display area on data signal line extending direction, be conducive to the narrow frame of display panel.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of display panel and display devices.
Background technique
There are multiple pixels in active matrix display panel, wherein the pixel with a line can share a scan signal line,
The pixel of same row can share a data signal wire, and each pixel is provided with driving transistor, the scan signal line energy
Enough scanning signals for providing driving chip sequentially input each row pixel, are opened with controlling the driving transistor of respective pixel, and
Inputted in the pixel by the data voltage signal that data signal line provides driving chip so that the pixel can show it is luminous.
With the development of display technology, the requirement to the display effect of display panel is higher and higher, pixel in display panel
Quantity is more and more, and the quantity of data signal line is more and more, and setting data voltage output pin is more and more in driving chip,
The frame area for causing driving chip to occupy is increasing.To reduce the frame area that driving chip occupies, the prior art passes through
Demultplexer circuit is set in display panel, and the method driven by timesharing realizes a data voltage of driving chip
Output pin can provide data voltage signal to multiple pixels of same a line respectively.
But since demultplexer circuit is provided with multiple transistors as switch unit, a transistor corresponding one
Data signal wire.When pixel quantity further increases in display device, in demultplexer circuit the quantity of transistor with
Increase so that the size of demultplexer circuit increases, occupied frame area increases, and is unfavorable for display device narrow frame
Design requirement.
Summary of the invention
The embodiment of the present invention provides a kind of display panel and display device, so as to reduce demultplexer electricity in display panel
The size on road is conducive to the screen accounting for improving display panel, and then improve display device to reduce the frame of display panel
Display effect.
In a first aspect, the embodiment of the invention provides a kind of display panels, comprising: viewing area and around the viewing area
Non-display area；The viewing area is provided with a plurality of data signal line arranged along first direction and extend in a second direction, wherein
The first direction and the second direction are intersected；The non-display area is provided with multiple demultplexer circuits and a plurality of clock
Control signal wire；
Each demultplexer circuit includes multiple transistors；It is each in the same demultplexer circuit
The input electrode of the transistor is electrically connected with a data signal lead；Each institute in the same demultplexer circuit
The coordination electrode for stating transistor is electrically connected from the different clock control signal lines respectively；The same demultplexer circuit
In the output electrode of each transistor be electrically connected respectively from the different data signal line；
It wherein, include at least one the first transistor in multiple transistors in any demultplexer circuit；Institute
The coordination electrode for stating the first transistor includes the first coordination electrode and the second coordination electrode, and the first transistor includes the first company
Wiring；First coordination electrode is connect with second coordination electrode by first connecting line, and first control
Electrode is electrically connected by the second connecting line with a clock control signal line；
First connecting line is located at first coordination electrode and second coordination electrode close to the viewing area
Side, the clock control signal line are located at side of the first transistor far from the viewing area.
Second aspect, the embodiment of the invention provides a kind of display devices, comprising: above-mentioned display panel.
The embodiment of the invention provides a kind of display panel and display devices, are distributed by the way that multichannel is arranged in display panel
Device circuit, and it is electrically connected the coordination electrode of all transistors of demultplexer circuit with same data signal leads, so that
All transistors of demultplexer circuit can receive the data-signal that driving chip is sent by a data signal lead；
Meanwhile the output end of the different crystal pipe of demultplexer circuit is electrically connected from different data signal lines, demultplexer
The different coordination electrodes of the different crystal pipe of circuit are electrically connected from different clock control signal lines, to realize demultplexer electricity
The Time-sharing control of different crystal pipe in road can make driving chip successively send data-signal to different data signal wire, thus
The data signal pin quantity that driving chip can be reduced, reduces the area occupied of driving chip；In addition, demultplexer circuit
Multiple transistors in include at least one the first transistor, the first transistor include two coordination electrodes, this two control
The second coordination electrode in electrode can be connect by the first connecting line with the first coordination electrode, and the first coordination electrode passes through the
Two connecting lines are electrically connected with a clock control signal line, brilliant so as to increase by first in the orientation of data signal line
The length of body pipe is conducive to the width for reducing the first transistor on data signal line extending direction, to reduce demultplexer electricity
The area occupied on road, and then reduce the size of non-display area on data signal line extending direction, be conducive to the narrow side of display panel
Frame.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of the demultplexer circuit of prior art；
Fig. 2 is that the embodiment of the present invention provides a kind of overlooking structure diagram of display panel；
Fig. 3 is a kind of structural schematic diagram of demultplexer circuit provided in an embodiment of the present invention；
Fig. 4 is a kind of equivalent circuit diagram of demultplexer circuit corresponding with Fig. 3；
Fig. 5 is a kind of driver' s timing figure of demultplexer circuit corresponding with Fig. 3；
Fig. 6 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Fig. 7 is a kind of part film schematic diagram of a layer structure of display panel provided in an embodiment of the present invention；
Fig. 8 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Fig. 9 is the structural schematic diagram of the demultplexer circuit of another prior art；
Figure 10 corresponds to a kind of equivalent circuit diagram of demultplexer circuit of Fig. 8；
Figure 11 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 12 is a kind of the schematic diagram of the section structure in Figure 11 along the section A-A'；
Figure 13 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 14 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention；
Figure 15 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Fig. 1 is a kind of structural schematic diagram of the demultplexer circuit of prior art.Such as Fig. 1, demultplexer circuit packet
Include three transistors T01, T02 and T03, three transistors T01, T02 and the T03 respectively correspond including a coordination electrode g01,
G02 and g03, and the input electrode of three transistors T01, T02 and the T03 pass through same data signal leads and are electrically connected to one
A data signal pin Vn；The coordination electrode of three transistors T01, T02 and the T03 pass through different clock control signals respectively
Line is electrically connected with different clocks control signal pins, to receive different clocks control signal ckh1, ckh2 and ckh3；Simultaneously this three
The output electrode of a transistor T01, T02 and T03 are electrically connected from different data signal lines respectively.In demultplexer circuit
Three transistors T01, T02 and T03 can receive different clock control signal ckh1, ckh2 and ckh3, at different times
Conducting so that data signal pin Vn transmission data-signal Data pass sequentially through in a serial fashion three transistor T01,
T02 and T03 and data signal line DataR, DataG and DataB are input to different pixels, realize timesharing driving.Wherein,
The sub-pixel of three different luminescent colors can form a pixel unit, and the sub-pixel of this three different luminescent colors is, for example,
Red sub-pixel, green sub-pixels and blue subpixels.Correspondingly, data signal line DataR, DataG and DataB can be with one
Red sub-pixel, green sub-pixels and the blue subpixels of a pixel unit are electrically connected.
But in the prior art, transistor T01, T02 and T03 of demultplexer circuit are arranged in X direction, along the side Y
To extension, such transistor T01, T02 and T03 have biggish size W0 in the Y direction, to increase the ruler of demultplexer
It is very little, it is unfavorable for the narrow frame of display panel.
In order to solve the above technical problems, the embodiment of the invention provides a kind of display panels.Fig. 2 is that the embodiment of the present invention mentions
For a kind of overlooking structure diagram of display panel.Such as Fig. 2, display panel 100 is including viewing area 110 and surrounds viewing area 110
Non-display area 120.The viewing area 110 of display panel 100 be provided with it is a plurality of along first direction X arrangement and Y prolongs in a second direction
Data signal line 51 and first direction X and the second direction Y stretched intersects.The non-display area 120 of display panel 100 is provided with multiple
Demultplexer circuit 20 and a plurality of clock control signal line 60.Each demultplexer circuit 20 includes multiple transistors；
The input electrode of each transistor in same demultplexer circuit 20 is electrically connected with a data signal lead 211；Together
The coordination electrode of each transistor in one demultplexer circuit 20 is electrically connected from different clock control signal lines 60 respectively；Together
The output electrode of each transistor in one demultplexer circuit 20 is electrically connected from different data signal lines 51 respectively.
In addition, the viewing area 110 of display panel 100 can also include that a plurality of Y in a second direction is arranged and along first direction
The scan signal line 52 (or grid line) of extension, which intersects with data signal line limits a sub-pixel.Its
In, the sub-pixel of three different luminescent colors can constitute a pixel unit, the sub-pixel example of this three different luminescent colors
It such as can be red sub-pixel, blue subpixels and green sub-pixels, and each sub-pixel and number of three different luminescent colors
It corresponds and is electrically connected according to signal wire.It is understood that only being shone with a pixel unit including three differences in the present invention
It is illustrated for the sub-pixel (red sub-pixel, blue subpixels and green sub-pixels) of color, in actual design, one
The quantity of the sub-pixel for the different luminescent colors that pixel unit includes, the present invention are not construed as limiting.Correspondingly, display panel 100
It can also include scan drive circuit 30 (or gate driving circuit) that the scan drive circuit 30 is used in non-display area 120
Scanning signal is provided to the scan signal line 52 of viewing area 110.
It further include driving chip setting area in the non-display area 120 of display panel 100, driving chip setting area can be set
Driving chip 40 is set, which has multiple data signal pin Vn.Each crystal in same demultplexer circuit 20
The input electrode of pipe is electrically connected by a data signal lead 211 with a data pin Vn of driving chip 40, so as to drive
The data-signal exported in the data signal pin Vn of dynamic chip can be transmitted to the input electrode of each transistor.Meanwhile it is same
The coordination electrode of each transistor of demultplexer 20 is electrically connected from different clock control signal lines 60 respectively, clock when this is each
Signal wire processed is electrically connected with the different clocks of driving chip 40 control signal pins CKH respectively, with can be by driving chip 40
The clock control signal of clock control signal pin output is transmitted to the coordination electrode of transistor.
Wherein, the working principle of demultplexer circuit 20 is the clock control signal pin CKH difference of driving chip 40
Different clock control signals is inputted to the different crystal pipe of same demultplexer circuit 20 by clock control signal line 60,
So that the input electrode of the different crystal pipe of same demultplexer 20 is different from the time that output electrode is connected；At this point, driving
The data-signal of the data signal pin Vn output of chip 40 is transmitted to by the transistor that input electrode is connected with output electrode
The data signal line 51 being electrically connected with the transistor so that the corresponding pixel of data signal line 51 can show it is luminous.Driving
The data-signal that the data signal pin Vn of chip 40 can be exported by serial manner to different data signal lines 51.
It should be noted that Fig. 2 is only the illustrative attached drawing of the embodiment of the present invention, in Fig. 2, demultplexer circuit 20,
Scan drive circuit 30 and clock control signal line 60 are separately connected the unlike signal pin of same driving chip 40；In addition,
Demultplexer circuit 20, scan drive circuit 30 and clock control signal line 60 can be separately connected respectively from different drivings
Chip connection, the present invention is not especially limit this.For ease of description, following implement the present invention by taking Fig. 1 as an example
The technical solution of example is illustratively illustrated.
It include at least one first crystal in multiple transistors in any demultplexer circuit 20 with continued reference to Fig. 2
Pipe, the coordination electrode of the first transistor include the first coordination electrode and the second coordination electrode, which further includes the
One connecting line.First coordination electrode of the first transistor is connect with the second coordination electrode by the first connecting line, and the first control
Electrode is electrically connected by the second connecting line with a clock control signal line；And first connecting line be located at the first coordination electrode and
For two coordination electrodes close to the side of viewing area 110, clock control signal line 60 is located at one of the first transistor far from viewing area 110
Side.
Illustratively, Fig. 3 is a kind of structural schematic diagram of demultplexer circuit provided in an embodiment of the present invention.In conjunction with figure
2 and Fig. 3 can wrap in demultplexer circuit 20 when a pixel unit includes the sub-pixel of three different luminescent colors
3 transistors are included, the output electrode of 3 transistors of each demultplexer circuit 20, which corresponds, is electrically connected same pixel list
The data signal line of three sub-pixels of member.Correspondingly, including 3 the first transistor T1 in a demultplexer 20, each
The first transistor T1 may each comprise two coordination electrodes, i.e. the first coordination electrode g11 and the second coordination electrode g12；Meanwhile each
The first transistor T1 can also include two input electrodes, i.e. the first input electrode s11 and the second input electrode s12.It is same
The the first coordination electrode g11 and the second coordination electrode g12 of the first transistor T1 is connected by first connecting line 201, and the
One coordination electrode g11 is electrically connected by second connecting line 202 with a clock control signal line 60；And three first crystals
The first coordination electrode g11 of pipe T1 passes through the second different connecting lines 202 and different 61,62 and 63 electricity of clock control signal line
Connection controls signal CKH1, CKH2 and CKH3 to receive the different clocks of the transmission of different clocks control signal wire 61,62 and 63；
The the first input electrode s11 and the second input electrode s12 of three the first transistor T1 is electric with same data signal leads 211
Connection, to receive the data-signal Vn of the data signal lead 211 transmission；The output electrode d1 of three the first transistor T1 points
It is not electrically connected with different data signal wire 51R, 51G and 51B, three datas signal wire 51R, 51G and the 51B and viewing area 110
Different subpixel electrical connection, such as three data signal wire 51R, 51G and 51B respectively with a pixel list in viewing area 110
The sub-pixel electrical connection of the different luminescent colors of member, i.e. data signal line 51R corresponding with red sub-pixel can be electrically connected, data
Signal wire 51G can electrical connection corresponding with green sub-pixels and data signal line 51B can with blue subpixels are corresponding is electrically connected
It connects.
Fig. 4 is a kind of equivalent circuit diagram of demultplexer circuit corresponding with Fig. 3, and Fig. 5 is that one kind corresponding with Fig. 3 is more
The driver' s timing figure of distributor circuit.In conjunction with Fig. 3, Fig. 4 and Fig. 5, in t1~t2 period, clock control signal CKH1 passes through
Clock control signal line 61 is transmitted to the coordination electrode of the first transistor T101, the input electrode and output of the first transistor T101
Electrode conduction, the output electrode and output that data-signal Vn passes through data signal leads 211 and the first transistor T101 of conducting
Electrode is transmitted to data signal line 51B, so that corresponding sub-pixel shows and shines；In t2~t3 period, the first transistor
The input electrode and output electrode of T101 disconnects, while clock control CKH2 is transmitted to the first crystalline substance by clock control signal line 62
The coordination electrode of body pipe T102, the input electrode of the first transistor T102 are connected with output electrode, and data-signal Vn passes through data
The output electrode and output electrode of signal lead 211 and the first transistor T102 of conducting are transmitted to data signal line 51G, so that
Corresponding sub-pixel, which is shown, to shine；In t3~t4 period, the input electrode and output electrode of the first transistor T102 is disconnected, together
When clock control CKH3 the coordination electrode of the first transistor T103, the first transistor be transmitted to by clock control signal line 63
The input electrode of T103 is connected with output electrode, the first transistor that data-signal Vn passes through data signal leads 211 and conducting
The output electrode and output electrode of T103 is transmitted to data signal line 51R, so that corresponding sub-pixel shows and shines.Multichannel distribution
Device circuit controls the input electrode of different the first transistors and leading for output electrode by above-mentioned different clock control signal
It is logical, to realize that timesharing drives.
The first transistor T1 includes two coordination electrodes in demultplexer circuit, i.e. the first coordination electrode g11 and
Second coordination electrode g12, two coordination electrodes are connected by the first connecting line 201, so as to believe a clock control
Clock control signal CKH1 (CKH2 or CKH2) is transmitted to two coordination electrodes of the first transistor T1 by number line 61 (62 or 63).
In this way, compared to the prior art, by the coordination electrode of the transistor in demultplexer circuit along in the form of straight line
Two direction Y are extended, and two coordination electrodes of the first transistor T1 arrange in X direction respectively in the embodiment of the present invention, and lead to
The connection of the first connecting line is crossed, it can be while passing through two coordination electrode of the clock control signal to the first transistor T1
Under the premise of control, reduce demultplexer circuit in width W1 of the first transistor T1 on second direction Y, so as to
In Y-direction, reduce the size of demultplexer circuit, is conducive to the area for reducing non-display area in display panel, realizes display
The narrow frame of panel.
Optionally, with continued reference to Fig. 3, the input electrode of the first transistor T1 includes the first input electrode s11 and second defeated
Enter electrode s12；First coordination electrode g11 is between the first input electrode s11 and the output electrode d1 of the first transistor T1；The
Two coordination electrode g12 are between the second input electrode s12 and the output electrode of the first transistor T1；And first input electrode
S11 is connect with the second input electrode s12 by third connecting line 203；And second first input electrode of input electrode s11 or described
S11 is electrically connected with data signal leads.
It include at least one the first transistor T1 in demultplexer circuit, the first transistor T1 includes two control electricity
Pole g11 and g12, while also set up in the first transistor T1 there are two input electrode, i.e. the first input electrode s11 and second is defeated
Enter electrode s12, and the first coordination electrode g11 is between the first input electrode s11 and the output electrode d1 of the first transistor T1,
Second coordination electrode g12 is between the second input electrode s12 and the output electrode of the first transistor T1, so that the first control electricity
Pole g11 can make full use of the gap between the first input electrode s11 and output electrode d1, and the second coordination electrode g12 can fill
Divide using the gap between the second input electrode s12 and output electrode d1, so as in the X direction, minimize the first crystalline substance
The length of body pipe T1 avoids the size of demultplexer circuit in the X direction from increasing, further decreases the non-display of display panel
The area occupied in area is conducive to the narrow frame of display panel.
In addition, the first input electrode s11 is connect with the second input electrode s12 by third connecting line 203, the second input electricity
Pole s12 (or first input electrode s11) is electrically connected with data signal leads 211, so as to not increase data signal leads
Under the premise of 211 quantity, the data-signal for enabling data signal line 211 to transmit passes through the first input electrode s11, the respectively
Two input electrode s12 are transmitted to output electrode d1, achieve the effect that simplified demultplexer circuit structure.Wherein, when multichannel point
Orchestration circuit includes multiple the first transistor T1, and when multiple the first transistor T1 is arranged successively along first direction X, any phase
Two adjacent the first transistor T1 can share a first input electrode s11 or (the second input electrode s12), so as in X
The size that demultplexer circuit is further decreased on direction further decreases the frame of display panel.
Optionally, the first transistor of demultplexer circuit further includes the 4th connecting line, and the 4th connecting line is located at the
One coordination electrode and side of second coordination electrode far from viewing area, the first coordination electrode and the second coordination electrode also pass through the 4th
Connecting line connection；Wherein, the first coordination electrode, the second coordination electrode, the first connecting line and the 4th connecting line constitute ring junction
Structure.
Illustratively, Fig. 6 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.In conjunction with
The the first coordination electrode g11 and the second coordination electrode g12 of Fig. 2 and Fig. 6, the first transistor T1 of demultplexer circuit are by leaning on
The first connecting line 201 connection of nearly 110 side of viewing area, and connected by the 4th connecting line 204 far from 110 side of viewing area
It connects, so that the first coordination electrode g11, the second coordination electrode g12, the first connecting line 201 and the 4th connecting line 204 form cyclic annular knot
Structure.The first coordination electrode g11, the second coordination electrode g12, the first connecting line 201 and the 4th connecting line 204 of the cyclic structure can
It is arranged with same layer, so that the first coordination electrode g11, the second coordination electrode g12, the first connecting line 201 and the 4th connecting line 204 are adopted
It is formed under same technique with same material, simplifies the preparation step of display panel, improved production efficiency, reduce cost.
The ring that first coordination electrode g11, the second coordination electrode g12, the first connecting line 201 and the 4th connecting line 204 form
Shape structure can be used as an electrostatic shielding body, which can be such that electrostatic is formed into a loop in the cyclic structure, with
Electrostatic is reduced to where except the first coordination electrode g11, the second coordination electrode g12, the first connecting line 201 and the 4th connecting line 204
Other film layers or other positions transmission outside film layer, avoid electrostatic from impacting signal transmission, so as to improve display effect
Fruit.
Optionally, Fig. 7 is a kind of part film schematic diagram of a layer structure of display panel provided in an embodiment of the present invention.In conjunction with figure
6 and Fig. 7, display panel further include underlay substrate 10；The first transistor T1 further includes having positioned at the first of 10 side of underlay substrate
Active layer m1；The the first coordination electrode g11 and the second coordination electrode g12 of the first transistor T1 is located at the first active layer m away from substrate
The side of substrate 10；Wherein, the length of Y, the first coordination electrode g11 and the second coordination electrode g12 are all larger than in a second direction
Equal to the length of the first active layer m1.
The the first coordination electrode g11 and the second coordination electrode g12 of the first transistor T1 of demultplexer circuit is located at the
One active layer m1 deviates from the side of underlay substrate 10, i.e. the first transistor T1 is top-gated transistor.In demultplexer circuit
The preparation sequence of each film layer of the first transistor can be to form semiconductor layer in the side of underlay substrate 10 and to the semiconductor layer
It is patterned；Gate insulating layer 1011 is formed away from the side of underlay substrate 10 in semiconductor layer；In gate insulating layer 1011
Gate metal layer is formed away from the side of underlay substrate 10, and patterning is carried out to the gate metal layer and forms the first coordination electrode
G11, the second coordination electrode g12, the first connecting line 201 and the 4th connecting line 204；To the first transistor T1 in semiconductor pattern
It is doped at the position of source electrode and drain electrode, forms the first active layer m1；Deviate from the side of underlay substrate 10 in gate metal layer
Form interlayer insulating film 1012；At the source electrode and drain electrode face position of the first transistor T1, is formed and run through interlayer insulating film
1012 and gate insulating layer 1011 via hole；Form Source and drain metal level on interlayer insulating film 1012, and to Source and drain metal level into
Row patterning, to form the first input electrode s11, the second input electrode s12 and output electrode d1 of the first transistor, first
Input electrode s11 and the second input electrode s12 passes through respectively to be electrically connected at via hole and the source electrode position of the first active layer m1, output
Electrode d1 at via hole and the drain locations of the first active layer m1 by being electrically connected.Wherein, the first input electrode s11, the second input
Electrode s12 and output electrode d1 passes through via hole respectively and contacts with the first active layer m1, which is the first input electrode
Contact 21a, 21b and 21c of s11, the second input electrode s12 and output electrode d1 and the first active layer m1, pass through setting
Multiple contact 21a, multiple contact 21b and multiple contact 21c, can reduce the first input electrode s11, the second input electrode
Contact resistance between s12 and output electrode d1 and the first active layer m1, to guarantee the accuracy of signal transmission.Accordingly
, multiple contacts correspond to multiple via holes.The embodiment of the present invention is not specifically limited the setting number of each contact, i.e., to setting
The quantity for setting via hole is not specifically limited.
The first coordination electrode g11 and the second coordination electrode g12 are covered in the orthographic projection of semiconductor layer in the first transistor T1
The semiconductor pattern part of lid be the first active layer m1 channel region, usual active layer channel region be low concentration doping and source electrode
With the doping at drain locations being high concentration；Due in the Y direction, the length of the first coordination electrode g11 and the second coordination electrode g12
The length Wm1 that Wg1 is more than or equal to the first active layer m1 is spent, therefore the first coordination electrode g11 and the second coordination electrode can formed
After g12, then by the mode of ion implanting semiconductor pattern is doped；At this point, the first coordination electrode g11 and second can be controlled
Mask plate of the electrode g12 processed as doping, prevents the impurity of high concentration from entering the channel region of active layer m1.Simultaneously as
Electrostatic is needed to bombard during doping, so that corresponding position of the ion implanting to semiconductor pattern, by the first coordination electrode
G11, the second coordination electrode g12, the first connecting line 201 and the 4th connecting line 204 form cyclic structure, quiet when can make to adulterate
Electricity is in the first coordination electrode g11 of ring structure, the second coordination electrode g12, the first connecting line 201 and the 4th connecting line 204
Forming circuit avoids spreading because of electrostatic to the channel region of active layer m1, and influences the on state characteristic of the first transistor T1.Wherein,
It is quiet in first coordination electrode g11 of ring structure, the second coordination electrode g12, the first connecting line 201 and the 4th connecting line 204
Electricity can be exported by other static guiding outbound paths, and the embodiment of the present invention is not specifically limited in this embodiment.
In addition, clock control signal line 61,62 and 63 can be electric with the input electrode s11 and s12 of the first transistor T1, output
Data signal line 51R, 51G and 51B same layer of pole d1, third connecting line 203 and viewing area are arranged；And the first connecting line 201,
Second connecting line 202, the 4th connecting line 204 and data signal leads 211 can be with the control electricity of the first coordination electrode g11 and second
Pole g12 is formed under same technique using same material, therefore the second connecting line 202 is needed through contact 202a and clock control
Signal wire 61 (62 or 63) electrical connection, data signal leads 211 are needed through contact 211a and the second input electrode s12 (or the
One input electrode s1) electrical connection.
It should be noted that in the embodiment of the present invention in demultplexer circuit transistor number be it is multiple, i.e., this is more
The number for the transistor being arranged in distributor circuit can be 3 and 3 or more；Meanwhile in a demultplexer circuit
Including at least one the first transistor, is i.e. it may include a first transistor in a demultplexer circuit, may also comprise 2
A or 2 or more the first transistors, and, it is understood that in demultplexer circuit provided in an embodiment of the present invention
Other second transistors different from the first transistor can also be set.Below in conjunction with attached drawing, to being wrapped in demultplexer circuit
Different transistors is included illustratively to be illustrated.
Optionally, Fig. 8 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.In conjunction with figure
2 and Fig. 8, include in multiple transistors in demultplexer circuit 20 at least one the first transistor T1 and at least one second
Transistor T21 and T22；The the first coordination electrode g11 and the second coordination electrode g12 of each the first transistor T1 passes through the first connection
Line 201 connects, and the first coordination electrode g11 of each the first transistor T1 passes through the second connecting line 202 and a clock control
Signal wire 61 is electrically connected；The coordination electrode g21 (g22) of each second transistor T21 (T22) passes through the 5th connecting line 205 (206)
It is electrically connected with a clock control signal line 62 (63).
Illustratively, more when a pixel unit includes the sub-pixel of three different luminescent colors in conjunction with Fig. 2 and Fig. 8
It may include 3 transistors, the output electrode one of 3 transistors of each demultplexer circuit 20 in distributor circuit 20
The data signal line of one corresponding three sub-pixels for being electrically connected same pixel unit.Correspondingly, can in demultplexer circuit 20
To include a first transistor T1 and two second transistors T21 and T22.Wherein, the first transistor T1 includes passing through first
The the first coordination electrode g11 and the second coordination electrode g12 that connecting line 201 connects, and the first coordination electrode g11 passes through the second connection
Line 202 is electrically connected with clock control signal line 61；Second transistor T21 (T22) includes coordination electrode g21 (g22), control electricity
Pole g21 (g22) is connect by the 5th connecting line 205 (206) and clock control signal line 62 (63) electricity.
In this way, the first transistor T01 is identical as second transistor T02 and T03 structure compared to the prior art in Fig. 9
The case where, the embodiment of the present invention is by the way that the first transistor T1 to be set as including two coordination electrodes, i.e. the first coordination electrode g11
With the second coordination electrode g12, and two coordination electrodes are connected by the first connecting line 201, and by the second connecting line 202 with
Clock control signal line 61 is electrically connected, and can reduce the length of the first transistor T1 and second transistor T21 (T22) in the Y direction
The sum of, so as to reduce the size of demultplexer circuit 20 in the Y direction, advantageously reduce the frame of display panel.
Optionally, continuing with reference Fig. 2 and Fig. 8, each the first transistor T1 and each second transistor T21 (T22),
Y is arranged in a second direction；And the first transistor T1 and second transistor T21 (T22) be located at do not go together；Wherein, first direction X is
Line direction；Y in a second direction, adjacent the first transistor T1 and second transistor T21 (T22) partly overlap.
The coordination electrode g21 of a second transistor T21 in two second transistors of demultplexer circuit 20 is logical
It crosses one article of the 5th connecting line 205 to be electrically connected with one bar of clock control signal line 62, the output electrode and number of second transistor pipe T21
It is electrically connected according to signal wire 51G；The coordination electrode g22 of another second transistor T22 is by another article of the 5th connecting line 206 and separately
One clock control signal line 63 is electrically connected；So that in the Y direction, the output electrode d21 of second transistor T21 can be with the first crystalline substance
The first input electrode s11 of body pipe T1 is overlapped.Wherein, in the X direction, second transistor T21 and the first transistor T1 is overlapping
Width can be L'.Meanwhile second transistor T21 and second transistor T22 can share input electrode s2, and second transistor
The input electrode s2 of T21 and second transistor T22 can pass through 211 electricity of extended line and data signal leads of third connecting line 203
Connection, the data-signal of the transmission of data signal leads 211 can be received.
By the way that the first transistor T1 second transistor T21 (T22) adjacent thereto is set to different rows, i.e., first is brilliant
Body pipe T1 in X direction on the side of viewing area 110 can be deviated from second transistor T21 (T22), and Y in a second direction is adjacent
The first transistor T1 and second transistor T21 (T22) partly overlap, i.e., at least one in a second direction Y extend straight line, energy
Enough while passing through the first transistor T1 and second transistor T21 (T22).It so, it is possible in the X direction, to reduce the first transistor
The sum of the size of T1 and second transistor T21 and T22 are conducive to narrow frame to reduce the size of demultplexer circuit 20
Realization.
Wherein, the same meaning can be expressed in Fig. 8 with appended drawing reference identical in Fig. 3, the part of not detailed description can in Fig. 8
Referring to the description to Fig. 3, this is no longer going to repeat them.Meanwhile Figure 10 correspond to a kind of demultplexer circuit of Fig. 8 etc.
Imitate circuit diagram.Its driving method can be similar with technical solution described in Fig. 3 and Fig. 4 of the embodiment of the present invention with driver' s timing, herein
No longer specifically repeat.
Correspondingly, Figure 11 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.Such as figure
11, the first coordination electrode g11 and g12 of the first transistor T1 can also be connected by the 4th connecting line 204 in demultplexer circuit
It connects.First coordination electrode g11, the second coordination electrode g12, the first connecting line 201 and the cyclic annular of the 4th connecting line 204 composition are tied
Structure can be used as an electrostatic shielding body, which can be such that electrostatic is formed into a loop in the cyclic structure, to reduce
Electrostatic is to except the first coordination electrode g11,204 place film layer of the second coordination electrode g12, the first connecting line 201 and the 4th connecting line
Outer other film layers or other positions transmission, avoid electrostatic from impacting signal transmission, so as to improve display effect.
In addition, the first coordination electrode g11 of the cyclic structure, the second coordination electrode g12, the first connecting line 201 and the 4th
Connecting line 204 can be arranged with same layer, so that the first coordination electrode g11, the second coordination electrode g12, the first connecting line 201 and the 4th
Connecting line 204 is formed under same technique using same material, simplifies the preparation step of display panel, improves production efficiency, drop
Low cost.
Wherein, it can refer to the description to Fig. 8 with something in common in Fig. 8 in Figure 11, and identical with Fig. 8 to Figure 11 below
Place, and the part being not described in detail in fig. 8, can refer to the description to Figure 11.
Optionally, Figure 12 is a kind of the schematic diagram of the section structure in Figure 11 along the section A-A'.In conjunction with reference Figure 11 and Figure 12,
Display panel further includes underlay substrate 10, and the first transistor T1 further includes the first active layer positioned at 10 side of underlay substrate
M1, second transistor T21 and T22 include the second active layer m2 positioned at 10 side of underlay substrate, and along first direction X, and first
The width L1 of active layer m1 is greater than the width L2 (L3) of the second active layer m2；Y in a second direction, the length of the second active layer m2
Wm2 is greater than the length Wm1 of the first active layer.
Illustratively, two second transistors T21 and T22 share an input electrode s2 in demultplexer circuit, i.e.,
In a first direction on X, the second active layer m2's and another second transistor T21 of a second transistor T21 (T22) is active
It can be L that layer, which has overlapping, overlapping width, at this time the width L2 of the second active layer m2 of a second transistor T21 (T22)
(L3) by the second part active layer m2 covered input electrode s2 and output electrode d21 (d22) and input electrode s2 with it is defeated
Part between second part active layer m2 of electrode d21 (d22) covering out.Therefore, in a first direction on X, one second brilliant
Width L1 of the width L2 (L3) of the second active layer m2 of body pipe T21 (T22) less than the first active layer m1, meanwhile, one second
The length Wm2 of the second active layer m2 of transistor T21 (T22) is greater than the length Wm1 of the first active layer.It so, it is possible to make first
The active layer size of transistor T1 can be suitable with the size of active layer of second transistor T21 (T22), to make first crystal
Pipe T1 and second transistor T21 (T22) have consistent on state characteristic, guarantee the display homogeneity of display panel.
Wherein, the 5th connecting line 205 and 206 can pass through contact 205a and 206a and clock control signal line 61 and 62 respectively
Electrical connection；The input electrode s2 of second transistor T21 and T22 can be electrically connected by contact 22a with the second active layer m2；Second is brilliant
The output electrode d21 and d22 of body pipe T21 and T22 can be electrically connected by contact 22b and 22c with the second active layer m2 respectively.Together
When, the input electrode s2 of second transistor T21 and T22 and the second active layer m2 contact 22a being electrically connected and second transistor
The contact 22b and 22c that the output electrode d21 and d22 of T21 and T22 is electrically connected with the second active layer m2 are settable multiple, with drop
Low contact resistance.
In addition, in addition to the first transistor T1 is located at second transistor T21 (T22) away from viewing area side in Fig. 8 and Fig. 9,
The first transistor T1 may be additionally located at the side of second transistor T21 (T22) close to viewing area.
Illustratively, Figure 13 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.Knot
Fig. 2 and Figure 13 is closed, a demultplexer circuit 20 includes 3 transistors, i.e., demultplexer circuit 20 includes one first
Transistor T3 and two second transistors T4 and T5.Wherein, the first transistor T3 includes the control of the first coordination electrode g31 and second
Electrode g32, the first coordination electrode g31 and the second coordination electrode g32 are electrically connected by the first connecting line 301, and the first control
Electrode g31 is electrically connected by the second connecting line 302 with a clock control signal line 73, and the first transistor T1 further includes first defeated
Electrode d31 and the second output electrode d32 out, the first output electrode d31 and the second output electrode d32 pass through the 6th connecting line
303 connections, and be electrically connected with a data signal wire 51G；The control of a second transistor T4 in two second transistors
Electrode g4 is electrically connected by one article of the 5th connecting line 305 with one bar of clock control signal line 71, the output electricity of second transistor T4
Pole d4 is electrically connected with a data signal wire 51R；The coordination electrode g5 of another second transistor T5 passes through one article of the 5th connection
Line 306 is electrically connected with a clock control signal line 73, the output electrode d5 of second transistor T5 and a data signal wire 51B
Electrical connection；And the input electrode s4 and s5 and number of the input electrode s3 of the first transistor T3 and two second transistors T4 and T5
According to signal lead 311, the data-signal of the data signal leads 311 transmission can be received.
Compared to the prior art in Fig. 9, the first transistor T01 feelings identical with second transistor T02 and T03 structure
Condition, the embodiment of the present invention can equally reduce the sum of the length of the first transistor T3 and second transistor T4 (T5) in the Y direction, from
And the size of demultplexer circuit 20 can be reduced in the Y direction, advantageously reduce the frame of display panel.
Correspondingly, Figure 14 is the structural schematic diagram of another demultplexer circuit provided in an embodiment of the present invention.Figure 14
In repeated no more with something in common in Figure 13, only difference in Figure 14 is illustrated.Such as Figure 14, the of the first transistor T3
One coordination electrode g31 and the second coordination electrode g32 can also be connected by the 4th connecting line 304, so that the first coordination electrode
G31, the second coordination electrode g32, the first connecting line 301 and the 4th connecting line 304 connect and compose ring structure, to form electrostatic
Shield, the electrostatic shielding body can be such that electrostatic is formed into a loop in the cyclic structure, to reduce electrostatic to except the first control electricity
Other film layers or other outside pole g31,304 place film layer of the second coordination electrode g32, the first connecting line 301 and the 4th connecting line
Location transmission avoids electrostatic from impacting signal transmission, so as to improve display effect.
The embodiment of the invention also provides a kind of display device, which includes display provided in an embodiment of the present invention
Panel.Therefore the display device also has beneficial effect possessed by organic light emitting display panel provided in an embodiment of the present invention,
Something in common can refer to understanding above, hereinafter repeat no more.
Illustratively, Figure 15 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.Such as Figure 15, display
Device 200 can be mobile phone, tablet computer, vehicle-mounted product, intelligent wearable device (for example, smartwatch) and art technology
Other kinds of display device, the embodiment of the present invention known to personnel are not construed as limiting this.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of display panel characterized by comprising viewing area and the non-display area around the viewing area；The display
Area is provided with a plurality of data signal line arranged along first direction and extend in a second direction, wherein the first direction and institute
State second direction intersection；The non-display area is provided with multiple demultplexer circuits and a plurality of clock control signal line；
Each demultplexer circuit includes multiple transistors；It is each described in the same demultplexer circuit
The input electrode of transistor is electrically connected with a data signal lead；Each crystalline substance in the same demultplexer circuit
The coordination electrode of body pipe is electrically connected from the different clock control signal lines respectively；In the same demultplexer circuit
The output electrode of each transistor is electrically connected from the different data signal lines respectively；
It wherein, include at least one the first transistor in multiple transistors in any demultplexer circuit；Described
The coordination electrode of one transistor includes the first coordination electrode and the second coordination electrode, and the first transistor includes the first connection
Line；First coordination electrode is connect with second coordination electrode by first connecting line, and the first control electricity
Pole is electrically connected by the second connecting line with a clock control signal line；
First connecting line is located at first coordination electrode and second coordination electrode close to the side of the viewing area,
The clock control signal line is located at side of the first transistor far from the viewing area.
2. display panel according to claim 1, which is characterized in that the input electrode of the first transistor includes first
Input electrode and the second input electrode；
First coordination electrode is between first input electrode and the output electrode of the first transistor；Described
Two coordination electrodes are between second input electrode and the output electrode of the first transistor；
First input electrode is connect with second input electrode by third connecting line；And second input electrode or
First input electrode is electrically connected with the data signal leads.
3. display panel according to claim 2, which is characterized in that the first transistor includes the 4th connecting line, institute
It states the 4th connecting line and is located at first coordination electrode and the side of second coordination electrode far from the viewing area, described
One coordination electrode also passes through the 4th connecting line with second coordination electrode and connect；
Wherein, first coordination electrode, second coordination electrode, first connecting line and the 4th connecting line structure
Circularize structure.
4. display panel according to claim 3, which is characterized in that first coordination electrode, the second coordination electrode, institute
State the first connecting line, second connecting line and the 4th connecting line same layer setting.
5. display panel according to claim 3, which is characterized in that the display panel further includes underlay substrate；
The first transistor further includes the first active layer positioned at the underlay substrate side；
First coordination electrode and second coordination electrode are located at one that first active layer deviates from the underlay substrate
Side；
Wherein, in this second direction, the length of first coordination electrode and second coordination electrode, which is all larger than, is equal to
The length of first active layer.
6. display panel according to claim 1, which is characterized in that multiple transistors in the demultplexer circuit
In further include at least one second transistor；The coordination electrode of each second transistor passes through the 5th connecting line and one article of institute
State the electrical connection of clock control signal line.
7. display panel according to claim 6, which is characterized in that each the first transistor and each second crystalline substance
Body Guan Jun is arranged along the second direction；And the first transistor and the second transistor are located at and do not go together；Wherein, described
First direction is line direction；
Along the second direction, the adjacent the first transistor and the second transistor partly overlap.
8. display panel according to claim 7, which is characterized in that the display panel further includes underlay substrate；It is described
The first transistor further includes the first active layer positioned at the underlay substrate side, and the second transistor includes being located at the lining
Second active layer of substrate side；
Along the first direction, the width of first active layer is greater than the width of second active layer；Along the second party
To the length of second active layer is greater than the length of first active layer.
9. display panel according to claim 1, which is characterized in that the demultplexer circuit includes 3 transistors；
The viewing area is additionally provided with a plurality of scan signal line for arranging and extending in a first direction in a second direction；It is a plurality of described
Scan signal line intersects with a plurality of data signal line limits multiple sub-pixels；The sub-pixel group of three different luminescent colors at
One pixel unit；Each sub-pixel, which corresponds, is electrically connected the data signal line；
The output electrode of 3 transistors of each demultplexer circuit, which corresponds, is electrically connected the same pixel unit
Three sub-pixels data signal line.
10. a kind of display device characterized by comprising display panel according to any one of claims 1 to 9.
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Application publication date: 20190903 |