CN106932990B - Display panel, display device and manufacturing method of display panel - Google Patents

Display panel, display device and manufacturing method of display panel Download PDF

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Publication number
CN106932990B
CN106932990B CN201710342031.9A CN201710342031A CN106932990B CN 106932990 B CN106932990 B CN 106932990B CN 201710342031 A CN201710342031 A CN 201710342031A CN 106932990 B CN106932990 B CN 106932990B
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layer
electrode
sub
line
connecting line
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CN106932990A (en
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金慧俊
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Shanghai AVIC Optoelectronics Co Ltd
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Shanghai AVIC Optoelectronics Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application discloses a display panel, a display device and a manufacturing method of the display panel. One embodiment of the display panel includes: a display area and a non-display area; the display area comprises a common electrode, a plurality of data lines extending along a first direction and a plurality of scanning lines extending along a second direction; the non-display area comprises an electrostatic discharge unit, a shift register and a frame sealing glue area surrounding the display area; the electrostatic discharge unit is electrically connected with the common electrode and the shift register, and the shift register is electrically connected with the plurality of scanning lines; the central line of the frame sealing glue area comprises a plurality of line segments communicated by a plurality of arc lines; a part of a connecting line of the electrostatic discharge unit and the shift register is positioned in the frame sealing glue area corresponding to the arc line; the connecting line comprises a first sub-connecting line in a region corresponding to the arc line, and the first sub-connecting line is formed on the first transparent electrode layer. The embodiment improves the transmittance of the frame sealing glue in the corresponding area of the arc line, thereby improving the ultraviolet curing efficiency of the frame sealing glue.

Description

Display panel, display device and manufacturing method of display panel
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel, a display device, and a method for manufacturing the display panel.
Background
With the rapid progress of display technology, liquid crystal display panels have been widely spread. The liquid crystal display panel mainly comprises a color film substrate, an array substrate and a liquid crystal layer, wherein the color film substrate and the array substrate are oppositely arranged, and the liquid crystal layer is positioned between the two substrates.
The array substrate generally includes a display area and a non-display area, the display area includes pixel electrodes, and each pixel electrode is provided with a thin film transistor. The drain electrode of the thin film transistor is electrically connected with the data line, and the grid electrode of the thin film transistor is electrically connected with the scanning line. The non-display area generally comprises a shift register and an electrostatic discharge unit, wherein the shift register is electrically connected with a plurality of scanning lines and the electrostatic discharge unit so as to provide a shift signal for the scanning lines; the static electricity discharge unit discharges static electricity generated in the display panel.
When the color film substrate and the array substrate are subjected to a box aligning process, the color film substrate and the array substrate are generally packaged by using frame sealing glue and are subjected to ultraviolet curing through ultraviolet rays. However, the metal connecting lines of the shift register and the electrostatic discharge unit are generally overlapped with the sealant region. Especially for rectangular display panels, the amount of frame sealing adhesive in the corner area is often large. At this time, the metal connecting wires may affect the transmittance of the frame sealing adhesive region, and reduce the efficiency of performing ultraviolet curing on the frame sealing adhesive.
Disclosure of Invention
The present application is directed to a display panel, a display device and a method for manufacturing the display panel, so as to solve the technical problems mentioned in the background section above.
In a first aspect, the present application provides a display panel, the display panel including a display area and a non-display area, the non-display area surrounding the display area; the display area comprises a common electrode, a plurality of data lines extending along a first direction and a plurality of scanning lines extending along a second direction; the common electrode is formed on the first transparent electrode layer and the first metal layer; a plurality of pixel regions are defined by the intersection of the data lines and the scanning lines, and each pixel region comprises a pixel electrode and a thin film transistor electrically connected with the pixel electrode; the thin film transistor includes a gate electrode, a source electrode, a drain electrode, and an active layer forming a conductive channel between the source electrode and the drain electrode; the gate electrode is formed on the first metal layer, the source electrode and the drain electrode are formed on the second metal layer, the active layer is formed between the first metal layer and the second metal layer, and the pixel electrode is formed on the second transparent electrode layer; the drain electrode is electrically connected with the pixel electrode through a via hole; a first insulating layer is formed between the first metal layer and the active layer, and a second insulating layer is formed between the second metal layer and the second transparent electrode layer; the non-display area comprises an electrostatic discharge unit, a shift register and a frame sealing glue area surrounding the display area; the electrostatic discharge unit is electrically connected with the common electrode and the shift register, and the shift register is electrically connected with the plurality of scanning lines; the central line of the frame sealing glue area comprises a plurality of line segments communicated by a plurality of arc lines; the static electricity releasing unit and a part of the connecting line of the shift register are positioned in the frame sealing glue area corresponding to the arc line; the connecting wire comprises a first sub-connecting wire in the frame sealing glue area corresponding to the arc line, and the first sub-connecting wire is formed on the first transparent electrode layer.
In a second aspect, the present application provides a method for manufacturing a display panel, where the method includes: depositing a first transparent electrode layer, a first metal layer and a first photoresist layer on the substrate in sequence; forming a grid electrode, a common electrode and a connecting line in an arc line corresponding region in a frame sealing glue region by using a first mask through a photoetching process, wherein the central line of the frame sealing glue region comprises a plurality of line segments communicated by a plurality of arc lines, the connecting line is used for electrically connecting an electrostatic discharge unit and a shift register, the connecting line comprises a first sub-connecting line, and the first sub-connecting line is formed on the first transparent electrode layer; depositing a first insulating layer, a polysilicon layer, a second metal layer and a second photoresist layer on the gate and the common electrode in sequence; forming an active layer on the polycrystalline silicon layer by using a second mask through a photoetching process, and forming a source electrode and a drain electrode on the second metal layer; depositing a second insulating layer and a third photoresist layer on the source electrode, the drain electrode and the active layer in sequence; forming a via hole connected with the source electrode on the second insulating layer by using a third mask through a photoetching process; depositing a second transparent electrode layer and a fourth photoresist layer on the second insulating layer in sequence; and forming a pixel electrode on the second transparent electrode layer by using a fourth mask through a photoetching process.
In a third aspect, the present application provides a display device including the display panel of the above embodiment.
According to the display panel, the display device and the manufacturing method of the display panel, a part of the connecting line of the shift register and the electrostatic release unit is located in the frame sealing glue area, the central line of the frame sealing glue area comprises a plurality of line segments communicated with a plurality of arc lines, and the first sub-connecting line of the connecting line in the frame sealing glue area corresponding to the arc lines is provided with the transparent electrode layer, so that the transmittance of the frame sealing glue in the area corresponding to the arc lines is improved, and the ultraviolet curing efficiency of the frame sealing glue is improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1a is a top view of one embodiment of a display panel according to the present application;
FIG. 1b is a top view of a pixel area of the display panel shown in FIG. 1 a;
FIG. 1c is a schematic cross-sectional view of the pixel region of FIG. 1b along direction XX';
fig. 1d is a schematic structural diagram of the frame sealing adhesive region corresponding to the arc line of the display panel shown in fig. 1 a;
fig. 2a is a schematic structural diagram of a connection line between the electrostatic discharge unit and the shift register of the display panel 100 shown in fig. 1 a;
FIG. 2b is a schematic cross-sectional view of the structure shown in FIG. 2a along the direction YY';
fig. 3 is a schematic structural view of an electrostatic discharge unit of a display panel according to the present application;
FIG. 4 is a schematic flow chart diagram illustrating one embodiment of a method for fabricating a display panel according to the present application;
FIGS. 4a to 4i are schematic structural diagrams illustrating a specific forming step of the display panel of the method shown in FIG. 4;
fig. 5 is a schematic structural diagram of one embodiment of a display device according to the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
FIG. 1a shows a top view of one embodiment of a display panel according to the present application. The display panel of the present embodiment includes a display area AA and a non-display area DA other than the display area AA. The display area AA refers to an area for displaying an image, and includes a plurality of pixel electrodes 10b, a common electrode (not shown in fig. 1 a), a plurality of data lines 12 extending in a first direction D1, and a plurality of scan lines 11 extending in a second direction D2. The non-display area DA is an area where no image is displayed, and includes an electrostatic discharge unit, a shift register, and a frame sealing adhesive area 13 surrounding the display area AA. The plurality of scan lines 11 and the plurality of data lines 12 intersect to define a plurality of pixel regions 10, and each pixel region 10 includes a pixel electrode 10b and a thin film transistor 10a electrically connected to the pixel electrode 10 b.
Referring to fig. 1b, a schematic structural diagram of the pixel region 10 may be shown, as shown in fig. 1b, each pixel region 10 includes a common electrode 101, a gate electrode 102, an active layer 103, a source electrode 104, a drain electrode 105, and a pixel electrode 106. The gate electrode 102, the active layer 103, the drain electrode 104, and the source electrode 105 constitute a thin film transistor, and the active layer 103 forms a conductive channel between the drain electrode 104 and the source electrode 105. The drain electrode 104 may be electrically connected to the pixel electrode 106 through a via 107, and the source electrode 105 may be electrically connected to the data line 12.
The pixel electrode of the embodiment includes a plurality of slits, so that the horizontal electric field between the pixel electrode and the common electrode can be enhanced, which is beneficial to the rotation of the liquid crystal molecules in the display panel.
Further reference is made to fig. 1c, which shows a schematic cross-sectional view in the XX' direction of the pixel area shown in fig. 1 b. The common electrode 101 includes a first portion 1011 formed on the first transparent electrode layer and a second portion 1012 formed on the first metal layer; the gate 102 is formed on the first metal layer and the first transparent electrode layer; the drain electrode 104 and the source electrode 105 are formed on the second metal layer; the active layer 103 is formed between the first metal layer and the second metal layer; the pixel electrode 106 is formed on the second transparent electrode layer; the drain electrode 104 is electrically connected to the pixel electrode 106 through a via 107. A first insulating layer 108 is formed between the first metal layer and the active layer 103, and a second insulating layer 109 is formed between the second metal layer and the second transparent electrode layer, which are formed on a substrate 110.
In the conventional pixel electrode structure, the layers formed on the substrate are generally a first metal layer (for forming a gate electrode), a first insulating layer, an active layer, a second metal layer (for forming a source electrode and a drain electrode), a second insulating layer, a common electrode layer, and a pixel electrode layer in this order. In the manufacturing process of such a pixel electrode, five masks are usually required to manufacture the gate electrode, the active layer, the source electrode, the drain electrode, the common electrode and the pixel electrode.
Compared with the existing pixel electrode structure, the pixel electrode structure of the embodiment only needs four mask plates, and the four mask plates are respectively used for manufacturing the gate electrode, the common electrode, the active layer, the source electrode, the drain electrode and the pixel electrode. Therefore, the manufacturing process of the pixel electrode is effectively reduced, the mask used in the manufacturing process is saved, and the manufacturing cost is reduced.
In some optional implementations of the present embodiment, the common electrode 101 may only include the first portion 1011 formed on the first transparent electrode layer. Since the transparent electrode layer is generally made of ITO (Indium tin oxide), the resistance thereof is large. The resistance of the second portion 1012 formed in the first metal layer is much lower than the resistance of the first portion 1011 formed in the first transparent electrode layer. By connecting the second portion 1012 formed on the first metal layer in parallel with the first portion 1011 formed on the first transparent electrode layer, the overall resistance of the common electrode 101 can be effectively reduced, which is beneficial to the transmission of signals in the common electrode 101.
According to the pixel structure, the first connecting line can be integrated in the manufacturing process of the grid electrode and the common electrode, so that the transmittance of the frame sealing glue area corresponding to the arc line is improved on the premise of not increasing the process complexity; furthermore, the connecting line can be made of the same half-tone mask, so that the manufacturing cost is saved.
Further referring to fig. 1d, it shows a schematic structural diagram of the frame sealing adhesive region corresponding to the arc line of the display panel 100 shown in fig. 1 a. As shown in fig. 1d, the non-display area DA further includes an electrostatic discharge unit 14, a shift register 15, and a sealant region 13 surrounding the display area AA. The electrostatic discharge unit 14 is electrically connected to the common electrode 101 and the shift register 15, respectively, and the shift register 15 is electrically connected to the plurality of scanning lines 11. The frame sealing adhesive region 13 is a strip-shaped structure surrounding the display area AA, and the central line 131 includes a plurality of line segments connected by a plurality of arcs. It can be understood that the central line 131 in this embodiment is a characteristic line formed by sequentially connecting center points of the frame sealing adhesive region 13, and the center point is a center point between each two opposite sides of the frame sealing adhesive region 13.
A portion of the connection line between the electrostatic discharge unit 14 and the shift register 15 may be located in the frame sealing adhesive region corresponding to the arc line (e.g., the sector region in fig. 1 d), that is, the connection line may span the frame sealing adhesive region corresponding to the arc line, or may be covered by the frame sealing adhesive region corresponding to the arc line. In this embodiment, the first sub-connecting lines 161 of the connecting lines in the frame sealing adhesive region corresponding to the arc line are formed on the first transparent electrode layer, that is, the first sub-connecting lines 161 are formed by ITO only. It should be understood that, although the frame sealing adhesive region corresponding to the arc is defined in fig. 1d, this is only illustrative and does not constitute a limitation to the shape of the frame sealing adhesive region corresponding to the arc, and a person skilled in the art may set the shape of the frame sealing adhesive region corresponding to the arc according to an actual application scenario.
According to the display panel provided by the embodiment of the application, the shift register and a part of the connecting line of the electrostatic release unit are located in the frame sealing adhesive region corresponding to the arc line, the first sub-connecting line located in the frame sealing adhesive region corresponding to the arc line is set to be formed by only the first transparent electrode layer, the transmittance of the frame sealing adhesive region corresponding to the arc line is effectively increased, and the efficiency of ultraviolet curing of the frame sealing adhesive is improved.
In some optional implementation manners of this embodiment, the electrostatic discharge unit 14 may also be located between the frame sealing adhesive region 13 and the display area AA, so that the length of a connection line between the electrostatic discharge unit 14 and the common electrode 101 may be reduced, and static electricity generated in the display panel 100 may be discharged as soon as possible.
In some optional implementations of the present embodiment, the common electrodes 101 are block-shaped electrodes, and an orthogonal projection of each common electrode 101 to the substrate 110 may cover a plurality of pixel regions. The display panel 100 may further include common signal lines, and each of the common electrodes 101 may be electrically connected to at least one common signal line, and each of the common signal lines may be electrically connected to the driving chip. Further, the plurality of common electrodes 101 may be arranged in an array on the display panel 100, and each common electrode 101 may be reused as a touch electrode in the touch stage. The touch electrode receives the touch scanning signal in the touch stage, senses touch operation to generate a touch sensing signal, and then returns the touch sensing signal to the driving chip so that the driving chip can determine the touch position according to the returned touch sensing signal.
Referring to fig. 2a, a schematic structural diagram of a connection line between the electrostatic discharge unit and the shift register of the display panel 100 shown in fig. 1a is shown. As shown in fig. 2a, the connection line 26 between the electrostatic discharge unit 24 and the shift register 25 further includes a second sub-connection line 262 and a third sub-connection line 263, which are located outside the frame sealing glue region corresponding to the arc line, the second sub-connection line 262 connects the electrostatic discharge unit 24 and the first sub-connection line 261, and the third sub-connection line 263 connects the first sub-connection line 261 and the shift register 25.
In connection with fig. 2b, there is shown a schematic cross-sectional view of the structure shown in fig. 2a along the YY' direction. As shown in fig. 2b, the second sub-connecting line 262 includes a first section 2621 and a second section 2622, the first section 2621 is formed on the first metal layer, and the second section 2622 is formed on the first transparent electrode layer; the third sub-connection line 263 includes a third segment 2631 and a fourth segment 2632, wherein the third segment 2631 is formed on the first metal layer, and the fourth segment 2632 is formed on the first transparent electrode layer. The first metal layer is electrically connected to the first transparent electrode layer, that is, the first section 2621 is electrically connected to the second section 2622, and the third section 2631 is electrically connected to the fourth section 2632. Here, the first transparent electrode layer and the first metal layer are in contact with each other.
In the display panel provided by the above embodiment of the application, in order to improve the ultraviolet curing efficiency of the frame sealing adhesive in the frame sealing adhesive region corresponding to the arc line, the first sub-connecting line of the frame sealing adhesive region corresponding to the arc line is formed by the first transparent electrode layer, so that the transmittance of the frame sealing adhesive region corresponding to the arc line is increased, and the curing of the frame sealing adhesive in the region is facilitated; for other regions, because the amount of the frame sealing glue is less relative to that of the frame sealing glue in the region corresponding to the arc line, the connecting line arranged in the region is formed by connecting the first transparent electrode layer and the first metal layer in parallel, the resistance of the connecting line in the region can be effectively reduced, and meanwhile, the curing of the frame sealing glue in the region is not influenced; and the manufacture of the connecting wire can be integrated in the manufacture process of the grid electrode and the common electrode, the manufacture process difficulty of the display panel cannot be increased, and the manufacture cost is saved.
Fig. 3 is a schematic structural diagram of an electrostatic discharge unit of a display panel according to the present application, and as shown in fig. 3, the electrostatic discharge unit of the present embodiment includes a first transistor 301 and a second transistor 302. The gate of the first transistor 301, the first pole of the first transistor 301, and the second pole of the second transistor 302 are electrically connected to the shift register VSR; the second pole of the first transistor 301, the gate of the second transistor 302, and the first pole of the second transistor 302 are electrically connected to a common electrode.
In this embodiment, the output terminal of the shift register VSR is generally electrically connected to a plurality of scan lines for providing a shift signal to each scan line, and the input terminal thereof generally includes at least one clock signal line, at least one input signal line, and the like, and these input terminals are electrically connected to an electrostatic discharge unit, so that the static electricity generated on the scan lines can be introduced into the common electrode through the shift register VSR and discharged through the common electrode.
According to the display panel provided by the embodiment of the application, static electricity generated by the scanning lines can be released through the static electricity releasing unit, damage of the static electricity to the display panel is reduced, and the manufacturing yield of the display panel is improved.
FIG. 4 shows a flow 400 of one embodiment of a method of fabricating a display panel according to the present application. As shown in fig. 4, the method for manufacturing a display panel of the present embodiment includes the following steps:
step 401, a first transparent electrode layer, a first metal layer and a first photoresist layer are sequentially deposited on a substrate.
In this embodiment, the first transparent conductive layer may be formed by doping ions in a transparent metal oxide semiconductor. For example, metal ions, hydrogen ions, or the like are implanted into the transparent metal oxide semiconductor to increase the electrical conductivity of the first transparent conductive layer.
Step 402, forming a connecting line in a region corresponding to an arc line in the gate electrode, the common electrode and the frame sealing glue region by the first transparent electrode layer and the first metal layer through a photoetching process by using a first mask.
The central line of the frame sealing glue area comprises a plurality of line segments communicated by a plurality of arcs, the connecting line is used for electrically connecting the electrostatic discharge unit and the shift register, the connecting line comprises a first sub-connecting line, and the first sub-connecting line is formed on the first transparent electrode layer.
In this embodiment, a part of the connection line between the electrostatic discharge unit and the shift register is located in the frame sealing adhesive region corresponding to the arc line. Generally, the amount of the sealant coated at the corners of the rectangular display panel is large, which causes the sealant at the corners of the display panel to be difficult to be cured by ultraviolet rays. In this embodiment, the connecting line disposed in the frame sealing adhesive region (i.e., the corner region) corresponding to the arc line is formed only by the first transparent electrode layer, so that the transmittance of the frame sealing adhesive therein can be improved, and the ultraviolet curing efficiency of the frame sealing adhesive therein can be improved.
In this embodiment, the first mask may be a mask capable of forming a photoresist pattern having a thickness difference.
In some optional implementations of this embodiment, the step 402 may be specifically implemented by the following steps not shown in fig. 4:
forming a first photoresist pattern on the first photoresist layer by using a first mask through a photoetching process, wherein the first photoresist pattern covers a region corresponding to the grid electrode in the first metal layer and a region corresponding to the common electrode, and exposes a region corresponding to an arc line in the frame sealing glue region in the first metal layer; removing the exposed region by an etching process; and removing the first photoresist pattern.
In step 403, a first insulating layer, a polysilicon layer, a second metal layer and a second photoresist layer are sequentially deposited on the gate electrode and the common electrode.
In this embodiment, the polysilicon layer is used to provide carriers between the source and the drain of the thin film transistor.
In step 404, the polysilicon layer is formed into an active layer by a photolithography process using a second mask, and the second metal layer is formed into a source and a drain.
In step 405, a second insulating layer and a third photoresist layer are sequentially deposited on the source, drain and active layers.
In step 406, a via hole electrically connected to the source electrode is formed on the second insulating layer by a photolithography process using a third mask.
Step 407, a second transparent electrode layer and a fourth photoresist layer are sequentially deposited on the second insulating layer.
And step 408, forming a pixel electrode on the second transparent electrode layer by using a fourth mask through a photolithography process.
It will be understood by those skilled in the art that, in the manufacturing process of the array substrate, besides the process steps disclosed in the present embodiment, other well-known process steps (for example, a process of forming a substrate, etc.) are also included. In describing the method of fabricating the array substrate of the present embodiment, descriptions of these well-known process steps are omitted so as not to obscure the core process steps of the present embodiment.
The following further shows specific steps of forming the display panel of this embodiment with reference to fig. 4a to 4 i.
First, as shown in fig. 4a, a first transparent electrode layer 401, a first metal layer 402, and a first photoresist layer (not shown in fig. 4 a) are sequentially deposited on a substrate 410. Then, the first transparent electrode layer 401 and the first metal layer 402 are formed into the gate 411, the common electrode 412 and the connection line (not shown in fig. 4 b) in the region corresponding to the arc in the frame sealing glue region by a photolithography process using a first mask, as shown in fig. 4 b. A first insulating layer 403 is deposited on the gate 411, the common electrode 412 and the connecting lines in the region corresponding to the arc in the frame sealing glue region, as shown in fig. 4 c.
A polysilicon layer 404, a second metal layer 405 and a second photoresist layer (not shown in fig. 4 d) are sequentially deposited over the structure shown in fig. 4c, as shown in fig. 4 d. The polysilicon layer 404 is then formed into an active layer 413 by a photolithography process using a second mask, and the second metal layer 405 is formed into a drain 414 and a source 415, as shown in fig. 4 e. A second insulating layer 406 is deposited over the resulting structure of the active layer 413, the drain 414 and the source 415, as shown in fig. 4 f.
A third photoresist layer is deposited on the structure shown in fig. 4f, and then a via 416 connected to the source 415 is formed on the second insulating layer 406 by a photolithography process using a third mask, as shown in fig. 4 g. A second transparent electrode layer 407 and a fourth photoresist layer (not shown in fig. 4 h) are sequentially deposited on the second insulating layer 406 as shown in fig. 4 h. Then, a pixel electrode 417 is formed on the second transparent electrode layer 407 by a photolithography process using a fourth mask, as shown in fig. 4 i.
In some optional implementations of this embodiment, the first mask is a halftone mask.
In some optional implementations of the present embodiment, the first photoresist pattern further covers a region of the first metal layer 402 where the scan line is to be formed.
According to the manufacturing method of the display panel, the transmittance of the frame sealing glue in the corner area of the display panel is improved, so that the ultraviolet curing efficiency of the frame sealing glue is improved; meanwhile, only four mask plates are needed in the manufacturing process of the display panel, so that the manufacturing process flow of the display panel is effectively simplified, and the manufacturing efficiency of the display panel is improved.
As shown in fig. 5, the present application also provides a display device 500 including the display panel described in the above embodiments. According to the display device, the first sub-connecting lines located in the frame sealing glue area corresponding to the arc line are formed only by the first transparent electrode layer, so that the transmittance of the frame sealing glue area corresponding to the arc line is effectively increased, and the ultraviolet curing efficiency of the frame sealing glue is improved.
The above description is only a preferred embodiment of the application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (10)

1. A display panel, comprising a display area and a non-display area, the non-display area surrounding the display area;
the display area comprises a common electrode, a plurality of data lines extending along a first direction and a plurality of scanning lines extending along a second direction;
the common electrode is formed on the first transparent electrode layer and the first metal layer;
a plurality of data lines and a plurality of scanning lines are crossed to define a plurality of pixel regions, and each pixel region comprises a pixel electrode and a thin film transistor electrically connected with the pixel electrode;
the thin film transistor includes a gate electrode, a source electrode, a drain electrode, and an active layer forming a conductive channel between the source electrode and the drain electrode;
the grid electrode is formed on the first metal layer, the source electrode and the drain electrode are formed on the second metal layer, the active layer is formed between the first metal layer and the second metal layer, and the pixel electrode is formed on the second transparent electrode layer;
the drain electrode is electrically connected with the pixel electrode through a via hole;
a first insulating layer is formed between the first metal layer and the active layer, and a second insulating layer is formed between the second metal layer and the second transparent electrode layer;
the non-display area comprises an electrostatic discharge unit, a shift register and a frame sealing glue area surrounding the display area;
the electrostatic discharge unit is electrically connected with the common electrode and the shift register, and the shift register is electrically connected with the plurality of scanning lines;
the central line of the frame sealing glue area comprises a plurality of line segments communicated by a plurality of arc lines;
a part of a connecting line of the electrostatic discharge unit and the shift register is positioned in the frame sealing glue area corresponding to the arc line;
the connecting lines comprise first sub-connecting lines in the frame sealing glue area corresponding to the arc lines, and the first sub-connecting lines are formed on the first transparent electrode layer;
the connecting lines further comprise a second sub-connecting line and a third sub-connecting line outside the frame sealing glue area corresponding to the arc line;
the second sub-connecting line is connected with the electrostatic discharge unit and the first sub-connecting line;
the second sub-connecting line comprises a first section formed on the first metal layer and a second section formed on the first transparent electrode layer;
the third sub-connecting line is connected with the first sub-connecting line and the shift register;
the third sub-connecting line comprises a third segment formed on the first metal layer and a fourth segment formed on the first transparent electrode layer;
the first metal layer is electrically connected with the first transparent electrode layer.
2. The display panel according to claim 1, wherein the electrostatic discharge unit is located between the frame sealing glue region and the display region.
3. The display panel according to claim 1, wherein the electrostatic discharge unit includes a first transistor and a second transistor;
the grid electrode of the first transistor, the first pole of the first transistor and the second pole of the second transistor are electrically connected with the shift register;
the second pole of the first transistor, the gate of the second transistor, and the first pole of the second transistor are electrically connected to the common electrode.
4. The display panel according to any one of claims 1 to 3, wherein the common electrode is a block electrode, a plurality of the common electrodes are arranged in an array on the display panel, and each of the common electrodes is multiplexed as a touch electrode in a touch phase.
5. The display panel according to claim 4, wherein the display panel further comprises common signal lines, each of which is electrically connected to the common electrode.
6. A method for manufacturing a display panel, the display panel comprising a substrate, the method comprising:
depositing a first transparent electrode layer, a first metal layer and a first photoresist layer on the substrate in sequence;
forming a grid electrode, a common electrode and a connecting line in an arc line corresponding region in a frame sealing glue region by using a first mask through a photoetching process, wherein the central line of the frame sealing glue region comprises a plurality of line segments communicated by a plurality of arc lines, the connecting line is used for electrically connecting an electrostatic discharge unit and a shift register, and comprises a first sub-connecting line formed on the first transparent electrode layer;
the connecting lines further comprise a second sub-connecting line and a third sub-connecting line outside the frame sealing glue area corresponding to the arc line; the second sub-connecting line is connected with the electrostatic discharge unit and the first sub-connecting line; the second sub-connecting line comprises a first section formed on the first metal layer and a second section formed on the first transparent electrode layer; the third sub-connecting line is connected with the first sub-connecting line and the shift register; the third sub-connecting line comprises a third segment formed on the first metal layer and a fourth segment formed on the first transparent electrode layer; the first metal layer is electrically connected with the first transparent electrode layer; depositing a first insulating layer, a polycrystalline silicon layer, a second metal layer and a second photoresist layer on the grid and the common electrode in sequence;
forming an active layer on the polycrystalline silicon layer by using a second mask through a photoetching process, and forming a source electrode and a drain electrode on the second metal layer;
sequentially depositing a second insulating layer and a third photoresist layer on the source electrode, the drain electrode and the active layer;
forming a via hole connected with the drain electrode on the second insulating layer by utilizing a third mask through a photoetching process;
depositing a second transparent electrode layer and a fourth photoresist layer on the second insulating layer in sequence;
and forming a pixel electrode on the second transparent electrode layer by using a fourth mask through a photoetching process.
7. The method according to claim 6, wherein the forming the first transparent electrode layer and the first metal layer into the connection line in the region corresponding to the arc line in the gate electrode, the common electrode and the frame sealing glue region by the photolithography process using the first mask comprises:
forming a first photoresist pattern on the first photoresist layer by using the first mask through a photoetching process, wherein the first photoresist pattern covers a region corresponding to the grid electrode and a region corresponding to the common electrode in the first metal layer, and exposes a region corresponding to an arc line in a frame sealing glue region in the first metal layer;
removing the exposed region by an etching process;
and removing the first photoresist pattern.
8. The method of claim 7, wherein the first reticle is a halftone reticle.
9. The method of claim 7, wherein the first photoresist pattern covers a region of the first metal layer where a scan line is to be formed.
10. A display device characterized in that it comprises a display panel as claimed in any one of claims 1 to 5.
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