JP2780681B2 - Active matrix liquid crystal display panel and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel, and more particularly to a liquid crystal display panel having a structure in which a liquid crystal is sandwiched between transparent insulating substrates having thin film field effect transistors and electrodes, and a method for manufacturing the same.

[0002]

2. Description of the Related Art Thin film field effect transistors ("TF")
T ") as a switching element of a pixel (" AMLC ").
D) has high quality image quality, and is widely applied to display devices of portable computers and light valves of projection display devices.

An active matrix liquid crystal display panel is
In general, a liquid crystal is sandwiched between a TFT substrate having a structure in which a pixel electrode connected to a scanning line, a signal line, and a thin film transistor arranged in the vicinity of an intersection thereof and a counter substrate having a transparent electrode formed on the entire surface to control a pixel. By applying a voltage between the electrode and the counter electrode, the amount of transmitted light in the corresponding pixel is controlled.

[0004] In the active matrix liquid crystal display device thus constructed, the potential between the electrodes sandwiching the liquid crystal is easily controlled, and the high quality liquid crystal display device is excellent in contrast and viewing angle as compared with a simple matrix type liquid crystal display device. The biggest feature is that the display can be obtained.

However, in constructing an active matrix liquid crystal display device, it is necessary to form a TFT array in a matrix.

[0006] This process is very similar to the process performed in the manufacture of a semiconductor device. However, in the case of a TFT array, one device must be manufactured in the same area as the display area of the display device. This is essentially different in that cost reduction cannot be achieved by obtaining a large number of devices from one substrate by reducing the size of the device.

[0007] On the other hand, the price is one of the major problems in further spreading the active matrix liquid crystal display device in the future, and there is a great demand for reducing the cost of manufacturing a TFT array.

It is known that reducing the number of times of pattern formation using photolithography (PR) (referred to as “PR number”) has a great effect in reducing costs related to TFT array manufacturing. Have been.

From this point of view, several steps with a small number of PRs have been proposed. For example, literature (1982SID
(Society for Information Display) International Sy
mposium Digest of Technical Papers, p. 44)
A method of making the number of PR twice is introduced.

In this method, first, a transparent electrode and an n-type amorphous silicon layer are deposited, and patterning is performed by photolithography (PR) using patterns of signal lines, TFT source / drain electrodes, and pixel electrodes. Deposit non-doped amorphous silicon layer, gate insulating film, metal layer,
The metal layer, the gate insulating film, the non-doped amorphous silicon layer, and the n-type amorphous silicon layer deposited by the scanning line pattern are etched.

Although this method requires a very small number of PRs of two, the signal lines are formed of transparent electrodes, so that the electrical resistance is large, and a signal is delayed in a large area (large liquid crystal panel). Therefore, it cannot be put to practical use.

If the signal line is formed of another metal layer, the electric resistance can be reduced, but a PR process for forming the signal line is required separately.

Further, in the case of this structure, when light enters from the substrate side, it directly enters the channel of the TFT, and there is a problem that the off-resistance of the TFT is reduced and the charge of the pixel cannot be held.

In order to avoid this problem, it is necessary to dispose an opaque layer electrically insulated from at least one of the source electrode and the drain electrode of the TFT under the TFT so as to cover the channel.

In order to form such an opaque layer,
Further, it is necessary to add one photolithography (PR) step. Therefore, at least 4 PR is required in order to obtain a TFT array capable of obtaining a stable, high-quality display in a large area without difficulty in terms of process.

Further, another problem of the above-mentioned prior art is that it has a so-called forward staggered TFT structure in which a gate electrode is disposed above a channel.

It is known that the ON current of a TFT flows by electrons accumulated at a so-called MIS interface between a gate insulating film and a channel amorphous silicon layer.

In the forward staggered structure, since the gate insulating film is formed after the channel amorphous silicon layer is formed, the MIS interface is damaged by the plasma impact at the time of forming the gate insulating film. I will.

When the inverted staggered type and the forward staggered type are compared with each other for the same size TFT, the inverted staggered type TFT has better ON characteristics. For this reason, when designing a TFT array using a forward staggered TFT, it is necessary to increase the channel width of the TFT, which causes a change in pixel potential due to a change in gate voltage at the end of writing to the pixel electrode.
Since the so-called feed-through voltage increases, the load on the drive circuit increases in order to maintain display quality.

Therefore, in general, higher quality pixels can be obtained by using an inverted staggered type TFT (also referred to as an “inverted staggered type”).

The inverse staggered TFT requires at least a pattern of a scanning line, a pattern of channel amorphous silicon, a pattern of a pixel electrode, a pattern of a signal line, and a pattern for exposing the scanning line at a peripheral terminal portion.

Further, in the inverted staggered type TFT, since the channel is exposed on the liquid crystal layer side, an insulating film such as a silicon nitride film is usually formed on the channel in order to protect the TFT from the electric influence of the alignment film or the liquid crystal. Is used as passivation.

In the case where the passivation is provided as described above, a pattern for exposing the signal line at the peripheral terminal portion,
A pattern for exposing the pixel electrode is required.

In consideration of this, even if the pattern for exposing the scanning lines and the signal lines and the pattern for exposing the pixel electrodes are formed by the same mask in the peripheral terminal portion, the other patterns are formed by independent masks. A total of five PR steps are required.

Therefore, as in the case of the forward staggered type, 4
In order to do this below the PR, one of the patterns must be formed by one other pattern or a combination of multiple patterns.

Although it is possible to form a pixel electrode and a signal line with the same pattern in terms of shape, it is necessary to use a transparent electrode for the signal line. It becomes difficult.

In addition, the pattern of the signal line and the channel amorphous silicon cannot be completely matched in principle.

Further, since it is necessary to arrange the scanning lines and the signal lines so as to cross each other, it is impossible to form them with the same pattern.

Considering the above, it seems that it is most promising to make the pattern of the scanning line coincide with the pattern of the channel amorphous silicon.

As a conventional method of matching the pattern of the scanning line with the pattern of the channel amorphous silicon, for example, Japanese Patent Application Laid-Open No. 63-18286
No. 2 discloses a method of manufacturing a TFT having an inverted stagger structure in which a gate electrode and an island portion are formed by collectively etching in a single photoresist process, thereby simplifying the process and improving the yield. Proposed. That is, the publication discloses that, after laminating a metal film for a gate electrode, a gate insulating film, and a semiconductor film, these are collectively patterned by a pattern of a scanning line, and then the sidewalls of the gate electrode are insulated. 8 has been proposed. In FIG. 8, 1 is a scanning line (gate electrode), 3 is a drain electrode, 4 is a source electrode, 9 is a glass substrate, 10 is a gate insulating film (silicon nitride), 11 is a semiconductor film (amorphous silicon film), Reference numeral 13 denotes an N ⁺ amorphous silicon layer serving as a contact portion, and reference numeral 20 denotes a region where the gate side wall is insulated by anodic oxidation (side wall insulating film Ta ₂ O ₅ ).
It is.

By using such a method, four times or less of P
It becomes possible to manufacture a TFT array in the R step.

[0032]

However, the method shown as the prior art in FIG. 8 requires a technique for selectively insulating only the end face of the gate electrode.

This is very difficult to control because it is greatly affected by the cross-sectional shape, and the probability of occurrence of insufficient insulation is high. Scanning lines and signal lines are short-circuited at such locations, and Line defects often appear on the display device.

Accordingly, the present invention has been made in view of the above problems, and an inverted staggered TFT array capable of obtaining high display quality four times without using such a difficult-to-control process. An object of the present invention is to provide an active matrix liquid crystal display panel having a structure that can be manufactured in the following number of PRs and can be manufactured at low cost, and a manufacturing method.

[0035]

In order to achieve the above object, the present invention comprises a plurality of parallel scanning lines and a plurality of parallel signal lines which are arranged in a grid and intersect with each other. A gate electrode provided near the intersection of the signal line and the signal line and formed on the same layer as the scanning line and connected to the scanning line; and a thin film semiconductor provided on the gate electrode via a gate insulating film. A first electrode provided on the thin film semiconductor layer and electrically connected to the signal line and a second electrode connected to the pixel electrode (provided that the first electrode is a source (drain) electrode; A second electrode is a drain (source) electrode), a first transparent insulating substrate formed with a thin film transistor formed of the thin film transistor, and a second transparent insulating substrate having a transparent electrode are attached with a liquid crystal layer interposed therebetween. LCD display panel The gate insulating film and the thin film semiconductor layer are patterned with the same pattern as the pattern including the scanning line and the gate electrode except for a peripheral terminal connection portion, and the first and second electrodes are formed of the thin film. In a predetermined region on the semiconductor layer, the pixel electrode is formed of the same layer as the pixel electrode, a protective insulating film is provided so as to cover the first and second electrodes and the thin-film semiconductor layer, and the signal insulating film is formed on the protective insulating film. A signal line, the signal line and the first electrode are connected via a contact hole formed in a predetermined region on the first electrode, and a metal formed on the same layer as the signal line. A liquid crystal display panel is provided, wherein the second electrode and the pixel electrode are electrically connected via a contact hole by a layer.

According to the present invention, there are provided a plurality of parallel scanning lines and a plurality of parallel signal lines which are arranged in a grid and cross each other, and are provided near each intersection of the scanning lines and the signal lines. It is formed in the same layer as the scanning lines with the run
And a gate electrode connected to 査 line, wherein the thin film semiconductor layer formed via a gate insulating film on the gate electrode, a first electrode connected is provided on the thin film semiconductor layer wherein the signal lines and electrically And a second electrode connected to the pixel electrode (however, when the first electrode is a source (drain) electrode, the second electrode is a drain (source) electrode). In a liquid crystal display panel in which a transparent insulating substrate and a second transparent insulating substrate having a transparent electrode are bonded together via a liquid crystal layer, the liquid crystal display panel has a structure in which the scanning lines and the gate electrode are separated except for a peripheral terminal connection portion. The gate insulating film and the thin film semiconductor layer are patterned by the same pattern as the first pattern and the first and second electrodes are formed in the same layer as the pixel electrode in a predetermined region on the thin film semiconductor layer. A protection insulating film is provided so as to cover the first and second electrodes and the thin film semiconductor layer, and a signal line is provided on the protection insulating film, and the signal line and the first electrode are connected to each other. The first electrode is connected through a contact hole, and the second electrode and the pixel electrode are connected through a contact hole by a metal layer formed in the same layer as the signal line. , Ji of the first contact hole formed on the second electrode
Boundary Yaneru side, the boundary of the channel side of the first and second electrodes are formed in the channel inner, impurities are doped by ion implantation into the thin film semiconductor layer under the opening end region of the contact hole The present invention provides a liquid crystal display panel characterized in that the liquid crystal display panel has an inclined region.

In a preferred embodiment of the active matrix liquid crystal display panel according to the present invention, a pattern formed of the same layer as the scanning lines and separated from the scanning lines and electrically connected to the pixel electrodes overlaps with the signal lines. In this way, they are arranged on both sides of the pixel electrode. With this configuration, a layer that blocks light leakage from the region where the TN liquid crystal operation between the pixel electrode and the signal line is not normally performed on the TFT substrate side can be formed without increasing the number of steps. . Such a layer is composed of a black matrix and a TF which are usually provided on the counter substrate side.
The alignment accuracy of the T-substrate can be greatly relaxed, and this can be used to improve the aperture ratio.

In a preferred embodiment of the active matrix liquid crystal display panel according to the present invention, a pattern formed in the same layer as the signal line, separated from the signal line and electrically connected to a pixel electrode is used for the scanning. It can be arranged on both sides of the pixel electrode so as to overlap with the line. With this configuration, a layer that blocks light leakage from the region where the TN liquid crystal operation between the pixel electrode and the scanning line is not normally performed on the TFT substrate side can be formed without increasing the number of steps. . Such a layer greatly reduces the alignment accuracy between the black matrix usually provided on the counter substrate side and the TFT substrate, and can be used to improve the aperture ratio.

Further, in a preferred embodiment of the active matrix liquid crystal display panel according to the present invention, a pattern formed in the same layer as the signal lines can be arranged so as to cover a channel region of the thin film transistor.
This makes it possible to manufacture a layer for shielding the back channel side of the TFT from light without increasing the number of steps.

Further, in a preferred embodiment of the active matrix liquid crystal display panel according to the present invention, a pattern formed in the same layer as the signal line, separated from the signal line and electrically connected to a pixel electrode is provided in the pixel. The two scanning lines adjacent to the electrode are arranged so as to overlap with the scanning line that does not control the thin film transistor that supplies the electric charge to the pixel electrode, and are partially isolated on the same layer as the pixel electrode in a part of the overlapping region. A pattern is formed, and a capacitor is formed between the isolated pattern and the scanning line with a gate insulating film layer interposed therebetween, and the isolated pattern can be electrically connected to the pixel electrode. In this manner, a storage capacitor which is usually provided to assist in holding the charge of the pixel electrode can be manufactured without increasing the number of steps.

The present invention relates to a liquid crystal display (L) including an inverted staggered thin film transistor (TFT) array.
CD) manufacturing method, (a) after forming a metal film, a gate insulating film, and a semiconductor film serving as a scanning line in this order on a transparent insulating substrate, patterning them in the same pattern, (b) pixel electrode, The first and second electrodes are formed of the same layer and are patterned by one photolithography. (C) A protective insulating film is formed so as to cover the pixel electrode, the first and second electrodes. (D) the first electrode and the signal line
A contact hole you arranged with respect to the protective insulating film on said first electrode to connect the door, the second electrode
And on the second electrode to connect the pixel electrode
A contact hole provided for the protective insulating film;
In order to connect the pixel electrode and the second electrode,
A contact arranged on the pixel electrode with respect to the protective insulating film
To supply signals to the scanning lines
In order to connect the scanning lines to the scanning line terminals formed on the same layer as
Forming a predetermined contact hole provided on the scanning line by opening the protective insulating film, the semiconductor film and the gate insulating film by one photolithography, and (e) forming a metal film Forming a signal line connected to the first electrode, and a metal layer connecting the second electrode and the pixel electrode by one photolithography ,
A method of manufacturing a liquid crystal display device including the above steps is provided.

[0042]

In the TFT array of the active matrix liquid crystal display panel of the present invention, after forming a metal film, a gate insulating film, and a channel amorphous silicon film serving as scanning lines, these are patterned with the same pattern. And the source / drain electrodes are composed of the same layer, and they are patterned by one photolithography (PR), and a protective insulating film is further provided thereon. The protective insulating film, the channel amorphous silicon, and the gate insulating film On the other hand, a contact hole in a necessary portion is formed by one PR, a metal film to be a signal line is formed thereafter, and a signal line connected to a drain electrode of the TFT, a source electrode and a pixel electrode of the TFT are formed. Can be manufactured by forming the same pattern as the wiring for connecting.

Therefore, according to the present invention, it is possible to fabricate a reverse staggered type TFT array having characteristics superior to that of a forward staggered type in four or fewer PR steps. An active matrix liquid crystal display with excellent image quality at low cost can be obtained.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

[0045]

Embodiment 1 FIG. 1 is a plan view showing a pixel portion of a TFT array of an active matrix liquid crystal display panel according to a first embodiment of the present invention, and FIG.
FIG. 2B shows a cross section taken along the line A ′, and FIG. 2B shows a cross section taken along the line BB ′ in FIG.

Referring to FIGS. 1 and 2, a plurality of scanning lines 1 and a plurality of signal lines 2 are crossed on a light-transmitting insulating substrate (also referred to as a “glass substrate”) 9 such as a glass plate. Arrange them in a grid.

In each lattice, a set of active pixel elements each including a TFT disposed near the intersection of the scanning line 1 and the signal line 2 and a pixel electrode 6 driven by the TFT are disposed. You.

The TFT has a scanning line 1 as a gate electrode, a channel portion made of an amorphous silicon film 11 provided on the gate electrode with an insulating film (gate insulating film) 10 interposed therebetween, and a TFT formed of the amorphous silicon film 11. It comprises a drain electrode 3 and a source electrode 4 provided on the surface.

Then, a protective insulating film 12 is formed so as to cover the amorphous silicon film 11, the drain electrode 3, and the source electrode 4.
Is provided.

Further, the signal line 2 is formed on the protective insulating film 12.
And a wiring 7 for electrically connecting the source electrode 4 to the pixel electrode 6.

The signal line 2 and the drain electrode 3 are connected via a contact hole 5 formed on the drain electrode 3.

FIG. 7 shows the configuration of the peripheral terminal section in the present embodiment.

Referring to FIG. 7, the signal lines 2 are formed on the uppermost layer at the time of formation, and therefore are formed integrally with the peripheral signal line terminals 23 as they are.

On the other hand, the scanning line 1 is connected to the gate insulating film 10.
(See FIG. 2), a contact hole 22 for taking out a terminal of the scanning line 1 is provided.
Is provided at the end of the
It is connected to a scanning line terminal 21 provided on the protective insulating film 12.

Hereinafter, a method for manufacturing a TFT array of an active matrix liquid crystal display panel according to this embodiment will be described in the order of steps.

First, a chromium film serving as a scanning line 1 is deposited to a thickness of 100 nm on a light-transmitting insulating substrate (glass substrate) by sputtering, and then a nitride film serving as a gate insulating film 10 is formed on this surface. After depositing a silicon film to a thickness of 500 nm,
A 00 nm amorphous silicon film 11 and a 10 nm thick n-type amorphous silicon layer 13 are sequentially deposited.

Thereafter, photolithography (referred to as "PR") is performed using the pattern of the scanning line 1, and n
The type amorphous silicon layer 13, the amorphous silicon film 11, and the silicon nitride film 10 are collectively etched. This etching can be performed by dry etching using plasma of CF ₄ gas, for example.

Thereafter, the chromium film serving as the scanning line 1 is etched to remove the resist.

Next, an ITO (Indium-Tin-Oxide) film is deposited to a thickness of 50 nm. Here, photolithography (PR) is performed using a pattern including the pixel electrode 5, the drain electrode 3, and the source electrode 4, and the ITO film is etched using hydrochloric acid.

Thereafter, the resist is removed, and the drain and source electrodes 3 and 4 made of ITO are used as a mask to remove n.
The total thickness of the amorphous silicon film 13 and the amorphous silicon film 11 is about 30 nm.

Thus, in the region where the source and drain electrodes made of ITO do not exist, the n-type amorphous silicon layer
13 is completely removed.

Next, a silicon oxide film having a thickness of 500 nm is deposited as the protective insulating film 12 by using a normal pressure CVD method.

Here, the pattern of the contact hole 5 used to connect the drain electrode 3 of the TFT and the signal line 2 and the pattern of the contact hole 5 ′ used to connect the wiring 7 connecting the source electrode 4 and the pixel electrode 6, PR is performed using an inverted pattern of the pattern of the region 8 on the electrode 6 where the protective insulating film 12 is to be removed and the pattern of the contact hole 22 for taking out the terminal of the scanning line 1.

Using this pattern, dry etching is performed by plasma of CF ₄ gas.

At this time, the protective insulating film 12 is etched in the contact hole portions 5 and 5 'on the drain electrode 3 and the source 4 electrode of the TFT, but the drain and source electrodes 3 and 4 made of ITO are etched stoppers. Becomes

In the region 8 where the protective insulating film 12 on the pixel electrode 6 is removed, only the protective insulating film 12 is similarly etched.

On the other hand, in the contact hole 22 for taking out the terminal of the scanning line 1, after the silicon oxide film formed as the protective insulating film 12 is etched, the amorphous silicon layer 11 and the gate insulating film are removed. 10 is subsequently etched, and the scanning line 1 formed of chromium becomes an etch stopper.

In this manner, the drain and source electrodes 3 and 4 in the contact hole portions 5 and 5 'on the source / drain electrodes of the TFT and the protective insulating film on the pixel electrode are removed by one etching. In the region 8, the pixel electrode 6 is exposed on the surface, and in the contact hole 22 for extracting a terminal of the peripheral scanning line, the scanning line 1 is exposed on the surface. In this state, the resist is removed.

Next, a chromium film is deposited to a thickness of 200 nm.
Here, the pattern of the signal line 2, the source electrode 4 and the pixel electrode 6
The PR is performed using a pattern including the pattern of the wiring 7 for connecting the two, the pattern of the signal line terminal 23, and the pattern of the scanning line terminal 21.

With this pattern, the chromium film is etched and the resist is removed.

As described above, the TF according to the present embodiment
The T array is completed.

As described above, the number of PRs performed in the process of manufacturing the TFT array of the active matrix liquid crystal display panel according to the present embodiment is only four. In addition, all processes performed in this step are extremely stable, and can be manufactured with very high yield. Therefore, according to the present embodiment, a high-throughput, low-cost active matrix liquid crystal display panel can be stably manufactured.

[0073]

Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 3 is a plan view of a pixel portion of a TFT array of an active matrix liquid crystal display panel according to a second embodiment of the present invention. FIG. 4A shows a cross section taken along line CC 'in FIG. 3, and FIG. 4B shows a cross section taken along line DD' in FIG.

Referring to FIGS. 3 and 4, a plurality of scanning lines 1 and a plurality of signal lines 2 are arranged in a grid on a light-transmitting insulating substrate 9 such as a glass plate. Each of the grids includes a TFT disposed near an intersection of the scanning line 1 and the signal line 2 and a pixel electrode 6 driven by the TFT.
Each set of active pixel elements is arranged.

The TFT has the scanning line 1 as a gate electrode, a channel portion made of an amorphous silicon film 11 provided on the gate electrode via an insulating film 10, and a TFT provided on the surface of the amorphous silicon film 11. And a drain electrode 3 and a source electrode 4.

Further, a protective insulating film is formed so as to cover the amorphous silicon film 11, the drain electrode 3 and the source electrode 4.
There are twelve. Then, the signal line 2 and the wiring 7 connecting the source electrode and the pixel electrode are formed on the protective insulating film 12.
Further, a TFT light shielding layer 24 is provided.

At this time, as shown in FIG. 3, the wiring 7 connecting the source electrode 4 and the pixel electrode 6 covers the periphery of the pixel electrode 6 and is arranged so as to overlap the adjacent scanning lines.

A pattern 14 is provided between the pixel electrode 6 and two signal lines 2 adjacent to the pixel electrode 6 so as to overlap with the signal lines.

A contact hole 5 ″ is formed on the pattern 14 at a position sufficiently distant from the signal line 2, and the source electrode 4
The lowermost metal layer 16 of the pattern 14 is connected to the wiring 7 connecting the pixel electrode 6 and the pixel electrode 6 (see FIG. 4A).

The signal line 2 and the drain electrode 3 are connected via a contact hole 5 formed on the drain electrode 3. Further, the TFT light shielding layer 24 is formed so as to cover the channel portion of the TFT.

A storage capacitor electrode 15 is formed on a part of the scanning line 1 in the same layer as the source / drain electrodes. A storage capacitor is formed between the storage capacitor electrode 15 and the scanning line 1, and plays a role of stabilizing the charge retention of the pixel.

A contact hole 5 "" is formed on the storage capacitor electrode 15, and the storage capacitor electrode 15 and the wiring 7 connecting the source electrode 4 and the pixel electrode 6 are connected via the contact hole 5 "".

At this time, the wiring 7 connecting the source electrode 4 and the pixel electrode 6 is configured to cover the storage capacitor electrode 15. In this case, the wiring 7 itself functions as a light-shielding layer, and the amorphous silicon film 11 around the storage capacitor electrode 15 is irradiated with light to increase the conductivity. The phenomenon that charge leaks to the electrode 3 can be prevented.

FIG. 7 shows the configuration of the peripheral terminal section in this embodiment. In the present embodiment, since the signal line is exposed to the uppermost layer at the time of formation, it is integrally formed with the peripheral signal line terminal 23 as it is. On the contrary,
Since the scanning line 1 is disposed below the gate insulating film 10,
Contact hole 22 for taking out the terminal of the scanning line
Are provided at the ends of the scanning lines 1 and are connected to the scanning line terminals 21 provided on the protective insulating film 12 via the contact holes 22.

The TFT constituting the liquid crystal panel of the present embodiment
The array is made as follows.

First, the scanning line 1, the gate insulating film 10, and the amorphous silicon layer 11 are formed in the same pattern as in the first embodiment. At this time, a pattern 14 that overlaps with the signal line is formed at the same time.

Next, as in the case of the first embodiment, the drain electrode 3, the source electrode 4, and the pixel electrode 6 are formed.
Is formed using a transparent conductive layer. At this time, the storage capacitor electrode 15 is formed at the same time.

Further, in the same manner as in the first embodiment, contact holes 5, 5 'on the source / drain electrodes and contact holes 22 for taking out the terminals of the scanning lines at the peripheral terminal connection portion are formed. Form.

At this time, a contact hole 5 ″ on the pattern 14 overlapping with the signal line and a contact hole 5 ″ ″ on the storage capacitor electrode 15 are formed at the same time.

Thereafter, the signal line 2, the wiring 7 connecting the source electrode and the pixel electrode, and the TFT light shielding layer 24 are formed. At this time, the wiring 7 connecting the source electrode 4 and the pixel electrode 6
Are also connected to the pattern 14 and the storage capacitor electrode 15 which overlap the signal line as described above.

As described above, the TFT array according to the second embodiment of the present invention is completed. At the boundary between the pixel electrode 6 and the signal line 2 or at the boundary between the pixel electrode 6 and the scanning line 1, a strong horizontal electric field exists, and the liquid crystal alignment is disturbed. The influence reaches the inside of the pixel electrode 6. Abnormality of transmitted light occurs in the periphery.

When such transmitted light appears on the display, a decrease in contrast and burn-in occur. In order to prevent this, a black matrix is usually provided on the counter substrate side to shield the area where the transmitted light abnormality occurs.

In the case of the TFT array of the present embodiment, most of the area where the transmitted light abnormality occurs is opaque due to the pattern 14 overlapping the signal line and the wiring 7 connecting the source electrode and the pixel electrode. Covered with metal,
Abnormal transmitted light is blocked by these patterns.

The light incident from the back channel side of the TFT is also shielded by the TFT light shielding layer 24. Therefore, there is no need to dispose a black matrix on the counter substrate side, and the device can be manufactured at lower cost than a configuration using a black matrix.

Further, in this embodiment, since it is not necessary to allow for a margin for misalignment required when a black matrix is provided on the counter substrate side, the width of light shielding can be reduced, and the aperture ratio can be further increased. Can be higher.

In the present embodiment, since the storage capacitor is formed for each pixel, the charge retention characteristics of the pixel become better and the display is stabilized.

When the storage capacitor is provided, it can be formed by simply overlapping the wiring 7 connecting the scanning line 1 with the source electrode and the pixel electrode. In the case of this embodiment, the storage capacitor is formed on the amorphous silicon layer. Since the storage capacitor electrode 15 is provided, a sufficiently large storage capacitor can be prepared with a small area.

When light is irradiated around the storage capacitor electrode 15, the amorphous silicon film 11 in the region irradiated with the light is irradiated.
, The electric charge leaks through this layer.

However, in the case of this embodiment, since the periphery of the storage capacitor electrode 15 is shielded from light by the wiring 7 connecting the source electrode 4 and the pixel electrode 6, the leak current can be extremely reduced.

In the process of fabricating the TFT array of the active matrix liquid crystal display panel shown in the present embodiment, the number of PR circuits performed is exactly four as in the case of the first embodiment. All of the processes performed in that step are extremely stable and can be manufactured with a very high yield. From the above, a high-throughput and low-cost active matrix liquid crystal display panel can be stably manufactured.

As an embodiment of the present invention, even when the technical contents described in claims 3 to 6 are applied to a liquid crystal panel alone or in combination of a plurality of them,
Depending on the situation, each effect can be obtained. In this case, it may be necessary to provide a black matrix on the counter substrate side, but the alignment of the counter substrate is eased as compared with the case where these methods are not applied at all.

[0102]

Third Embodiment Next, a third embodiment of the present invention will be described.

FIG. 5 is a plan view of a TFT section according to the third embodiment of the present invention. FIG.
FIG. 6B is a cross-sectional view taken along line FF ′ of FIG. 5.

The active matrix liquid crystal panel of the third embodiment of the present invention has exactly the same structure as the panel of the first embodiment except for the source / drain electrode portions of the TFT.

In the case of this embodiment, an n-type amorphous silicon layer 17 formed by ion doping is provided below and around the drain electrode 3 and the source electrode 4 which are composed of transparent electrodes such as ITO.

A contact hole for connecting the drain electrode 3 and the signal line 2 and a contact hole for connecting the source electrode 4 and the wiring 7 (connecting the source electrode 4 and the pixel electrode 6) are side-etched. As a result, the shape shown in FIG.

Hereinafter, the TFT array of the liquid crystal panel of the present embodiment is manufactured as follows.

First, a chromium film serving as the scanning line 1 is deposited to a thickness of 100 nm on a light-transmitting insulating substrate by sputtering, and a silicon nitride film serving as the gate insulating film 10 is then formed on this surface to a thickness of 500 nm. After the deposition, the amorphous silicon film 11 having a thickness of 200 nm is sequentially deposited.

Thereafter, PR is performed using the pattern of the scanning line 1, and the amorphous silicon film and the silicon nitride film are collectively etched using this pattern.

This etching can be performed by dry etching using, for example, plasma of CF ₄ gas. Thereafter, the chromium film is etched to remove the resist.

Next, an ITO film is deposited to a thickness of 30 nm. Here, the pixel electrode 6, the drain electrode 3, and the source electrode 4
PR is performed using a pattern consisting of: and the ITO is etched using hydrochloric acid. Thereafter, the resist is removed.

Next, a silicon oxide film is deposited to a thickness of 500 nm as a protective insulating film by using a normal pressure CVD method.

Here, a pattern shown as 18 as a contact hole used for connection between the drain electrode 3 of the TFT and the signal line 2 and connection between the source electrode 4 and the wiring 7 (connecting the source electrode 4 and the pixel electrode 6) and a pixel PR is performed using an inverted pattern of the pattern of the region 8 from which the protective insulating film on the electrode is to be removed and the pattern of the contact hole 22 for extracting a scanning line terminal.

Using this pattern, dry etching is performed by plasma of CF ₄ gas. At this time, the protective insulating film 12 is etched in the contact holes on the source / drain electrodes of the TFT, but the source / drain electrodes formed of ITO serve as an etch stopper. Also,
Similarly, only the protective insulating film is etched in the region 8 on the pixel electrode 6 where the protective insulating film is to be removed.

On the other hand, in the contact hole 22 for taking out the terminal of the scanning line, after the silicon oxide film formed as the protective insulating film is etched, the amorphous silicon layer 11 and the gate insulating film 10 are removed. Subsequently, the etching is performed, and the scanning line 1 formed of chromium serves as an etch stopper.

As described above, the drain and source electrodes 3 and 4 in the contact hole portion 18 on the source and drain electrodes of the TFT and the region 8 where the protective insulating film on the pixel electrode is removed are formed by one etching. The pixel electrode 6
In the contact holes 22 for taking out the terminals of the peripheral scanning lines, the scanning lines 1 are each exposed on the surface.

Here, while the resist is still covered, the silicon oxide film formed as the protective insulating film 12 is side-etched with dilute hydrofluoric acid, and the contact hole is widened to the pattern indicated by 19 in FIGS. In this state, the resist is removed.

Further, phosphorus ions are implanted at an acceleration voltage of 40 kV. At this time, the protective insulating film 12 serves as a mask for ion implantation, and phosphorus is doped under and around the drain and source electrodes 3 and 4 made of ITO,
N-type amorphous silicon layer formed by ion doping
17 is formed.

Next, chromic acid is deposited to a thickness of 200 nm.
Here, the pattern of the signal line 2, the source electrode 4 and the pixel electrode 6
PR is performed using a pattern including the pattern of the wiring 7 connecting the two, the pattern of the signal line terminal 23, and the pattern of the scanning line terminal 21. With this pattern, the chromium film is etched and the resist is removed.

As described above, the TFT array of this embodiment is completed. As described above, the number of PRs performed in the process of manufacturing the TFT array of the active matrix liquid crystal display panel according to the present embodiment is only four. In addition, all processes performed in this step are extremely stable, and can be manufactured with very high yield. Therefore, according to the present embodiment, a high-throughput, low-cost active matrix liquid crystal display panel can be stably manufactured.

In this embodiment, since the etching of the n-type amorphous silicon layer between the source and drain electrodes required in the first embodiment is not required,
There is no need to dig an amorphous silicon film,
The thickness of the amorphous silicon film can be set thin.

Further, since the back channel interface of the TFT is not exposed to the etching, a good interface can be formed, and more stable characteristics can be obtained.

Although detailed description is omitted here, it is noted that the TFT having the structure shown in the third embodiment of the present invention can be used in combination with the pixel structure shown in the second embodiment. Needless to say.

[0124]

As described in detail above, according to the present invention,
An inverted staggered TFT array having excellent characteristics can be manufactured by using only a stable process in four times or less PR times, which has the effect of reducing the cost of the liquid crystal panel.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2A is a view showing a cross section taken along line AA ′ of FIG. 1; (B) is a figure which shows the cross section of the BB 'line of FIG.

FIG. 3 is a plan view showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4A is a view showing a cross section taken along line CC ′ of FIG. 3; (B) is a figure which shows the cross section of the DD 'line of FIG.

FIG. 5 is a plan view showing a configuration of a third exemplary embodiment of the present invention.

FIG. 6A is a view showing a cross section taken along line EE ′ of FIG. 5; FIG. 6B is a diagram showing a cross section taken along line FF ′ of FIG. 5.

FIG. 7 is a plan view for explaining a configuration of a peripheral terminal connection portion in the embodiment of the present invention.

FIG. 8 is a diagram showing a cross section of a conventional TFT.

[Explanation of symbols]

Reference Signs List 1 scanning line 2 signal line 3 drain electrode 4 source electrode 5 contact hole 6 pixel electrode 7 wiring connecting source electrode and pixel electrode 8 region where protective insulating film on pixel electrode is removed 9 glass substrate 10 gate insulating film 11 amorphous Silicon film 12 Protective insulating film 13 N-type amorphous silicon layer 14 Pattern overlapping signal line 15 Storage capacitor electrode 16 Lowermost metal layer 17 N-type amorphous silicon layer formed by ion doping 18 Before side etch Contact hole 19 Contact hole after side etching 20 Area to insulate gate side wall 21 Scan line terminal 22 Contact hole for taking out scanning line terminal 23 Signal line terminal 24 TFT light shielding layer

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/786

Claims (11)

(57) [Claims] A plurality of parallel scanning lines and a plurality of parallel signal lines which are arranged in a grid pattern and intersect with each other; provided near each intersection of the scanning lines and the signal lines; A gate electrode formed on the same layer as the above and connected to the scanning line; a thin film semiconductor layer provided on the gate electrode via a gate insulating film; and a signal line provided on the thin film semiconductor layer and electrically connected to the signal line. And a second electrode connected to the pixel electrode (however, when the first electrode is a source (drain) electrode, the second electrode is a drain (source) electrode). In a liquid crystal display panel obtained by laminating a first transparent insulating substrate on which is formed and a second transparent insulating substrate having a transparent electrode via a liquid crystal layer, Scan line and front The gate insulating film and the thin-film semiconductor layer are patterned with the same pattern as that of the gate electrode, and the first and second electrodes are formed in the same layer as the pixel electrode in a predetermined region on the thin-film semiconductor layer. A protection insulating film is provided so as to cover the first and second electrodes and the thin film semiconductor layer, and the signal line is provided on the protection insulating film; and the signal line and the first An electrode is connected to the electrode via a contact hole formed in a predetermined region on the first electrode, and the second layer is formed by a metal layer formed in the same layer as the signal line.
A liquid crystal display panel, wherein the electrode and the pixel electrode are electrically connected via a contact hole . 2. A semiconductor device comprising: a plurality of parallel scanning lines and a plurality of parallel signal lines arranged in a grid and crossing each other; provided near each intersection of the scanning lines and the signal lines; A gate electrode formed on the same layer as the above and connected to the scanning line; a thin film semiconductor layer provided on the gate electrode via a gate insulating film; and a signal line provided on the thin film semiconductor layer and electrically connected to the signal line. A first electrode connected to the first electrode and a second electrode connected to the pixel electrode (however, when the first electrode is a source (drain) electrode,
A first transparent insulating substrate on which a thin film transistor including a drain (source) electrode is formed, and a second transparent insulating substrate having a transparent electrode are bonded together via a liquid crystal layer. In the liquid crystal display panel, the gate insulating film and the thin-film semiconductor layer are patterned with the same pattern as the pattern including the scanning line and the gate electrode except for a peripheral terminal connection portion; Two electrodes are formed in the same layer as the pixel electrode in a predetermined region on the thin film semiconductor layer, and a protective insulating film is provided so as to cover the first and second electrodes and the thin film semiconductor layer. A signal line is provided on the insulating film; the signal line and the first electrode are connected via a contact hole on the first electrode; formed in the same layer as the signal line Wherein the metal layer and the second
And the pixel electrode are connected via a contact hole, and the contact hole formed on the first and second electrodes
The boundaries of the channel side, the more the boundary of tea <br/> channel side of the first and second electrodes are formed in the channel inside, ions into the thin film semiconductor layer under the opening end region of the contact hole A liquid crystal display panel having a region doped with impurities by implantation. 3. A pattern formed on the same layer as the scanning line, separated from the scanning line, and electrically connected to the pixel electrode, on both sides of the pixel electrode so as to overlap the signal line. The liquid crystal display panel according to claim 1, wherein the liquid crystal display panel is arranged. 4. A pattern formed on the same layer as the signal line, separated from the signal line, and electrically connected to the pixel electrode, is disposed on both sides of the pixel electrode so as to overlap the scanning line. 3. The liquid crystal display panel according to claim 1, wherein 5. The liquid crystal display panel according to claim 1, wherein a pattern formed in the same layer as the signal line is disposed so as to cover a channel region of the thin film transistor. 6. A pattern formed on the same layer as the signal line, separated from the signal line, and electrically connected to the pixel electrode, the pattern being one of two scanning lines adjacent to the pixel electrode. A thin film transistor that supplies electric charges to the non-controlling scanning line, and an isolated pattern is formed in the same layer as the pixel electrode in a part of the overlapping region. 3. The liquid crystal display panel according to claim 1, wherein a capacitor is formed between the gate insulating film layers, and the isolated pattern is electrically connected to the pixel electrode. 7. A thin film transistor (TF) having an inverted stagger structure.
T) In a method of manufacturing a liquid crystal display device (LCD) including an array, (a) forming a metal film, a gate insulating film, and a semiconductor film serving as scanning lines on a transparent insulating substrate in this order, and then forming them with the same pattern; Patterning, (b) forming a pixel electrode, first and second electrodes in the same layer, and patterning them by one photolithography; (c) forming the pixel electrode, the first and second electrodes (D) forming a protective insulating film so as to cover the first electrode and a signal line;
It is connected to the contact hole you arranged with respect to the protective insulating film on the first electrode, and said pixel electrode and said second electrode
For protecting the protective insulating film on the second electrode.
A contact hole to be provided, the pixel electrode and the second
The protective insulation on the pixel electrode to connect with the electrode
Contact holes provided for the film and the surrounding area
Formed on the same layer as the signal lines to supply signals to the scanning lines
Scan line to connect the scan line terminal to the scan line
Said protective insulating film, forming a predetermined contact hole which is arranged to open said semiconductor film and said gate insulating film, with one photolithography above, to form a (e) a metal layer, said first A signal line connected to one electrode, and a metal connecting the second electrode and the pixel electrode
A method for manufacturing a liquid crystal display device, comprising: forming each of the layers by one photolithography . 8. the first electrode is the signal line via a contact hole formed by opening the protective insulating film, the gold
A peripheral layer electrically connected to the second electrode and formed on the protective insulating film through a contact hole formed in the protective insulating film, the semiconductor film, and the gate insulating film; 8. A scanning line terminal is electrically connected to the gate electrode (scanning line).
The manufacturing method of the liquid crystal display device according to the above. 9. Following the step (b), the first and second
Said electrode as a mask semiconductor layer a predetermined depth engraved,
8. The method according to claim 7, wherein an n-type semiconductor layer serving as a contact portion is left only under the first and second electrodes. 10. An n-type semiconductor layer serving as a contact portion is formed under the first and second electrodes using the protective insulating film as a mask for ion implantation, following the step (d). 8. The method for manufacturing a liquid crystal display device according to item 7. 11. A channel-side boundary of a contact hole formed on said first and second electrodes, said first and second electrodes being formed on said first and second electrodes.
Between the channel-side boundary of the second electrode and the channel
It is formed in a method of manufacturing a liquid crystal display device according to claim 10, wherein the introduction by ion implanting n-type impurities under the open end region of the contact hole.