CN101562152B - manufacturing method of active element array substrate - Google Patents
manufacturing method of active element array substrate Download PDFInfo
- Publication number
- CN101562152B CN101562152B CN2009101076045A CN200910107604A CN101562152B CN 101562152 B CN101562152 B CN 101562152B CN 2009101076045 A CN2009101076045 A CN 2009101076045A CN 200910107604 A CN200910107604 A CN 200910107604A CN 101562152 B CN101562152 B CN 101562152B
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- electrode
- connection pads
- conductive connection
- photoresist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention is applicable to the technical field of display panel, and provides a manufacturing method of an active element array substrate, comprising the following steps of: firstly, forming a gate, a capacitor electrode, a first insulating layer, a channel layer, a source electrode and a drain electrode; secondly, forming a second insulating layer on the substrate on all sides, and forming a patterning photo-resistant layer on the substrate; thirdly, removing the second insulating layer above the drain electrode and the capacitor electrode to form a contact window and an opening by taking the patterning photo-resistant layer as a mask, wherein the contact window is exposed out of the drain electrode, while the opening is exposed out of the first insulating layer positioned above the capacitor electrode; and fourthly, forming a pixel electrode on the substrate, wherein the pixel electrode passes through the contact window so as to be electrically connected with the drain electrode and filled in the opening. A storage capacitor is formed by the pixel electrode, the capacitor electrode, and the first insulating layer positioned between the pixel electrode and the capacitor electrode. In the invention, the manufacturing method of the active element array substrate has good process yield, and can avoid the occurrence of over-etching or insufficient etching.
Description
Technical field
The invention belongs to technical field of display panel, relate in particular to a kind of manufacture method element of active component array base board.
Background technology
Display panels mainly is made of active component array base board, colored optical filtering substrates and liquid crystal layer, and wherein active component array base board for example is made up of the dot structure of a plurality of arrayed.In order to control other dot structure, usually can be via scan wiring (scan line) and data wiring (data line) choosing specific dot structure, and suitable operating voltage is provided, to show the video data of corresponding this dot structure.
Particularly, to promote display quality, in each dot structure, the subregion of pixel electrode can be covered on scan line or the capacitance electrode usually, to form storage capacitors in order to keep the operating voltage of dot structure.
Figure 1A is the top view of the dot structure of existing active component array base board.Figure 1B is the generalized section along the I-I ' line of Figure 1A.Please be simultaneously with reference to Figure 1A and Figure 1B, in the dot structure 10 of this active component array base board, storage capacitors 70 mainly is to be coupled to form by the pixel electrode 40 of capacitance electrode 30 with its top.Between capacitance electrode 30 and pixel electrode 40, dispose lock insulating barrier 32 and protective layer 60, and form the storage capacitors 70 of metal layer/insulator layer/indium tin oxide layer (MII) framework.
Storage capacitors 70 is mainly in order to stablize the data voltage of dot structure 10, to promote the display quality of LCD.When the storage capacitors value is big more, the effect of the data voltage of its stable dot structure 10 is good more.There is the researcher to propose a kind of method that increases the storage capacitors value of dot structure 10, that is increases the overlapping area of capacitance electrode 30 and pixel electrode 40.Yet this kind method causes the aperture opening ratio (aperture ratio) of dot structure 10 to reduce easily, makes the shown image of LCD be easy to generate the problem of luminance shortage.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of active component array base board, be intended to solve prior art can not improve the storage capacitors value under the prerequisite that does not influence aperture ratio of pixels problem.
The present invention proposes a kind of manufacture method of active component array base board.At first, on substrate, form grid and capacitance electrode.Then, on substrate, form first insulating barrier cover gate and the capacitance electrode.Then, on first insulating barrier above the grid, form channel layer.Thereupon, on channel layer, form source electrode and drain electrode, and source electrode lays respectively at the both sides of grid with draining.Moreover, on substrate, form second insulating barrier all sidedly.Continue it, on substrate, form the patterning photoresist layer.Afterwards, at a processing procedure in the time, with the patterning photoresist layer serve as cover curtain remove be positioned at drain electrode top and capacitance electrode top second insulating barrier to form contact hole and opening, wherein contact hole exposes drain electrode, and opening exposes first insulating barrier that is positioned at the capacitance electrode top.Then, on substrate, form pixel electrode, and pixel electrode sees through contact hole and electrically connects drain electrode and insert in the opening.Pixel electrode, capacitance electrode and first insulating barrier between pixel electrode and capacitance electrode constitute storage capacitors.
In one embodiment of this invention, above-mentioned part second insulating barrier that removes comprises with the method that forms contact hole and opening: carry out a dry ecthing procedure.
In one embodiment of this invention, chien shih is positioned at the capacitance electrode top and is patterned second insulating barrier that photoresist layer comes out and removes fully just when controlling above-mentioned processing procedure.
In one embodiment of this invention, the method for above-mentioned formation patterning photoresist layer comprises: form a photoresist layer earlier on second insulating barrier.Then, with the light shield be cover curtain patterning photoresist layer to form the patterning photoresist layer, wherein, light shield has a plurality of mask pattern, and mask pattern wherein one be arranged on the drain electrode top, and wherein another of mask pattern is arranged on the capacitance electrode top.
In one embodiment of this invention, the manufacture method of said active element array substrate also comprises: forming ohmic contact layer between source electrode and the channel layer and between drain electrode and the channel layer.
The present invention proposes a kind of manufacture method of active component array base board in addition.At first, on substrate, form grid, capacitance electrode and first conductive connection pads.Then, on substrate, form first insulating barrier, and the first insulating barrier cover gate, capacitance electrode and first conductive connection pads.Then, on first insulating barrier above the grid, form channel layer.Then, form source electrode and drain electrode on channel layer, and form second conductive connection pads simultaneously on first insulating barrier, wherein, source electrode and drain electrode lay respectively at the both sides of grid, and contiguous first conductive connection pads of second conductive connection pads.Afterwards, on substrate, form second insulating barrier all sidedly.Continue it, on second insulating barrier, form the patterning photoresist layer.Then, serve as that cover curtain carries out first etch process with the patterning photoresist layer, remove the position at second insulating barrier above second conductive connection pads and above first conductive connection pads, to expose second conductive connection pads and to be positioned at first insulating barrier of first conductive connection pads top.Thereupon, with the patterning photoresist layer serves as that the cover curtain carries out second etch process, first insulating barrier that removes first conductive connection pads top is to expose first conductive connection pads, second insulating barrier that removes drain electrode top and capacitance electrode top simultaneously is to form contact hole and opening, wherein contact hole exposes drain electrode, and opening exposes first insulating barrier that is positioned at the capacitance electrode top.Afterwards, on second insulating barrier, form patterned electrode layer, and patterned electrode layer comprises pixel electrode and connection electrode.Pixel electrode sees through contact hole electric connection drain electrode and inserts in the opening, and connection electrode electrically connects first conductive connection pads and second conductive connection pads.Pixel electrode, capacitance electrode and position first insulating barrier between pixel electrode and capacitance electrode constitute storage capacitors.
In one embodiment of this invention, with the etch stop layer of second conductive connection pads as first etch process.
In one embodiment of this invention, with the etch stop layer of first conductive connection pads as second etch process.
In one embodiment of this invention, the method for above-mentioned formation patterning photoresist layer comprises: form the photoresist layer on second insulating barrier.Then, be that cover curtain patterning photoresist layer is to form the patterning photoresist layer with the gray-level mask.This patterning photoresist layer can have a plurality of thinning patterns and a plurality of mouth that penetrates, and the thinning pattern lays respectively at above the drain electrode and the capacitance electrode top, penetrates second insulating barrier that mouth exposes first conductive connection pads and second conductive connection pads top respectively.
For example, above-mentioned formation thinning pattern and the method that penetrates mouthful comprise: this photoresist layer of patterning is to form a plurality of first pre-thinning pattern and a plurality of second pre-thinning pattern, and wherein the thickness of the first pre-thinning pattern is greater than the thickness of the second pre-thinning pattern.Then, carrying out the ashing processing procedure removes the second pre-thinning pattern fully and penetrates mouthful and make simultaneously the thickness attenuate of the first pre-thinning pattern with formation thinning pattern with formation.
In addition, the first above-mentioned etch process comprises: with the patterning photoresist layer is that the cover curtain removes and penetrates second insulating barrier that come out of mouth, to expose second conductive connection pads and to be positioned at first insulating barrier of first conductive connection pads top.
Further, after carrying out first etch process and carry out before second etch process, also comprise and carry out an ashing processing procedure to remove the thinning pattern to expose second insulating barrier of drain electrode top and capacitance electrode top.
In one embodiment of this invention, the method for the above-mentioned described patterning photoresist layer of formation comprises: form a photoresist layer on second insulating barrier.Then, with a gray-level mask is this photoresist layer of cover curtain patterning, this patterning photoresist layer has a plurality of first thinning patterns, a plurality of second thinning pattern and a plurality of mouth that penetrates, wherein the first thinning pattern lays respectively at drain electrode top and capacitance electrode top, and the position of the second thinning pattern between grid and the capacitance electrode, and first conductive connection pads and second conductive connection pads between, and the thickness of the first thinning pattern is less than the thickness of the second thinning pattern.Penetrating mouth exposes above first conductive connection pads respectively and second insulating barrier above second conductive connection pads.
At this, the method that forms the first thinning pattern, the second thinning pattern and penetrate mouthful comprises: this photoresist layer of patterning is to form a plurality of first pre-thinning pattern, a plurality of second pre-thinning pattern and a plurality of the 3rd pre-thinning pattern, wherein, the thickness of the first pre-thinning pattern is greater than the thickness of the 3rd pre-thinning pattern, and the thickness of the second pre-thinning pattern is greater than the thickness of the first pre-thinning pattern.Then, carry out an ashing processing procedure and remove the 3rd pre-thinning pattern fully and penetrate mouth, and the thickness attenuate that makes the first pre-thinning pattern and the second pre-thinning pattern simultaneously is to form the first thinning pattern and the second thinning pattern respectively with formation.
In one embodiment of this invention, the first above-mentioned etch process comprises: with the patterning photoresist layer is that the cover curtain removes and penetrates second insulating barrier that come out of mouth, to expose second conductive connection pads and to be positioned at first insulating barrier of first conductive connection pads top.
In one embodiment of this invention, after carrying out first etch process, and carry out also comprising before second etch process: carry out an ashing processing procedure, the first thinning pattern is removed fully exposing second insulating barrier of drain electrode top and capacitance electrode top, and make the thickness attenuate of the second thinning pattern simultaneously.
In addition, after carrying out second etch process and before the formation patterned electrode layer, can also comprise and carry out an ashing processing procedure, the second thinning pattern is removed fully to expose at second insulating barrier that reaches between grid and the capacitance electrode between first conductive connection pads and second conductive connection pads.In one embodiment, the method for formation patterned electrode layer comprises: form an electrode material layer all sidedly on the patterning photoresist layer and second insulating barrier.And, removing the patterning photoresist layer simultaneously, remove the electrode material layer that covers on the patterning photoresist layer in the lump, on second insulating barrier, to form pixel electrode and connection electrode.
In one embodiment of this invention, above-mentioned first etch process or second etch process comprise a dry-etching processing procedure.
In one embodiment of this invention, above-mentioned formation patterned electrode layer also comprises before: remove the patterning photoresist layer fully.
In one embodiment of this invention, the manufacture method of said active element array substrate also comprises: forming an ohmic contact layer between source electrode and the channel layer and between drain electrode and the channel layer.
Based on above-mentioned,, utilize second insulating barrier that removes the capacitance electrode top when forming contact hole in the lump in the manufacture method of active component array base board proposed by the invention.Thus, only there is first insulating barrier to be clipped between capacitance electrode and the pixel electrode and constitutes the bigger storage capacitors of capacitance.In addition, the present invention etching second insulating barrier more suitably control the processing procedure time when forming contact hole or with the first/the second conductive connection pads as etch stop layer to control the degree of depth that second insulating barrier is removed well.Therefore, the manufacture method of active component array base board of the present invention has good process yield, can avoid the over etching or the phenomenon of undercut to take place.
Description of drawings
Figure 1A is the top view of the dot structure of existing active component array base board;
Figure 1B is the generalized section along the I-I ' line of Figure 1A;
Fig. 2 is the partial cutaway schematic of a kind of active component array base board of preferred embodiment of the present invention;
Fig. 3 A to Fig. 3 D is the schematic diagram of manufacture method of the active component array base board of first embodiment of the invention;
Fig. 4 A to Fig. 4 F is the schematic diagram of manufacture method of the active component array base board of second embodiment of the invention;
Fig. 5 A to Fig. 5 H is the schematic diagram of manufacture method of the active component array base board of third embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in the qualification invention.
In embodiments of the present invention, utilize second insulating barrier that removes the capacitance electrode top when forming contact hole in the lump.Thus, only there is first insulating barrier to be sandwiched between capacitance electrode and the pixel electrode and constitutes the bigger storage capacitors of capacitance.In addition, the present invention etching second insulating barrier more suitably control the processing procedure time when forming contact hole or with the first/the second conductive connection pads as etch stop layer to control the degree of depth that second insulating barrier is removed well.Therefore, the manufacture method of active component array base board of the present invention has good process yield, can avoid the over etching or the phenomenon of undercut to take place.
Fig. 2 is the partial cutaway schematic of a kind of active component array base board of preferred embodiment of the present invention.Please refer to Fig. 2, this active component array base board 20 comprises substrate 200, grid 210, capacitance electrode 220, first insulating barrier 230, channel layer 240, source electrode 250, drain electrode 260, second insulating barrier 270 and pixel electrode 280.
Please continue with reference to Fig. 2, grid 210 is configured on the substrate 200 with capacitance electrode 220.First insulating barrier, 230 cover gate 210 and capacitance electrode 220.Channel layer 240 is configured on first insulating barrier 230, and channel layer 240 is positioned at grid 210 tops.Source electrode 250 all is configured on the channel layer 240 with drain electrode 260, and the position of source electrode 250 and drain electrode 260 lays respectively at the both sides of grid 210.Particularly, source electrode 250 does not link to each other mutually with drain electrode 260, and grid 210, channel layer 240, source electrode 250 and drain electrode 260 common formation one transistor T FT.
In addition, second insulating barrier 270 covers on the substrate 200, and second insulating barrier 270 has a contact hole 272 and an opening 274.Pixel electrode 280 is configured on second insulating barrier 270 and sees through contact hole 272 and electrically connects drain electrode 260.Simultaneously, pixel electrode 280 is inserted in the opening 274.What deserves to be mentioned is that opening 274 exposes first insulating barrier 230 that is positioned at capacitance electrode 220 tops, so that pixel electrode 280, capacitance electrode 220 and first insulating barrier 230 between pixel electrode 280 and capacitance electrode 220 constitute storage capacitors 290.
In the structure of the storage capacitors 290 of present embodiment, a layer insulating is only arranged, just only have first insulating barrier 230 to be configured between capacitance electrode 220 and 280 liang of conductive layers of pixel electrode.According to following formula (1),
Electric capacity (C) ∝ conductive layer area (A)/thickness of insulating layer (T) ... (1)
As can be known, under the situation that does not change the conductive layer area, the thickness of insulating layer attenuate can be promoted storage capacitors.More specifically, under the condition of conductive layer (capacitance electrode 220, pixel electrode 280) with the equal area layout, the storage capacitors 290 of present embodiment only has first insulating barrier 230 (thickness of insulating layer is thinner), therefore compare existing storage capacitors Cs1 (shown in Figure 1B), the storage capacitors 290 of present embodiment has bigger storage capacitors value.Under the prerequisite of the aperture opening ratio that does not influence active component array base board 20, can effectively improve the storage capacitors value of storage capacitors 290.
In fact, in order to make the storage capacitors 290 with high storage capacitors value, the present invention proposes the manufacture method of several active component array base boards in the following example.Following manufacture method is the usefulness for illustrating only, is not in order to limit the present invention.
Fig. 3 A to Fig. 3 D is the schematic diagram of manufacture method of the active component array base board of first embodiment of the invention.Please, at first, on substrate 200, form grid 210 and capacitance electrode 220 earlier with reference to Fig. 3 A.This grid 210 for example forms from same conductor layer patterning with capacitance electrode 220.Then, on substrate 200, form one first insulating barrier 230, its cover gate 210 and capacitance electrode 220.Then, on first insulating barrier 230 above the grid 210, form a channel layer 240.Channel layer 240 for example is the semiconductor layer of a patterning.Thereupon, on channel layer 240, form an one source pole 250 and a drain electrode 260, and the source electrode 250 and 260 both sides that lay respectively at grid 210 that drain.
The transistor T FT structure that present embodiment is illustrated in Fig. 3 A only is the usefulness that illustrates, and can adjust the production method of transistor T FT in other embodiments and makes transistor T FT present other structure.For example, channel layer 240, source electrode 250 can be patterned in same fabrication steps with drain electrode 260, so that between the source electrode 250 and first insulating barrier 230 and drain and all dispose semiconductor layer between 260 and first insulating barrier 230.In other words, the present invention does not limit the structure of transistor T FT.In addition, present embodiment does not limit the production method of transistor T FT, all under the technical field method that is applied to make transistor T FT can use in the present embodiment.
Then, please refer to Fig. 3 B, on substrate 200, form one second insulating barrier 270 all sidedly.Come again, on substrate 200, form a patterning photoresist layer 300.At this, patterning photoresist layer 300 for example is to expose part second insulating barrier 270 of drain electrode 260 tops and part second insulating barrier 270 of capacitance electrode 220 tops.
In detail, the method for formation patterning photoresist layer 300 for example is to form a photoresist layer (not illustrating) earlier on second insulating barrier 270.Then, serve as that cover curtain patterning photoresist layer (not illustrating) is to form patterning photoresist layer 300 with a light shield.Particularly, employed light shield (not illustrating) for example has a plurality of mask pattern (not illustrating) in this step.When this photoresist layer (not illustrating) of patterning, one of them is arranged on drain electrode 260 tops mask pattern, and wherein another of mask pattern is arranged on capacitance electrode 220 tops.
Thus, the patterning photoresist layer 300 that forms after photoresist layer (not illustrating) development just can expose part second insulating barrier 270 of drain electrode 260 tops and part second insulating barrier 270 of capacitance electrode 220 tops.What deserves to be mentioned is that the design of mask pattern can be different with the material selection of photoresist layer.That is when selecting eurymeric photoresist or minus photoresist as the photoresist layer for use, the different mask pattern of need arranging in pairs or groups respectively is to form patterning photoresist layer 280.
Afterwards, please continue with reference to Fig. 3 B and simultaneously with reference to Fig. 3 C, at a processing procedure in the time, with patterning photoresist layer 300 serve as the cover curtain remove be positioned at drain 260 tops and capacitance electrode 220 tops second insulating barrier 270 to form a contact hole 272 and an opening 274.Contact hole 272 exposes drain electrode 260, and opening 274 then exposes first insulating barrier 230 that is positioned at capacitance electrode 220 tops.At this, the method that removes second insulating barrier 270 partly for example is dry ecthing procedure.
Generally speaking, capacitance electrode 220 must be by the covering of at least one layer insulating to provide suitable capacity effect.Therefore, the process that is removed of second insulating barrier 270 of part must be controlled at suitable processing procedure in the time, to avoid the situation of over etching and first insulating barrier 230 also is removed.In other words, when present embodiment removes partly second insulating barrier 270, can be by the control processing procedure time, remove fully just so that be positioned at capacitance electrode 220 tops and be patterned second insulating barrier 270 that photoresist layer 300 comes out.Particularly, the collocation dry ecthing procedure can make the accuracy of second insulating barrier 270 that removes capacitance electrode 220 tops higher.In this step, but the integral thickness of the insulating barrier of attenuate storage capacitors 290 (first insulating barrier 230 is only arranged).
Then, please refer to Fig. 3 D, on substrate 200, form a pixel electrode 280, and pixel electrode 280 sees through contact hole 272 and electrically connects drain electrode 260 and insert in the opening 274.At this moment, active component array base board 20 is roughly finished, and wherein, pixel electrode 280, capacitance electrode 220 and first insulating barrier 230 between pixel electrode 280 and capacitance electrode 220 constitute a storage capacitors 290.
In the present embodiment, owing to when making contact hole 272, also removed second insulating barrier 270 above the capacitance electrode 220, make and only dispose one deck first insulating barrier 230 between pixel electrode 280 and the capacitance electrode 220.Therefore, also can promote whole demonstration aperture opening ratio except the capacitance that can increase storage capacitors 290 effectively.
Particularly, the manufacture method of present embodiment is made contact hole 272 and is removed 270 of second insulating barrier in the light shield processing procedure, can not increase light shield quantity, can reduce cost of manufacture.Hold above-mentionedly, the LCD of using active component array base board 20 can have superior display quality, and can not be subjected to negative influence showing on the aperture opening ratio.
Fig. 4 A to Fig. 4 F is the schematic diagram of manufacture method of the active component array base board of second embodiment of the invention.Please, at first provide substrate 400, wherein dispose transistor T FT and the capacitance electrode 220 that is illustrated as Fig. 3 A on the substrate 400 earlier with reference to Fig. 4 A.Detailed structure is no longer repeated.
It should be noted that and on substrate 400, also be formed with one first adjacent conductive connection pads 410 of position and one second conductive connection pads 420.First conductive connection pads 410 for example is that the grid 310 with transistor T FT forms in the lump, and second conductive connection pads 420 for example is and the source electrode of transistor T FT 250 forms in the lump with drain electrode 260.In fact, first conductive connection pads 410 is configured between the substrate 400 and first insulating barrier 230 and second conductive connection pads 420 is configured between first insulating barrier 230 and second insulating barrier 270.
In addition, second insulating barrier 270 covers on the substrate 400 all sidedly.Be formed with a patterning photoresist layer 430 on second insulating barrier 270.The method that forms patterning photoresist layer 430 is included in and forms a photoresist layer (not illustrating) on second insulating barrier 270 and serve as that cover curtain patterning photoresist layer (not illustrating) is with formation patterning photoresist layer 430 with a gray-level mask (not illustrating).
Present embodiment for example is earlier shown in Fig. 4 A, with the gray-level mask be the cover curtain with photoresist layer (not illustrating) patterning to form a plurality of first pre-thinning pattern 432 and a plurality of second pre-thinning pattern 434.At this, the thickness of the first pre-thinning pattern 432 for example is the thickness greater than the second pre-thinning pattern 434.In addition, the first pre-thinning pattern 432 lays respectively at drain electrode 260 tops and capacitance electrode 220 tops, and the second pre-thinning pattern 434 lays respectively at first conductive connection pads 410 and second conductive connection pads, 420 tops
Thereupon, carrying out an ashing processing procedure removes the second pre-thinning pattern 434 fully and penetrates mouthful 434A and make the thickness attenuate of the first pre-thinning pattern 432 to form a plurality of thinning pattern 432A simultaneously to form a plurality of shown in Fig. 4 B.
In other words, patterning photoresist layer 270 has a plurality of thinning pattern 432A and a plurality of mouthful 434A that penetrates.Thinning pattern 432A lays respectively at drain electrode 260 tops and capacitance electrode 220 tops, and penetrates second insulating barrier 270 that mouthful 434A exposes first conductive connection pads, 410 tops and second conductive connection pads, 420 tops respectively.
Then, please refer to Fig. 4 C, serves as that the cover curtain carries out one first etch process with patterning photoresist layer 430, removes second insulating barrier 270 that is positioned at second conductive connection pads, 420 tops and first conductive connection pads, 410 tops.Thus, first insulating barrier 230 of second conductive connection pads 420 and first conductive connection pads, 410 tops can be exposed.In other words, first etch process can remove penetrating mouthful second insulating barrier 270 that 434A came out.
Particularly, at this with the etch stop layer of second conductive connection pads 420 as first etch process.More specifically, in the present embodiment, second conductive connection pads, 420 tops only are covered with by second insulating barrier 270, do not cover and be patterned photoresist layer 430.Therefore, first etch process if with second conductive connection pads 420 as etch stop layer, then first etch process institute etched depth is the thickness of second insulating barrier 270 just.In other words, second insulating barrier 270 on first conductive connection pads 410 can be removed in first etch process just fully, and exposes first insulating barrier 230 of first conductive connection pads, 410 tops.
Then, please carry out an ashing processing procedure, to remove the thinning pattern 432A in the patterning photoresist layer 430 simultaneously with reference to Fig. 4 C and Fig. 4 D.After thinning pattern 432A was removed, second insulating barrier 270 that is positioned at drain electrode 260 tops and is positioned at capacitance electrode 220 tops can be exposed.
Then, please be simultaneously with reference to Fig. 4 D and Fig. 4 E, continuing with patterning photoresist layer 430 serves as that the cover curtain carries out one second etch process, first insulating barrier 230 that removes first conductive connection pads, 410 tops is to expose first conductive connection pads 410.Simultaneously, in second etch process, remove the drain electrode 260 above and capacitance electrode 220 above second insulating barrier 270 to form a contact hole 272 and an opening 274.Contact hole 272 for example can expose drain electrode 260, and opening 274 exposes first insulating barrier 230 that is positioned at capacitance electrode 220 tops.First etch process or second etch process of present embodiment for example adopt the dry-etching processing procedure.
What deserves to be mentioned is, second etch process be with first conductive connection pads 410 as etch stop layer, that is to say that the etch depth of second etch process can remove the thickness of first insulating barrier 230 just.At this moment, being patterned second insulating barrier 270 that photoresist layer 430 comes out also can be removed identical thickness and form contact hole 272 and opening 274.Second etch process has first conductive connection pads 410 as etch stop layer, so second etch process can also not remove first insulating barrier 230 above the capacitance electrode 220 when forming opening 274.Therefore, the etch stop layer design helps to improve the process rate of present embodiment.
Then, please refer to Fig. 4 F, on second insulating barrier 270, form a patterned electrode layer 440 to form active component array base board 40.Patterned electrode layer 440 comprises a pixel electrode 442 and a connection electrode 444.Pixel electrode 442 sees through contact hole 272 electric connection drain electrodes 260 and inserts in the opening 274, and connection electrode 444 electrically connects first conductive connection pads 410 and second conductive connection pads 420.At this, pixel electrode 442, capacitance electrode 220 and first insulating barrier 230 between pixel electrode 442 and capacitance electrode 220 constitute a storage capacitors 530.It should be noted that, first conductive connection pads 410 for example is to be arranged in the scan line of viewing area (not illustrating) or the splicing ear of data wire, and second conductive connection pads 420 for example be arranged in surrounding zone (not illustrating) in order to be connected to the outside terminal of source electrode driver or gate driver, utilize and to carry out the electric connection of skip floor formula, can increase the degree of freedom of circuit design as the design of Fig. 4 F.
In fact, before forming patterned electrode layer 440, also comprise the patterning photoresist layer 430 that removes fully shown in Fig. 4 E.The generation type of patterned electrode layer 440 then for example is to form an electrode material layer (not illustrating) earlier on substrate 400, again this electrode material layer of patterning (not illustrating).The mode of this electrode material layer of patterning (not illustrating) can be to carry out a micro image etching procedure.
Because only have first insulating barrier 230 to be configured in the middle of pixel electrode 442 and 220 liang of conductive layers of capacitance electrode in the structure of storage capacitors 530, storage capacitors 530 can have bigger storage capacitors value.Therefore, the LCD of application active component array base board 40 can have superior display quality.In addition, by second etch process second insulating barrier 270 of capacitance electrode 220 tops is moved the area that can effectively improve the capacitance of storage capacitors 530 and need not increase storage capacitors 530.So, the characteristic that the LCD of application active component array base board 40 can also be possessed high aperture.
What deserves to be mentioned is that capacitance electrode 220 can cause the product yield to reduce if be exposed.Second etch process of present embodiment can avoid the insulating barrier of capacitance electrode 220 tops by over etching with first conductive connection pads 410 as etch stop layer.Therefore, the manufacture method of the active component array base board 40 of present embodiment at least also has the advantage of high process rate except that above-mentioned advantage.
Fig. 5 A to Fig. 5 H is the schematic diagram of manufacture method of the active component array base board of third embodiment of the invention.Please, provide a substrate 400 that is illustrated as Fig. 4 A earlier with reference to Fig. 5 A.In the present embodiment, the patterning photoresist layer that illustrated except patterning photoresist layer 500 and Fig. 4 A 430 was different, other member that is disposed on the substrate 400 was all identical with the member that Fig. 4 A is illustrated, and does not repeat them here.Certainly, the member identical with Fig. 4 A can be adopted in a like fashion and be made in the present embodiment, but the invention is not restricted to this.
Particularly, the present embodiment method that forms patterning photoresist layer 500 is included in and forms a photoresist layer (not illustrating) on second insulating barrier 270 and serve as a cover act patterning photoresist layer (not illustrating) with a gray-level mask (not illustrating).Thus, for example be formed with a plurality of first pre-thinning pattern 502, a plurality of second pre-thinning pattern 504 and a plurality of the 3rd pre-thinning pattern 506 on the substrate 400.
Particularly, the first pre-thinning pattern 502 is positioned at drain electrode 260 and capacitance electrode 220 tops respectively; The second pre-thinning pattern 504 is respectively between grid 210 and the capacitance electrode 220 and between first conductive connection pads 410 and second conductive connection pads 420; And the 3rd 506 in pre-thinning pattern lays respectively at first conductive connection pads, 410 tops and second conductive connection pads, 420 tops.In addition, the thickness of the first pre-thinning pattern 502 is greater than the thickness of the 3rd pre-thinning pattern 506, and the thickness of the second pre-thinning pattern 504 is greater than the thickness of the first pre-thinning pattern 502.
In the present embodiment, utilize gray-level mask can provide the characteristic of different light transmittances to make patterning photoresist layer 500 have the pattern of stepped distribution in zones of different.Thus, can reach the etched effect of difference in follow-up etch process step uses number and then reduces cost of manufacture to save light shield.Similarly, in the 3rd embodiment, also can use gray-level mask to reach the etched effect of difference.
Then, please refer to Fig. 5 B, carry out an ashing processing procedure, remove the 3rd pre-thinning pattern 506 fully and penetrate a mouthful 506A, and the thickness attenuate that makes the first pre-thinning pattern 502 and the second pre-thinning pattern 504 simultaneously is to form the first thinning pattern 502A and the second thinning pattern 504A respectively with formation.The first thinning pattern 502A lays respectively at drain electrode 260 tops and capacitance electrode 220 tops, and the position of the second thinning pattern 504A is between grid 210 and the capacitance electrode 220 and between first conductive connection pads 410 and second conductive connection pads 420.In addition, the thickness of the first thinning pattern 502A penetrates second insulating barrier 270 that mouthful 506A then exposes first conductive connection pads 410 and second conductive connection pads, 420 tops respectively less than the thickness of the second thinning pattern 504A.
Then, please refer to Fig. 5 C, serves as that cover curtain carries out first etch process and penetrates mouthful second insulating barrier 270 that 506A was come out to remove with patterning photoresist layer 500.So, second conductive connection pads 420 and first insulating barrier 230 that is positioned at first conductive connection pads, 410 tops for example are exposed.This fabrication steps for example is as etch stop layer, so first insulating barrier 230 on first conductive connection pads 410 can not be removed because of the over etching of first etch process with second conductive connection pads 420.That is to say that the etch depth of first etch process is Be Controlled more correctly.
Next, please be simultaneously with reference to Fig. 5 C and Fig. 5 D, carry out an ashing processing procedure once more the first thinning pattern 502A is removed fully exposing second insulating barrier 270 of drain electrode 260 tops and capacitance electrode 220 tops, and make the thickness attenuate of the second thinning pattern 504A simultaneously.
Subsequently, please refer to Fig. 5 E, serves as that cover curtain carries out one second etch process and removes first insulating barrier 230 of first conductive connection pads, 410 tops to expose first conductive connection pads 410 with patterning photoresist layer 500.Simultaneously, in second etch process, remove the drain electrode 260 above and capacitance electrode 220 above second insulating barrier 270 to form a contact hole 272 and an opening 274.
For the insulating barrier attenuate that makes capacitance electrode 220 tops improving the capacity effect that it is provided, present embodiment has removed second insulating barrier 270 that is positioned at above the capacitance electrode 220 in second etch process.In addition, second etch process is as etch stop layer in the present embodiment with first conductive connection pads 410.So the etch depth of second etch process is a removable layer insulating just.Therefore, first insulating barrier 230 on the capacitance electrode 220 can not be removed because of the over etching of second etch process yet.In other words, the etch depth of second etch process is subjected to good control and helps to promote the process rate of present embodiment.
Then, please refer to Fig. 5 F, carry out an ashing processing procedure once more, the second thinning pattern 504A shown in Fig. 5 E is removed fully to expose at second insulating barrier 270 that reaches between grid 210 and the capacitance electrode 220 between first conductive connection pads 410 and second conductive connection pads 420.At this moment, still having part second insulating barrier 270 to be patterned photoresist layer 500 on the substrate 400 covers.
Then, please refer to Fig. 5 G, on the patterning photoresist layer 500 and second insulating barrier 270, form an electrode material layer 510 all sidedly.
Thereupon, please remove patterning photoresist layer 500 to form active component array base board 50 simultaneously with reference to Fig. 5 G and Fig. 5 H.Removing patterning photoresist layer 500 simultaneously, the electrode material layer 510 that covers on the patterning photoresist layer 500 also can remove in the lump to form patterned electrode layer 520.Thus, promptly be formed with pixel electrode 522 and connection electrode 524 on second insulating barrier 270.In other words, present embodiment is to form patterned electrode layer 520 to divest processing procedure (lift-off process).
What deserves to be mentioned is that present embodiment just can be with electrode material layer (not illustrating) patterning, so help to simplify fabrication steps when removing patterning photoresist layer 500.In addition, in the general processing procedure, the mode of patterned electrodes material layer (not illustrating) all must adopt micro image etching procedure, just must re-use one light shield and the processing procedure cost is increased.Present embodiment must not re-use light shield just can form patterned electrode layer 520, thereby more helps to save the processing procedure cost.
In addition, in the present embodiment, capacitance electrode 220, pixel electrode 442 and first insulating barrier 230 that is positioned between this two conductive layer constitute a storage capacitors 530.Only there is the design of a layer insulating can make the storage capacitors value height of the storage capacitors value of storage capacitors 530 between two conductive layers than existing design.Therefore, the present embodiment overlapping area that can increase capacitance electrode 220 and pixel electrode 442 just can effectively improve the storage capacitors value and promote the element characteristic of active component array base board 50.
In sum, in embodiments of the present invention, utilize the suitable design (etch stop layer) and the control of process conditions to decide the etch depth of etch process, and make the insulating barrier attenuate in the storage capacitors.Therefore, the storage capacitors in the active component array base board of the present invention has bigger capacitance and helps to promote the element characteristic of active component array base board.In addition, the manufacture method of active component array base board can have good process yield and lower cost of manufacture.Moreover active component array base board of the present invention also has bigger demonstration aperture opening ratio.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the manufacture method of an active component array base board is characterized in that, described method comprises the steps:
On a substrate, form a grid and a capacitance electrode;
On described substrate, form one first insulating barrier and cover described grid and described capacitance electrode;
On described first insulating barrier above the described grid, form a channel layer;
On described channel layer, form one source pole and drain, and described source electrode and described drain electrode lay respectively at the both sides of described grid with one;
On described substrate, form one second insulating barrier all sidedly;
On described substrate, form a patterning photoresist layer;
At a processing procedure in the time, with described patterning photoresist layer serve as cover curtain remove be positioned at described drain electrode top and described capacitance electrode top described second insulating barrier to form a contact hole and an opening, wherein said contact hole exposes described drain electrode, and described opening exposes described first insulating barrier that is positioned at described capacitance electrode top; And
Form a pixel electrode on described substrate, described pixel electrode electrically connects described drain electrode through described contact hole and inserts in the described opening,
Wherein, described pixel electrode, described capacitance electrode and described first insulating barrier between described pixel electrode and described capacitance electrode constitute a storage capacitors.
2. the manufacture method of active component array base board as claimed in claim 1, it is characterized in that, described at a processing procedure in the time, serve as that the cover curtain removes described second insulating barrier that is positioned at described drain electrode top and described capacitance electrode top and specifically comprises with the step that forms a contact hole and an opening with described patterning photoresist layer:
With described patterning photoresist layer is cover curtain, by carry out a dry ecthing procedure remove be positioned at described drain electrode top and described capacitance electrode top described second insulating barrier to form a contact hole and an opening;
Control the described processing procedure time, make to be positioned at above the described capacitance electrode and to remove fully just by described second insulating barrier that described patterning photoresist layer comes out;
The described step that forms a patterning photoresist layer on described substrate specifically comprises:
On described second insulating barrier, form a photoresist layer; And
With a light shield serves as that the described photoresist layer of cover curtain patterning is to form described patterning photoresist layer, wherein said light shield has a plurality of mask pattern, one of them is arranged on described drain electrode top described a plurality of mask pattern, and in described a plurality of mask pattern another is arranged on described capacitance electrode top;
The manufacture method of described active component array base board also comprises:
Forming an ohmic contact layer between described source electrode and the described channel layer and between described drain electrode and the described channel layer.
3. the manufacture method of an active component array base board is characterized in that, described method comprises the steps:
On a substrate, form a grid, a capacitance electrode and one first conductive connection pads;
On described substrate, form one first insulating barrier, and described first insulating barrier covers described grid, described capacitance electrode and described first conductive connection pads;
On described first insulating barrier above the described grid, form a channel layer;
On described channel layer, form an one source pole and a drain electrode, and the while forms one second conductive connection pads on described first insulating barrier, wherein said source electrode and described drain electrode lay respectively at the both sides of described grid, and contiguous described first conductive connection pads of described second conductive connection pads;
On described substrate, form one second insulating barrier all sidedly;
On described second insulating barrier, form a patterning photoresist layer;
With described patterning photoresist layer serves as that the cover curtain carries out one first etch process, remove described second insulating barrier that is positioned at described second conductive connection pads top and described first conductive connection pads top, to expose described second conductive connection pads and to be positioned at described first insulating barrier of described first conductive connection pads top;
With described patterning photoresist layer serves as that the cover curtain carries out one second etch process, described first insulating barrier that removes described first conductive connection pads top is to expose described first conductive connection pads, described second insulating barrier that removes described drain electrode top and described capacitance electrode top simultaneously is to form a contact hole and an opening, wherein said contact hole exposes described drain electrode, and described opening exposes described first insulating barrier that is positioned at described capacitance electrode top; And
On described second insulating barrier, form a patterned electrode layer, described patterned electrode layer comprises a pixel electrode and a connection electrode, described pixel electrode electrically connects described drain electrode through described contact hole and inserts in the described opening, and described connection electrode electrically connects described first conductive connection pads and described second conductive connection pads;
Wherein said pixel electrode, described capacitance electrode and described first insulating barrier between described pixel electrode and described capacitance electrode constitute a storage capacitors.
4. the manufacture method of active component array base board as claimed in claim 3 is characterized in that:
With the etch stop layer of described second conductive connection pads as described first etch process; With the etch stop layer of described first conductive connection pads as described second etch process;
Described first etch process or described second etch process comprise a dry-etching processing procedure;
Also comprised the steps: before the step that forms a patterned electrode layer on described second insulating barrier described
Remove described patterning photoresist layer fully;
The manufacture method of described active component array base board also comprises the steps:
Forming an ohmic contact layer between described source electrode and the described channel layer and between described drain electrode and the described channel layer.
5. the manufacture method of active component array base board as claimed in claim 3 is characterized in that, the described step that forms a patterning photoresist layer on described second insulating barrier specifically comprises:
On described second insulating barrier, form a photoresist layer; And
With a gray-level mask serves as that the described photoresist layer of cover curtain patterning is to form described patterning photoresist layer, and described patterning photoresist layer has a plurality of thinning patterns and a plurality of mouth that penetrates, described a plurality of thinning pattern lays respectively at described drain electrode top and described capacitance electrode top, and described a plurality of described second insulating barrier that mouth exposes described first conductive connection pads and described second conductive connection pads top respectively that penetrates.
6. the manufacture method of active component array base board as claimed in claim 5, it is characterized in that, with a gray-level mask serves as the described photoresist layer of cover curtain patterning forming described patterning photoresist layer, and described patterning photoresist layer has a plurality of thinning patterns and a plurality of step that penetrates mouthful specifically comprises:
With a gray-level mask serves as the described photoresist layer of cover curtain patterning forming a plurality of first pre-thinning pattern and a plurality of second pre-thinning pattern, and the thickness of the described a plurality of first pre-thinning pattern is greater than the thickness of the described a plurality of second pre-thinning pattern; And
Carry out an ashing processing procedure, remove the described a plurality of second pre-thinning pattern fully and also make the thickness attenuate of the described a plurality of first pre-thinning pattern simultaneously to form described a plurality of thinning pattern to form described a plurality of mouth that penetrates;
Described serves as that the cover curtain carries out one first etch process with described patterning photoresist layer, remove described second insulating barrier that is positioned at described second conductive connection pads top and described first conductive connection pads top, specifically comprise with the step that exposes described second conductive connection pads and be positioned at described first insulating barrier of described first conductive connection pads top:
With described patterning photoresist layer is cover curtain, removes described a plurality of described second insulating barrier that mouth is come out that penetrates, to expose described second conductive connection pads and to be positioned at described first insulating barrier of described first conductive connection pads top;
After carrying out described first etch process and carry out before described second etch process, also comprise and carry out an ashing processing procedure, to remove described a plurality of thinning pattern to expose described second insulating barrier of described drain electrode top and described capacitance electrode top.
7. the manufacture method of active component array base board as claimed in claim 3 is characterized in that, the step that forms a patterning photoresist layer on described second insulating barrier specifically comprises:
On described second insulating barrier, form a photoresist layer; And
With a gray-level mask serves as to cover the described photoresist layer of curtain patterning to form described patterning photoresist layer, and described patterning photoresist layer has a plurality of first thinning patterns, a plurality of second thinning pattern and a plurality of mouth that penetrates,
Wherein, described a plurality of first thinning pattern lays respectively at described drain electrode top and described capacitance electrode top, the position of described a plurality of second thinning patterns between described grid and the described capacitance electrode, and described first conductive connection pads and described second conductive connection pads between, the thickness of the described first thinning pattern is less than the thickness of the described second thinning pattern
Described a plurality of described second insulating barrier that mouth exposes described first conductive connection pads top and described second conductive connection pads top respectively that penetrates.
8. the manufacture method of active component array base board as claimed in claim 7, it is characterized in that, with a gray-level mask serves as to cover the described photoresist layer of curtain patterning to form described patterning photoresist layer, and described patterning photoresist layer has a plurality of first thinning patterns, a plurality of second thinning pattern and a plurality of step that penetrates mouth and specifically comprises:
The described photoresist layer of patterning is to form a plurality of first pre-thinning pattern, a plurality of second pre-thinning pattern and a plurality of the 3rd pre-thinning pattern, the thickness of the described first pre-thinning pattern is greater than the thickness of the described a plurality of the 3rd pre-thinning pattern, and the thickness of the described a plurality of second pre-thinning pattern is greater than the thickness of the described a plurality of first pre-thinning pattern;
Carry out an ashing processing procedure, remove the described the 3rd pre-thinning pattern fully forming described a plurality of mouth that penetrates, and the thickness attenuate that makes the described a plurality of first pre-thinning pattern and the described a plurality of second pre-thinning simultaneously is to form described a plurality of first thinning pattern and described a plurality of second thinning pattern respectively; Described first etch process comprises:
With described patterning photoresist layer is cover curtain, removes described a plurality of described second insulating barrier that mouth is come out that penetrates, to expose described second conductive connection pads and to be positioned at described first insulating barrier of described first conductive connection pads top;
Described serve as that cover curtain carries out one first etch process with described patterning photoresist layer, remove described second insulating barrier that is positioned at described second conductive connection pads top and described first conductive connection pads top, to expose described second conductive connection pads and to be positioned at after the step of described first insulating barrier of described first conductive connection pads top, and described serve as that cover curtain carries out one second etch process with described patterning photoresist layer, described first insulating barrier that removes described first conductive connection pads top is to expose described first conductive connection pads, described second insulating barrier that removes described drain electrode top and described capacitance electrode top simultaneously is to form a contact hole and an opening, wherein said contact hole exposes described drain electrode, and described opening exposes before the step of described first insulating barrier that is positioned at described capacitance electrode top, and described method also comprises the steps:
Carry out an ashing processing procedure, described a plurality of first thinning patterns are removed fully exposing described second insulating barrier of described drain electrode top and described capacitance electrode top, and make the thickness attenuate of described a plurality of second thinning patterns simultaneously.
9. the manufacture method of active component array base board as claimed in claim 7, it is characterized in that, described is serving as that the cover curtain carries out one second etch process with described patterning photoresist layer, described first insulating barrier that removes described first conductive connection pads top is to expose described first conductive connection pads, described second insulating barrier that removes described drain electrode top and described capacitance electrode top simultaneously is to form a contact hole and an opening, wherein said contact hole exposes described drain electrode, and described opening exposes after the step of described first insulating barrier that is positioned at described capacitance electrode top and in the described patterned electrode layer that forms on described second insulating barrier, described patterned electrode layer comprises a pixel electrode and a connection electrode, described pixel electrode electrically connects described drain electrode through described contact hole and inserts in the described opening, also comprises the steps: before the step of described connection electrode with described first conductive connection pads and the electric connection of described second conductive connection pads
Carry out an ashing processing procedure, described a plurality of second thinning patterns are removed fully to expose at described second insulating barrier that reaches between described grid and the described capacitance electrode between described first conductive connection pads and described second conductive connection pads.
10. the manufacture method of active component array base board as claimed in claim 9, it is characterized in that, on described second insulating barrier, form a patterned electrode layer, described patterned electrode layer comprises a pixel electrode and a connection electrode, described pixel electrode electrically connects described drain electrode through described contact hole and inserts in the described opening, and described connection electrode specifically comprises the step of described first conductive connection pads and the electric connection of described second conductive connection pads:
On described patterning photoresist layer and described second insulating barrier, form an electrode material layer all sidedly; And
Removing described patterning photoresist layer simultaneously, remove the described electrode material layer that covers on the described patterning photoresist layer in the lump, on described second insulating barrier, to form described pixel electrode and described connection electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101076045A CN101562152B (en) | 2009-05-21 | 2009-05-21 | manufacturing method of active element array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101076045A CN101562152B (en) | 2009-05-21 | 2009-05-21 | manufacturing method of active element array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101562152A CN101562152A (en) | 2009-10-21 |
| CN101562152B true CN101562152B (en) | 2011-11-30 |
Family
ID=41220881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101076045A Expired - Fee Related CN101562152B (en) | 2009-05-21 | 2009-05-21 | manufacturing method of active element array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101562152B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101902315B (en) | 2009-06-01 | 2013-04-17 | 华为技术有限公司 | Retransmission method, device and communication system based on forward error correction |
| CN104103583B (en) * | 2014-06-24 | 2017-02-15 | 京东方科技集团股份有限公司 | Array substrate and fabrication method thereof and display panel |
| TWI587043B (en) * | 2017-01-25 | 2017-06-11 | 友達光電股份有限公司 | Pixel structure and display panel thereof |
| CN107706116A (en) * | 2017-09-15 | 2018-02-16 | 惠科股份有限公司 | The manufacture method of active array switch |
-
2009
- 2009-05-21 CN CN2009101076045A patent/CN101562152B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101562152A (en) | 2009-10-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110649043B (en) | Array substrate, display panel, display device and preparation method of array substrate | |
| CN108376672B (en) | Array substrate, preparation method thereof and display device | |
| JP4336341B2 (en) | Thin film transistor liquid crystal display, multilayer storage capacitor structure and method for forming the same | |
| US10573595B2 (en) | Array substrate, fabricating method thereof, and display device | |
| US7998803B2 (en) | Pixel structure and method for manufacturing the same | |
| CN111880344B (en) | Display panel, preparation method thereof and display device | |
| CN110289270B (en) | Array substrate, manufacturing method thereof and display device | |
| JP2007193313A (en) | Organic light emitting display and method of fabricating the same | |
| CN112599580B (en) | Display panel and display device | |
| US7768015B2 (en) | Pixel structure of display panel and method of making the same | |
| US20220293708A1 (en) | Display substrate, method for manufacturing display substrate, and display device | |
| CN101562152B (en) | manufacturing method of active element array substrate | |
| CN103681514B (en) | Array base palte and preparation method thereof, display unit | |
| CN111276492B (en) | Display device, OLED panel thereof and manufacturing method of OLED panel | |
| US10126610B2 (en) | Array substrate, manufacturing method thereof and display device | |
| JP4512600B2 (en) | Method for manufacturing pixel structure | |
| US6940480B2 (en) | Pixel structure | |
| CN100498480C (en) | Thin film transistor array base plate and making method thereof | |
| CN111129029B (en) | Array substrate, display panel and manufacturing method of array substrate | |
| CN100521164C (en) | Pixel structure and its making method | |
| CN110176444B (en) | Array substrate, forming method thereof and display panel | |
| JP2005064338A (en) | Array substrate and flat surface display device | |
| CN108010918A (en) | The production method of tft array substrate and tft array substrate | |
| CN216288456U (en) | Display panel | |
| CN110544672B (en) | Display panel and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: CPT TECHNOLOGY (GROUP) CO., LTD. Free format text: FORMER OWNER: CPT DISPLAY TECHNOLOGY SHENZHEN LTD. Effective date: 20130704 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 518000 SHENZHEN, GUANGDONG PROVINCE TO: 350000 FUZHOU, FUJIAN PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20130704 Address after: 350000, No. 6 West Road, Mawei District, Fujian, Fuzhou Patentee after: CPT DISPLAY TECHNOLOGY (SHENZHEN)CO., LTD. Patentee after: Chunghwa Picture Tubes Ltd. Address before: 518000, Guangming hi tech Industrial Park, Shenzhen, Guangdong, No. 9, Ming Tong Road, Baoan District Patentee before: CPT Display Technology Shenzhen Ltd. Patentee before: Chunghwa Picture Tubes Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111130 Termination date: 20200521 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |