CN111681545B

CN111681545B - Display panel and display device

Info

Publication number: CN111681545B
Application number: CN202010461793.2A
Authority: CN
Inventors: 金慧俊; 姜炜; 张劼
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2020-05-27
Filing date: 2020-05-27
Publication date: 2022-03-29
Anticipated expiration: 2040-05-27
Also published as: CN111681545A

Abstract

The invention discloses a display panel and a display device, belonging to the technical field of display, wherein the display panel comprises a display area and a non-display area; a plurality of scanning lines and a plurality of signal lines; the bonding region includes a first region including a plurality of first conductive pads and a second region including a plurality of second conductive pads; the display panel also comprises a test circuit, wherein the test circuit comprises a plurality of electrically connected switch transistors and is connected with a switch control signal line and a reference voltage line; in the second direction, the switch control signal line and the reference voltage line are both positioned on one side of the switch transistor close to the display area; in the second direction, at least part of the switch transistor is positioned on one side of the first connecting line far away from the display area. The display device comprises the display panel. The invention can ensure that the test circuit has enough setting space as much as possible, improve the efficiency of bad detection of a production line, meet the test requirement and realize a narrower frame.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the development of display technology, display devices have become an essential part of consumers' daily lives. As display devices become popular, users have increasingly demanded not only the types of functions and performances of the display devices but also the appearances of the display devices, and conditions such as thinning and narrowing of the display devices have increasingly become factors for selecting display devices. The narrow bezel is to further expand an effective Area (AA) Area by further compressing the width of the bezel Area. The requirement for a narrow bezel presents even greater challenges to the design and manufacture of display devices.

Among the prior art, generally in display panel's processing procedure, accomplish before the box preparation, drive chip generally will test when not attached promptly, whether have the bad of foreign matter, luminance inequality (mura), bright spot and so on in the detection screen to ensure that display panel's overall arrangement is walked the line and is shown the function intact, test circuit sets up on the panel, is undoubtedly unfavorable for realizing narrow frame.

Therefore, it is an urgent need to solve the technical problem of the art to provide a display panel and a display device that can meet the test requirements in the panel process and realize a narrow frame.

Disclosure of Invention

In view of the above, the present invention provides a display panel and a display device, so as to solve the problem that the display panel in the prior art cannot meet the test requirements in the panel manufacturing process and realize a narrow frame.

The invention discloses a display panel, comprising: a display area and a non-display area disposed around the display area; a plurality of scan lines extending in a first direction and a plurality of signal lines extending in a second direction, the first direction and the second direction intersecting; the non-display area comprises a binding area, the binding area comprises a first area and a second area, the first area comprises a plurality of first conductive pads, and the second area comprises a plurality of second conductive pads; in the second direction, the second area is positioned on one side of the first area far away from the display area; the display panel also comprises a test circuit, wherein the test circuit comprises a plurality of switch transistors which are electrically connected, the grid electrodes of the switch transistors are connected with a switch control signal line, the source electrodes of the switch transistors are connected with a reference voltage line, and the drain electrodes of the switch transistors are connected with the signal line; in the second direction, the switch control signal line and the reference voltage line are both positioned on one side of the switch transistor close to the display area; in the second direction, each second conductive pad comprises a vertex or an edge close to one side of the first conductive pad, the connecting line of at least part of the vertexes or the edges is a first connecting line, and the first connecting line extends along the first direction; in the second direction, at least part of the switch transistor is positioned on one side of the first connecting line far away from the display area.

Based on the same inventive concept, the invention also discloses a display device, which comprises the display panel.

Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:

in the display panel of the invention, the distance between two adjacent second conductive pads in the first direction can be set to be larger than the distance between two adjacent first conductive pads in the first direction, the switch transistor is in a single structure in the test circuit, and then a space is provided for at least part of the switch transistors in the test circuit to be arranged on one side of the first connecting line far away from the display area, namely, a possibility is provided for the structure of part of the test circuit to sink between the second conductive pads. The display panel provided by the invention better utilizes the characteristics that the second conductive bonding pads are fewer than the first conductive bonding pads in quantity and can be arranged at a large interval, the second conductive bonding pads are arranged in the second direction, the switch control signal line and the reference voltage line are both positioned on one side of the switch transistor close to the display area, and at least part of the switch transistors in the test circuit are positioned on one side of the first connecting line far away from the display area, so that the arrangement area of the test circuit is not required to be reduced, the test circuit is ensured to have enough arrangement space as far as possible, the delay of screen lightening in the test process is avoided, the poor detection efficiency of a production line is improved, and a narrower frame can be realized while the test requirement is met.

Of course, it is not necessary for any product in which the present invention is practiced to specifically achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a partially enlarged structure of the bonding region in FIG. 1;

FIG. 3 is a schematic plan view of another display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another enlarged partial structure of the bonding region in FIG. 1;

FIG. 5 is a schematic diagram of another enlarged partial structure of the bonding region of FIG. 1;

FIG. 6 is a schematic diagram of another enlarged partial structure of the bonding region in FIG. 1;

FIG. 7 is a schematic diagram of a planar structure of another display panel according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a planar structure of another display panel according to an embodiment of the present invention;

FIG. 9 is a partial enlarged structural view of the bonding region of FIG. 8;

fig. 10 is a schematic plan view of another display panel according to an embodiment of the present invention;

fig. 11 is a schematic plan view of another display panel according to an embodiment of the present invention;

fig. 12 is a schematic plan view of another display panel according to an embodiment of the present invention;

fig. 13 is a schematic plan view of another display panel according to an embodiment of the present invention;

fig. 14 is a schematic plan view of another display panel according to an embodiment of the present invention;

fig. 15 is a schematic plan view of another display panel according to an embodiment of the present invention;

FIG. 16 is a partial enlarged structural view of a region M of the bonding region in FIG. 15;

FIG. 17 is a schematic view of another enlarged partial structure of a region M of the bonding region in FIG. 15;

FIG. 18 is a schematic view of another enlarged partial structure of a region M of the bonding region in FIG. 15;

FIG. 19 is a schematic view of another enlarged partial structure of a region M of the bonding region in FIG. 15;

FIG. 20 is a schematic view of another enlarged partial structure of a region M of the bonding region in FIG. 15;

FIG. 21 is a schematic view of another enlarged partial structure of a region M of the bonding region in FIG. 15;

FIG. 22 is a schematic view of another enlarged partial structure of a region M of the bonding region in FIG. 15;

fig. 23 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Among the many factors affecting the size of the display frame in the related art, the driver ic plays an important role. The conventional structure of the driving integrated circuit is to arrange the driving integrated circuit on a substrate, and an array test (array test) circuit and a cell test (cell test) circuit for detecting the electrical property of the whole display panel are directly arranged between an input circuit and an output circuit of the driving integrated circuit. Along with the gradual narrowing of the frame, the size of the driving integrated circuit is also gradually reduced, and the residual space is not enough for placing the array test circuit and the unit test circuit, so that the test requirement is met.

Based on the above problem, the application provides a display panel and a display device, which can meet the test requirement in the panel manufacturing process and can realize a narrow frame. Specific embodiments of the display panel and the display device proposed in the present application are described in detail below.

Referring to fig. 1, fig. 1 is a schematic plan view of a display panel according to an embodiment of the present invention, fig. 2 is a schematic partial enlarged structural view of a bonding area in fig. 1 (for clearly illustrating a structure of a test circuit in the present embodiment, the test circuit in fig. 1 is represented by a block diagram, and a specific structure can refer to an enlarged view of fig. 2), and the display panel according to the present embodiment includes: a display area AA and a non-display area NA disposed around the display area AA; the touch panel comprises a plurality of scanning lines 10 extending along a first direction X and a plurality of signal lines 20 extending along a second direction Y, wherein the signal lines 20 optionally comprise data signal lines and/or touch signal lines, the first direction X intersects with the second direction Y, and optionally the first direction X is perpendicular to the second direction Y;

the non-display area NA includes a bonding area BA including a first area BA1 and a second area BA2, the first area BA1 including a plurality of first conductive pads 30, the second area BA2 including a plurality of second conductive pads 40; in the second direction Y, the second area BA2 is located on a side of the first area BA1 away from the display area AA;

as shown in fig. 2, the display panel 000 further includes a testing circuit 50, the testing circuit 50 includes a plurality of electrically connected switching transistors 60, gates of the switching transistors 60 are connected to a switching control signal line 70, sources of the switching transistors 60 are connected to a reference voltage line 80, and drains of the switching transistors 60 are connected to the signal lines 20 (not shown) within the display area AA; in the second direction Y, the switch control signal line 70 and the reference voltage line 80 are both located at a side of the switching transistor 60 close to the display area AA;

in the second direction Y, each second conductive pad 40 includes a vertex a or an edge B (illustrated by taking the edge B as an example in fig. 2) close to one side of the first conductive pad 30, and a connection line of at least a part of the vertex a or the edge B is a first connection line K, and the first connection line K extends along the first direction X;

in the second direction Y, at least a portion of the switch transistors 60 is located on a side of the first connection line K away from the display area AA (for clarity of illustrating the structure of the test circuit 50, fig. 2 only shows the number and size of the switch transistors 60 in the test circuit, and the switch transistors can be arranged according to practical situations when implemented).

Specifically, the bonding area BA of the display panel 000 of the embodiment is used for bonding a driving circuit (a driving chip or a flexible circuit board), and the driving circuit bonded in the bonding area BA is used for providing a driving signal for implementing a display function for the display panel. The bonding area BA includes a first area BA1 and a second area BA2 arranged in this order in the second direction Y (the extending direction of the signal lines 20), and the second area BA2 is located on the side of the first area BA1 away from the display area AA in the second direction Y. The first area BA1 includes a plurality of first conductive pads 30, the first conductive pads 30 may be output conductive pads, the second area BA2 includes a plurality of second conductive pads 40, the second conductive pads 40 may be input conductive pads, the second conductive pads 40 are configured to be electrically connected to respective input signal terminals of the driving circuit in a one-to-one binding manner, and the driving signal is input from the second conductive pads 40 to the driving circuit, the first conductive pads 30 are configured to be electrically connected to respective output signal terminals of the driving circuit in a one-to-one binding manner, and the driving signal input from the second conductive pads 40 to the driving circuit is output from the first conductive pads 30 to the display panel 000, so as to provide the display panel with a driving signal for implementing a display function. The non-display area NA range of the display panel 000 of the embodiment includes the test circuit 50, and the test circuit 50 is used for detecting whether there is a defect such as a foreign object, mura, or a bright spot in the screen when the driving circuit is not attached, and in order to meet the test requirement, a large space is required to set the test circuit 50 with a large enough area on the display panel, otherwise, in the test process, the screen is lit, and the test circuit is not suitable for detecting defects in a production line. The test circuit 50 includes a plurality of switch transistors 60 electrically connected to each other, the switch transistors 60 are used to control whether the test circuit 50 is turned on, and the switch transistors 60 are temporary operating switches of the display panel 000 during process inspection in the production line process. The gate of the switching transistor 60 is connected to a switching control signal line 70, the drain of the switching transistor 60 is connected to the signal line 20 in the display area AA, and the switching control signal line 70 is used for controlling whether a test detection signal is input to a pixel of the display area AA through the signal line 20; the source of the switching transistor 60 is connected to a reference voltage line 80, the reference voltage line 80 is used for providing a test data voltage signal for the pixels in the display area AA, the pixels can be lit up for testing during the test operation, and the reference voltage line 80 is generally electrically connected to a test data signal source, so that the function of inputting the test data signal to the display panel for the screen lighting test is realized. The switch transistor 60 connects the reference voltage line 80 with all data lines, touch lines, and drive lines of the shift register in the panel, and when the switch transistor 60 is turned on, the above lines are applied with working voltage, and the screen works; when the switching transistor 60 is turned off, the above wirings are not applied with the operating voltage, and the screen does not operate.

In the related art, the test circuit 50 is generally disposed between the first area BA1 and the second area BA2 along the second direction Y, and at this time, if a narrow frame is to be realized, the panel space occupied by the test circuit 50 between the first area BA1 and the second area BA2 must be reduced, which is not favorable for meeting the test requirement and the poor production line detection; in order to satisfy the test requirements and the inspection failure of the production line, the panel space occupied by the test circuit 50 must be increased, and a narrow bezel cannot necessarily be realized.

In order to solve the above problem, unlike the prior art in which the switch control signal line 70 and the reference voltage line 80 are both located on the side of the switch transistor 60 away from the display area AA, the present embodiment is designed such that the switch control signal line 70 and the reference voltage line 80 are both located on the side of the switch transistor 60 close to the display area AA in the second direction Y, and generally, when the second conductive pad 40 is used as an input conductive pad, there are fewer signal terminals required to be input to the inside of the driving circuit, so the number of the second conductive pads 40 is less than the number of the first conductive pads 30, and therefore, the distance between two adjacent second conductive pads 40 in the first direction X can be set to be larger than the distance between two adjacent first conductive pads 30 in the first direction X. Furthermore, in the second direction Y, at least a portion of the switch transistors 60 in the test circuit 50 is located on a side of the first connection line K away from the display area AA, where the first connection line K is defined as: in the second direction Y, each of the second conductive pads 40 includes a vertex a or an edge B near one side of the first conductive pad 30, and a connection line of at least a part of the vertex a or the edge B is a first connection line K, and the first connection line K extends along the first direction X. Since the distance between two adjacent second conductive pads 40 in the first direction X in the present embodiment may be set to be larger than the distance between two adjacent first conductive pads 30 in the first direction X, the switch transistor 60 is a separate structure in the test circuit 50, and then a space is provided for at least a part of the switch transistor 60 in the test circuit 50 to be disposed on a side of the first connection line K away from the display area AA, that is, it is possible for a part of the structure of the test circuit 50 to sink between the second conductive pads 40. The display panel 000 of the embodiment preferably utilizes the characteristics that the number of the second conductive pads 40 is less than that of the first conductive pads 30, and the distance between the second conductive pads can be set to be large, so that the structure of the partial switch transistor 60 in the test circuit 50 is sunk between the second conductive pads 40, and the space between the first area BA1 and the second area BA2 in the second direction Y is reduced, thereby realizing a narrower frame, and not affecting the test effect of the test circuit 50. The display panel 000 of the embodiment is in the second direction Y, the switch control signal line 70 and the reference voltage line 80 are both located on one side of the switch transistor 60 close to the display area AA, and at least part of the switch transistor 60 in the test circuit 50 is located on one side of the first connection line K away from the display area AA, the setting area of the test circuit 50 is not required to be reduced, it is ensured as much as possible that the test circuit 50 has a sufficient setting space, delay when the screen is lit in the test process is avoided, poor efficiency of production line detection is improved, a narrower frame is realized while test requirements are met.

It should be noted that, in the arrangement manner of the second conductive pads 40 shown in fig. 1 of the present embodiment, in the second direction Y, each second conductive pad 40 includes an edge B close to one side of the first conductive pad 30, a connection line of all the edges B is a first connection line K, and the first connection line K extends along the first direction X. Optionally, as shown in fig. 3, fig. 3 is a schematic plan view of another display panel according to an embodiment of the present invention, and another arrangement manner of the second conductive pads 40 in the second area BA2 shown in fig. 3 is that adjacent second conductive pads 40 are arranged in a staggered manner in the second direction Y, that is, in all the second conductive pads 40 along the first direction X, odd-numbered second conductive pads 40 of the first, third, fifth, and … … are arranged in a flush manner, and even-numbered second conductive pads 40 of the second, fourth, sixth, and … … are arranged in a flush manner, which is beneficial to reducing the risk of short circuit between adjacent second conductive pads 40; in the arrangement of the second conductive pads 40 shown in fig. 3, in the second direction Y, each second conductive pad 40 includes an edge B (the edge B is taken as an example in fig. 3) close to one side of the first conductive pad 30, a connection line of a partial edge B (the second conductive pad 40 closer to the first area BA 1) is a first connection line K, and the first connection line K extends along the first direction X, so that the arrangement of the second conductive pads 40 is flexible, and meanwhile, the second conductive pads 40 can be regularly arranged, which is beneficial to improving the manufacturing efficiency.

It should be further noted that fig. 1 and 3 of the present embodiment illustrate the shape of the conductive pads by taking the first conductive pads 30 and the second conductive pads 40 as regular rectangles as an example, in practical implementation, the shape of the conductive pad may not be in a regular pattern due to the limitation of process conditions, as shown in fig. 4 and 5, fig. 4 is a schematic view of another partially enlarged structure of the bonding region of fig. 1, fig. 5 is a schematic view of another partially enlarged structure of the bonding region of fig. 1, the shapes of the first conductive pad 30 and the second conductive pad 40 in fig. 4 and 5 are long strips as a whole, however, the second conductive pads 40 have a structure in which the side close to the first conductive pad 30 is a dot-shaped structure, and in this case, in the second direction Y, each second conductive pad 40 includes a vertex a close to the first conductive pad 30, and a connection line of at least a part of the vertices a is a first connection line K.

In some alternative embodiments, please refer to fig. 1 and fig. 6 in combination, fig. 6 is another schematic partial enlarged structure diagram of the bonding region in fig. 1, in this embodiment, along the first direction X, an orthogonal projection of at least a portion of the switch transistor 60 on the light-emitting surface of the display panel 000 is located between two adjacent second conductive pads 40.

The present embodiment further explains that the orthographic projection of at least a part of the switch transistors 60 in the test circuit 50 on the light-emitting surface of the display panel 000 is located between two adjacent second conductive pads 40, so that at least a part of the switch transistors 60 or all the switch transistors 60 in the test circuit 50 can be disposed on one side of the first connection line K away from the display area AA, so that the test circuit 50 has a sufficient disposition space, delay in the process of testing the screen is avoided, poor production line detection efficiency is improved, and while the test requirement is met, a narrower frame is facilitated to be realized.

It should be noted that, in this embodiment, the number of the switch transistors 60 disposed between two adjacent second conductive pads 40 is not specifically limited, one switch transistor 60 may be disposed between two adjacent second conductive pads 40, or a plurality of switch transistors 60 may be disposed, and in the specific implementation, the number may be set according to the size of the space between two adjacent second conductive pads 40 and the size of the space in which one switch transistor 60 needs to be disposed, and this embodiment is not specifically limited herein.

In some alternative embodiments, with continuing reference to fig. 1-2, in the present embodiment, in the first direction X, the distance L2 between two adjacent second conductive pads 40 is greater than the distance L1 between two adjacent first conductive pads 30.

The present embodiment further explains that the second conductive pads 40 can be used as input conductive pads, and in this case, since there are fewer signal terminals required to be input to the inside of the driving circuit, the number of the second conductive pads 40 is smaller than that of the first conductive pads 30, and therefore, the distance L2 in the first direction X between two adjacent second conductive pads 40 can be set larger than the distance L1 in the first direction X between two adjacent first conductive pads 30. Since the switch transistor 60 is a separate structure in the test circuit 50, a space is provided for at least a part of the switch transistor 60 in the test circuit 50 to be disposed on a side of the first connection line K away from the display area AA, that is, it is possible for a part of the structure of the test circuit 50 to sink to between two adjacent second conductive pads 40. The display panel 000 of the embodiment preferably utilizes the fact that the number of the second conductive pads 40 is less than that of the first conductive pads 30, and the structure of the partial switch transistor 60 in the test circuit 50 is sunk between the second conductive pads 40, which is not only beneficial to reducing the space between the first area BA1 and the second area BA2 in the second direction Y, but also beneficial to realizing a narrower frame, and the test effect of the test circuit 50 is not affected.

In some optional embodiments, please refer to fig. 7, fig. 7 is a schematic plane structure diagram of another display panel provided in the embodiments of the present invention, in which the bonding area BA includes a plurality of input pads 90 in the embodiment_inAnd a plurality of output pads 90_outInput pad 90_inIncluding scan driving signal input pad and driving chip signal input pad, output pad 90_outIncluding a scan driving signal output pad 901_outAnd driver chip signal output pad 902_out；

Driver chip signal output pad 902_outElectrically connected to signal line 20, optionally, driver chip signal output pad 902_outElectrical connections to the signal lines 20 may be made through fan-out traces (not shown) of the fan-out area;

the scan line 10 is connected to a scan driving circuit 100 (illustrated in a frame, and when implemented, it can be understood with reference to the scan driving circuit in the related art), and a scan driving signal output pad 901_outAn optional scan driving signal output pad 901 electrically connected to the scan driving circuit 100_outCan be electrically connected with the scan driving circuit 100 through a connection trace (not shown);

wherein the second conductive pad 40 is an input pad 90_inAnd/or scan driving signal output pad 901_out. Optionally, an input pad 90_inAnd a scan driving signal output pad 901_outAre located in the second area BA 2.

The present embodiment further illustrates that the bonding area BA is provided with a plurality of conductive pads, including a plurality of input pads 90_inAnd a plurality of output pads 90_outAnd is used for bonding and electrically connecting with a driving unit (not shown), the driving unit can be a driving chip or a flexible circuit board, the driving unit is provided with a plurality of input pins and output pins, the input pins are correspondingly bonded with the input bonding pads of the bonding area BA one by one, and the output pins are bonded with the output bonding pads 90 of the bonding area BA_outOne-to-one binding through the input pad 90_inThe driving signal supplied from the driving unit is inputted through the output pad 90_outOutputs the inputted driving signal to the display panel 000, wherein the output pad 90_outIncluding a scan driving signal output pad 901_outAnd driver chip signal output pad 902_outDriver chip signal output pad 902_outAnd signal line20 are electrically connected for providing a data voltage signal and/or a touch detection signal to the signal line 20 via the driving unit. The scan line 10 is connected with a scan driving circuit 100, and a scan driving signal output pad 901_outIs electrically connected to the scan driving circuit 100 for providing scan signals to the scan lines 10 through the driving unit. The present embodiment will bind output pads 90 within the area BA_outAnd classification for transmitting the scan driving signal and the data driving/touch driving signal, thereby clearly distinguishing. Since there are fewer signal terminals required to be inputted to the inside of the driving circuit, the input pad 90_inThe scan driving signal input pad and the driving chip signal input pad of (1) may be both the second conductive pad 40, and the scan driving signal output pad 901_outIs also small in number, and thus the scan driving signal output pads 901_outIt can also be used as the second conductive pad 40, i.e. the second conductive pad 40 is the input pad 90_inAnd/or scan driving signal output pad 901_out(FIG. 7 of the present embodiment takes the second conductive pad 40 as the input pad 90_inAnd a scan driving signal output pad 901_outI.e. input pads 90_inAnd a scan driving signal output pad 901_outAre located in the second area BA2 for illustration), so as to provide enough space for disposing the first conductive pads 30 in the first area BA1, and avoid short circuit between the first conductive pads 30.

In some optional embodiments, please refer to fig. 8 and 9, fig. 8 is a schematic plan structure diagram of another display panel according to an embodiment of the present invention, fig. 9 is a schematic partial enlarged structure diagram of a bonding region in fig. 8 (for clarity, to illustrate a structure of the test circuit of the present embodiment, the test circuit 50 in fig. 8 is shown in a block diagram, and a specific structure may refer to the structure of the test circuit in fig. 9 of the present embodiment);

in the second direction Y, the distance from the first sub-pad 301 to the first wire K is smaller than the distance from the second sub-pad 302 to the first wire 302.

The present embodiment further explains that in order to achieve a narrower frame, it may be designed that there are portions of the first conductive pad 30 close to the second conductive pad 40, that is, in the second direction Y, the distance H1 from the first sub-pad 301 to the first wire K is smaller than the distance H2 from the second sub-pad 302 to the first wire 302. In the related art, since the distance H1 from the first sub-pad 301 to the first wire K in the first conductive pad 30 is smaller than the distance H2 from the second sub-pad 302 to the first wire K in the first conductive pad 30 in the second direction Y in the display panel for realizing the narrow bezel structure, thereby reducing the space between the first conductive pad 30 and the second conductive pad 40, being disadvantageous to laying a test circuit 50 with a larger area, failing to meet the test requirements, in the display panel 000 of this configuration, therefore, the configuration in which the part of the switching transistor 60 in the test circuit 50 is disposed sinks between the second conductive pads 40, so that in the case of narrowing the space between the first area BA1 and the second area BA2 in the second direction Y to achieve a narrower border, the layout area of the test circuit 50 is not affected, the test effect is improved, and the test requirement is met.

It should be noted that, in the second direction Y of the present embodiment, the distance H1 from the first sub-pad 301 to the first connection line K is smaller than the distance H2 from the second sub-pad 302 to the first connection line K, and as shown in fig. 8, the distances H1 from all the first sub-pads 301 to the first connection line K are equal and are smaller than the distance H2 from the second sub-pad 302 to the first connection line K; as shown in fig. 10, fig. 10 is a schematic plan view of another display panel provided by the embodiment of the present invention, in which the distance H1 from the first sub-pad 301 to the first connection line K is gradually decreased in the second direction Y along the direction away from the second sub-pad 302, but the distance from the first sub-pad 301 closest to the second sub-pad 302 to the first connection line K is still less than the distance H2 from the second sub-pad 302 to the first connection line K; as shown in fig. 11, fig. 11 is a schematic plan view of another display panel according to an embodiment of the present invention, in a direction away from the second sub-pad 302, in the second direction Y, first, a distance H1 from a part of the first sub-pad 301 to the first connection line K is gradually decreased, and then, distances H1 from the remaining part of the first sub-pad 301 to the first connection line K are all equal, but the distance from all the first sub-pads 301 to the first connection line K is smaller than the distance H2 from the second sub-pad 302 to the first connection line K. The distances H2 from the second sub-pads 302 to the first connection line K may be the same, or a part of the second sub-pads 302 may be far from the first connection line K and another part of the second sub-pads 302 may be near to the first connection line K (not shown). The arrangement of the first conductive pads 30 may be various, and this embodiment is not particularly limited, and it is only required that in the second direction Y, the distance H1 from the first sub-pad 301 to the first connection line K is smaller than the distance H2 from the second sub-pad 302 to the first connection line K.

It should be further noted that, in fig. 8 to 11 of this embodiment, a plurality of first sub-pads 301 and a plurality of second sub-pads 302 of the plurality of first conductive pads 30 are both in a structure of being arranged in a row, optionally, the plurality of first conductive pads 30 sequentially arranged along the first direction X may also be divided into two or more rows, and the two or more rows of first conductive pads 30 are sequentially arranged in the second direction Y, that is, the arrangement of the plurality of first sub-pads 301 and the plurality of second sub-pads 302 may also be the second conductive pads 40 shown in fig. 3 in the above embodiment, the first conductive pads 30 adjacent to each other in the first direction X are alternately arranged in the second direction Y (not shown in the drawing). At this time, in the second direction Y, a distance from the first sub-pad 301 to the first wire K refers to a distance from the first sub-pad 301 to the first wire K in the same row of the first conductive pad 30, and a distance from the second sub-pad 302 to the first wire K refers to a distance from the second sub-pad 302 to the first wire K in the same row of the first conductive pad 30.

Optionally, referring to fig. 12, fig. 12 is a schematic plan view of another display panel according to an embodiment of the present invention, in this embodiment, a fan-out area FA is disposed on a side of the first area BA1 close to the display area AA, a plurality of fan-out leads 110 are disposed in the fan-out area FA, and the signal lines 20 in the display area AA are electrically connected to the first conductive pads 30 in the bonding area BA through the fan-out leads 110, wherein a first fan-out lead 1101 is electrically connected to the first sub-pad 301, a second fan-out lead 1102 is electrically connected to the second sub-pad 302, and a distance H1 from the first sub-pad 301 to the first connection line K in the second direction Y along a direction away from the second sub-pad 302 is gradually reduced, but a distance H2 from the first sub-pad 301 closest to the second sub-pad 302 to the first connection line K is still smaller than a distance H2 from the second sub-pad 302 to the first connection line K, so that the first sub-pad 301 connected to the first sub-pad 301 is bent to a side away from the display area AA as far as possible, further, the width of the fan-out area FA in the second direction Y is advantageously reduced, that is, a narrower frame can be further realized.

In some optional embodiments, please refer to fig. 13, fig. 13 is a schematic plan view illustrating a planar structure of another display panel according to an embodiment of the present invention, in this embodiment, the plurality of first conductive pads 30 at least includes a plurality of third sub-pads 303, a plurality of fourth sub-pads 304, and a plurality of fifth sub-pads 305, and in the first direction X, the third sub-pads 303 and the fifth sub-pads 305 are respectively located on two opposite sides of the fourth sub-pads 304;

in the second direction Y, the distance from the third sub-pad 303 to the first connection line K is a, the distance from the fourth sub-pad 304 to the first connection line K is B, and the distance from the fifth sub-pad 305 to the first connection line K is C, where a < B and C < B.

The embodiment further explains that in order to realize a narrower frame, it may be designed that a plurality of third sub-pads 303 and a plurality of fifth sub-pads 305 in the first conductive pad 30 are close to each other in a direction close to the second conductive pad 40, and in the first direction X, the third sub-pads 303 and the fifth sub-pads 305 are respectively located on two opposite sides of the fourth sub-pad 304, that is, part of the sub-pads on two sides in the first conductive pad 30 are close to each other in a direction close to the second conductive pad 40, so as to form a structure in which an OLB (Outer Lead Bonding) region is sunk. When the display panel normally displays, a Chip On Film (COF) needs to be connected to the outer lead bonding region of the panel through a lead, so that the driving signal integrated on the COF is conducted to the panel through the OLB region. In the second direction Y of the present embodiment, a distance a from the third sub-pad 303 to the first connection line K is smaller than a distance B from the fourth sub-pad 304 to the first connection line K, and a distance C from the fifth sub-pad 305 to the first connection line K is smaller than a distance B from the fourth sub-pad 304 to the first connection line K. Optionally, in the second direction Y, a distance a from the third sub-pad 303 to the first connection line K is equal to a distance C from the fifth sub-pad 305 to the first connection line K, that is, the third sub-pad 303 and the fifth sub-pad 305 are symmetrical to each other with respect to a central axis of the fourth sub-pad 304 extending along the second direction Y, and the third sub-pad 303 and the fifth sub-pad 305 are also equal in number, so that widths of the bonding area BA in the second direction Y are substantially the same, and when the display panel is cut, it is beneficial to avoiding a risk of damage to the routing wire due to abnormal cutting.

Optionally, in the direction away from the fourth sub-pad 304, the distance a from the third sub-pad 303 to the first connection line K in the second direction Y gradually decreases, but the distance from the third sub-pad 303 closest to the fourth sub-pad 304 to the first connection line K is still smaller than the distance B from the fourth sub-pad 304 to the first connection line K; and the distance C of the fifth sub-pad 305 to the first wire K in the second direction Y is gradually decreased in a direction away from the fourth sub-pad 304, but the distance of the fifth sub-pad 305 closest to the fourth sub-pad 304 to the first wire K is still smaller than the distance B of the fourth sub-pad 304 to the first wire K (as shown in fig. 13). The sinking structure of the OLB area in the non-display area NA is beneficial to reducing the width of the fan-out area in the second direction Y, and a narrower frame is realized. Because the space between the third sub-pad 303 and the first connection line K is reduced, the space between the fifth sub-pad 305 and the first connection line K is also reduced, which is not beneficial to laying the large-area test circuit 50, and the test requirement cannot be met, in the display panel 000 with the structure of this embodiment, the structure of the partial switch transistor 60 in the test circuit 50 is set to sink between the second conductive pads 40, so that the space between the first area BA1 and the second area BA2 in the second direction Y is reduced to realize a narrower frame, the laying area of the test circuit 50 is not affected, which is beneficial to improving the test effect, and the test requirement is met.

It should be noted that, in fig. 13 of this embodiment, the third sub-pads 303, the fourth sub-pads 304, and the fifth sub-pads 305 of the first conductive pads 30 are all configured in a row, and optionally, the first conductive pads 30 may also be divided into two or more rows, and the two or more rows of the first conductive pads 30 are sequentially arranged in the second direction Y, that is, the third sub-pads 303, the fourth sub-pads 304, and the fifth sub-pads 305 may also be arranged in the second conductive pads 40 as shown in fig. 3 of the above embodiment, and the first conductive pads 30 adjacent to each other in the first direction X are arranged in a staggered manner in the second direction Y (not shown in the figure). At this time, in the second direction Y, the distance from the third sub-pad 303 to the first wire K refers to the distance from the third sub-pad 303 to the first wire K in the same row of the first conductive pads 30, the distance from the fourth sub-pad 304 to the first wire K refers to the distance from the fourth sub-pad 304 to the first wire K in the same row of the first conductive pads 30, and the distance from the fifth sub-pad 305 to the first wire K refers to the distance from the fifth sub-pad 305 to the first wire K in the same row of the first conductive pads 30.

In some optional embodiments, please refer to fig. 14, fig. 14 is a schematic plane structure diagram of another display panel according to an embodiment of the present invention (for clearly illustrating the structure of the test circuit of the present embodiment, the test circuit 50 in fig. 14 is shown in a block diagram, and the specific structure can be understood with reference to the structure of the test circuit in the foregoing embodiment), in the present embodiment, the test circuit 50 includes a first test circuit 501, a second test circuit 502, and a third test circuit 503; wherein the content of the first and second substances,

in the first direction X, the orthographic projection of the first test circuit 501 on the light-emitting surface of the display panel 000 is located between two adjacent second conductive pads 40, and the orthographic projection of the second test circuit 502 on the light-emitting surface of the display panel 000 is located on at least one side of the second area BA 2;

in the second direction Y, the orthographic projection of the third test circuit 503 on the light emitting surface of the display panel 000 is located between the first area BA1 and the second area BA 2.

This embodiment further illustrates that, in the structure in which the sub-pads on both sides of the first conductive pad 30 are close to the second conductive pad 40 to form a sunken OLB (Outer Lead Bonding) region, since the second conductive pad 40 is used as an input conductive pad, there are fewer signal terminals required to be input to the inside of the driving circuit, the number of the second conductive pads 40 is smaller than the number of the first conductive pads 30, and the pitch between adjacent two of the second conductive pads 40 in the first direction X may be set larger than the pitch between adjacent two of the first conductive pads 30 in the first direction X, and the length of the first area BA1 in the first direction X is greater than the length of the second area BA2 in the first direction X, the two opposite sides of the second conductive pad 40 also have spaces in which the test circuit 50 can be routed, and the test circuit 50 can be routed between the first area BA1 and the second area BA2 in the second direction Y. Therefore, the testing circuit 50 of the present embodiment includes a first testing circuit 501, a second testing circuit 502, and a third testing circuit 503, wherein in the first direction X, an orthogonal projection of the first testing circuit 501 on the light-emitting surface of the display panel 000 is located between two adjacent second conductive pads 40, and an orthogonal projection of the second testing circuit 502 on the light-emitting surface of the display panel 000 is located on at least one side of the second area BA 2; in the second direction Y, the orthographic projection of the third test circuit 503 on the light-emitting surface of the display panel 000 is located between the first area BA1 and the second area BA2, so that the space of the binding area BA can be better utilized, the overall layout area of the test circuit 50 is further increased, and the test effect of the test circuit 50 is further improved while the narrow frame is not affected.

In some optional embodiments, please refer to fig. 15, fig. 15 is a schematic plane structure diagram of another display panel according to an embodiment of the present invention (for clearly illustrating the structure of the test circuit of this embodiment, the test circuit 50 in fig. 15 is shown in a block diagram, and a specific structure can be understood with reference to the structure of the test circuit in the above embodiment, a connection relationship between the switch transistor 60 and the reference voltage line 80 in the specific test circuit 50 and the switch control signal line 70 is not shown in fig. 15, and the structure of the test circuit 50 can be understood with reference to fig. 2 in the above embodiment).

The present embodiment further illustrates that the testing circuit 50 includes a first testing circuit 501, a second testing circuit 502, and a third testing circuit 503, and in the first direction X, an orthographic projection of the first testing circuit 501 on the light-emitting surface of the display panel 000 is located between two adjacent second conductive pads 40, and an orthographic projection of the second testing circuit 502 on the light-emitting surface of the display panel 000 is located on at least one side of the second area BA 2; in the second direction Y, the orthographic projection of the third test circuit 503 on the light emitting surface of the display panel 000 is located between the first area BA1 and the second area BA2, alternatively, as shown in fig. 15, the switching transistors 60 (not shown) of the first test circuit 501 and the second test circuit 502 may be connected to one branch of the switch control signal line 70, the switching transistor 60 (not shown) of the third test circuit 503 may be connected to the other branch of the switch control signal line 70, and the two branches can be connected with a bus at one side of the bonding area BA in the first direction X to form a switch control signal line 70 of a Y-shaped branched structure, and each of the reference voltage lines 80 may be disposed between two branch lines of the switch control signal line 70, an input signal required for the reference voltage line 80 may enter from the other side of the bonding area BA in the first direction X (as shown in fig. 15). The space of district BA is bound in utilization that this embodiment can be better, further increase test circuit 50's the whole area of laying, when not influencing the realization narrow frame, still be favorable to further improving under the condition of test circuit 50's test effect, first test circuit 501, second test circuit 502, third test circuit 503 share reference voltage line 80 and on-off control signal line 70, thereby be favorable to sparingly reference voltage line 80 and on-off control signal line 70 occupy the space of the district BA of binding, can reduce the wiring structure who simplifies non-display area NA, realize the narrow frame.

Optionally, with continued reference to fig. 15, the reference voltage line 80 and the switch control signal line 70 are disposed to extend along the first direction X, and in the second direction Y, the reference voltage line 80 and the switch control signal line 70 are located between the third test circuit 503 and the first test circuit 501, and the reference voltage line 80 and the switch control signal line 70 are disposed to extend along the first direction X, so that a space between the first area BA1 and the second area BA2 is preferably utilized, and the first test circuit 501, the second test circuit 502, and the third test circuit 503 can be all connected to the reference voltage line 80 and the switch control signal line 70, so as to implement sharing.

In some alternative embodiments, referring to fig. 15 and 16, fig. 16 is a schematic partial enlarged structure view of a region M of the bonding region in fig. 15, in this embodiment, along the first direction X, an orthogonal projection of at least one switch transistor 60 on the light-emitting surface of the display panel 000 is located between two adjacent second conductive pads 40. Optionally, along the first direction X, an orthogonal projection of one switch transistor 60 on the light-emitting surface of the display panel 000 is located between two adjacent second conductive pads 40, and the switch transistor 60 includes a gate 601, a source 602, a drain 603, and an active layer silicon island 604, where the gate 601 is connected to the switch control signal line 70, the source 602 is connected to the reference voltage line 80 (which may be electrically connected through a via hole, not shown in the figure), and the drain 603 is connected to a data line, a touch line, a shift register driving line, and the like in the display area AA of the display panel 000 (which are not shown in fig. 16), so as to implement a test function of the test circuit 50. In this embodiment, the structure of the partial switch transistor 60 in the test circuit 50 is sunk between the second conductive pads 40, and the orthographic projection of at least one switch transistor 60 on the light-emitting surface of the display panel 000 is located between two adjacent second conductive pads 40, so that the layout area of the test circuit 50 is not affected even when the space between the first area BA1 and the second area BA2 in the second direction Y is reduced to realize a narrower frame, which is beneficial to improving the test effect and meeting the test requirements.

In some alternative embodiments, referring to fig. 15 and 17, fig. 17 is another schematic partial enlarged structure diagram of the region M of the bonding region in fig. 15, in this embodiment, along the first direction X, an orthogonal projection of at least three (schematically illustrated in fig. 17 by taking three switch transistors 60 as an example) switch transistors 60 on the light-emitting surface of the display panel 000 is located between two adjacent second conductive pads 40. Optionally, the number of the reference voltage lines 80 is at least three, and the reference voltage lines are respectively electrically connected to the red test data signal source R, the green test data signal source G, and the blue test data signal source B, and the three reference voltage lines 80 are respectively used for providing the test data signal sources with different colors for the test circuit 50.

The present embodiment further explains that, because the size of the switch transistor 60 is small, the occupied layout area on the panel is also relatively small, so that at least three switch transistors 60 can be disposed between two adjacent second conductive pads 40 along the first direction X, which is beneficial to further realizing a narrower frame without affecting the layout area of the test circuit 50.

In some alternative embodiments, referring to fig. 15, 17 and 18 in combination, fig. 18 is another schematic partial enlarged structure diagram of the region M of the bonding region in fig. 15, in this embodiment, at least three switching transistors 60 between two adjacent second conductive pads 40 are sequentially arranged along the first direction X, or at least three switching transistors between two adjacent second conductive pads 40 are sequentially arranged along the second direction Y.

This embodiment further explains that when at least three switch transistors 60 are disposed between two adjacent second conductive pads 40, the at least three switch transistors 60 may be sequentially arranged along the first direction X (as shown in fig. 17), and optionally, both the source 602 lead line and the drain 603 lead line of the switch transistor 60 may be parallel to the signal line 20 in the display area AA, that is, may be disposed to extend along the second direction Y; the at least three switch transistors 60 may also be sequentially arranged along the second direction Y (as shown in fig. 18), optionally, at this time, the source 602 outgoing line and the drain 603 outgoing line of the switch transistor 60 may both be parallel to the arrangement direction of the switch transistor 60, that is, both may be extended along the second direction Y, in this embodiment, at least three switch transistors 60 may be arranged between two adjacent second conductive pads 40 along the first direction X, which is beneficial to further realizing a narrower frame on the premise of not affecting the layout area of the test circuit 50.

In some alternative embodiments, referring to fig. 15, fig. 19 and fig. 20 in combination, fig. 19 is a schematic diagram of another partial enlarged structure of a region M of the bonding region in fig. 15, and fig. 20 is a schematic diagram of another partial enlarged structure of the region M of the bonding region in fig. 15, in this embodiment, two switching transistor groups 600 are disposed between two adjacent second conductive pads 40, and each switching transistor group 600 includes at least three switching transistors 60;

the two switching transistor groups 600 are sequentially arranged in the first direction X, or the two switching transistor groups 600 are sequentially arranged in the second direction Y.

The present embodiment further explains that, because the size of the switch transistor 60 is small, the occupied layout area on the panel is also relatively small, so that at least two switch transistor groups 600 may be disposed between two adjacent second conductive pads 40 along the first direction X, and each switch transistor group 600 includes at least three switch transistors 60, which is beneficial to further realizing a narrower frame without affecting the layout area of the test circuit 50. Optionally, when two switch transistor groups 600 are disposed between two adjacent second conductive pads 40, and each switch transistor group 600 includes at least three switch transistors 60, at least three switch transistors 60 of each switch transistor group 600 may be sequentially arranged along the first direction X, that is, two switch transistor groups 600 are sequentially arranged along the second direction Y (as shown in fig. 19), and optionally, both the source lead 602 and the drain 603 lead of the switch transistor 60 are disposed to extend along the second direction Y; the at least three switch transistors 60 of each switch transistor group 600 may also be sequentially arranged along the second direction Y, that is, the two switch transistor groups 600 are sequentially arranged along the first direction X (as shown in fig. 20), optionally, at this time, the source 602 outgoing line and the drain 603 outgoing line of the switch transistor 60 may both be extended and disposed along the second direction Y, and in this embodiment, two switch transistor groups 600 may be disposed between two adjacent second conductive pads 40 along the first direction X, which is beneficial to further realizing a narrower frame on the premise of not affecting the layout area of the test circuit 50.

In some alternative embodiments, referring to fig. 15 and fig. 21, fig. 21 is another schematic diagram of a partial enlarged structure of the region M of the bonding region in fig. 15, in this embodiment, the gate 601 and the switch control signal line 70 of each switch transistor 60 between two adjacent second conductive pads 40 are disposed in the same layer and have an overall structure (the same filling pattern in fig. 21 indicates that the gate is disposed in the same layer and has an overall structure).

The present embodiment further explains that since the gate 601 of each switch transistor 60 between two adjacent second conductive pads 40 is electrically connected to the switch control signal line 70, the gate 601 and the switch control signal line 70 of each switch transistor 60 can be disposed in the same layer, and are of an integral structure, and since the gate 601 and the source 602, and the drain 603 of each switch transistor 60 are disposed in different layers, even if the gate 601 and the switch control signal line 70 of the switch transistor 60 are designed as a monolithic structure, a short circuit is not caused. The film layer where the gate 60 of the switching transistor 60 and the switching control signal line 70 are located can be designed as a whole structure in this embodiment, which is beneficial to reducing the etching process, and can also reduce the expansion and warpage difference caused by the temperature difference between the bonding area BA and other nearby areas when the driving chip is bonded and attached.

In some optional embodiments, please refer to fig. 15 and fig. 22, fig. 22 is another partial enlarged structural diagram of a region M of the bonding region in fig. 15, in this embodiment, the second conductive pads 40 include at least one floating second conductive pad 401 and a plurality of effective second conductive pads 402, and the floating second conductive pad 401 does not receive an electrical signal; in a direction perpendicular to the light emitting surface of the display panel 000, the gate 601 of each switching transistor 60 between two adjacent second conductive pads 40 overlaps with the floating second conductive pad 401. Optionally, the number of the suspended second conductive pads 401 may be 1 or more, and the setting positions of the suspended second conductive pads 401 in all the second conductive pads 40 are not specifically limited in this embodiment, and may be selectively set according to requirements in actual implementation.

The embodiment further explains that the second conductive pad 40 includes at least one suspended second conductive pad 401 and a plurality of effective second conductive pads 402, wherein the suspended second conductive pad 401 is not connected with an electrical signal, that is, the suspended second conductive pad 401 is a dummy pad, and the suspended second conductive pad 401 has no actual signal output and is only used for supporting a chip when a driver chip is bound; while the active second conductive pad 402 has the actual signal output. Therefore, the embodiment is disposed in a direction perpendicular to the light emitting surface of the display panel 000, and the gate 601 of each switch transistor 60 between two adjacent second conductive pads 40 overlaps with the suspended second conductive pad 401, so that the whole structure designed by the gate 601 of the switch transistor 60 and the switch control signal line 70 can be further overlapped with the suspended second conductive pad 401, which is beneficial to further reducing the etching process, and further reducing the expansion warpage difference caused by the temperature difference between the bonding area BA and other nearby areas when the driver chip is bonded and attached.

In some alternative embodiments, please refer to fig. 23, where fig. 23 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device 111 according to this embodiment includes the display panel 000 according to the above embodiment of the present invention. The embodiment of fig. 23 is only an example of a mobile phone, and the display device 111 is described, it is understood that the display device 111 provided in the embodiment of the present invention may be another display device 111 having a display function, such as a computer, a television, and a vehicle-mounted display device, and the present invention is not limited thereto. The display device 111 provided in the embodiment of the present invention has the beneficial effects of the display panel 000 provided in the embodiment of the present invention, and specific reference may be made to the specific description of the display panel 000 in the above embodiments, which is not described herein again.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

in the display panel of the invention, the distance between two adjacent second conductive pads in the first direction can be set to be larger than the distance between two adjacent first conductive pads in the first direction, the switch transistor is in a single structure in the test circuit, and then a space is provided for at least part of the switch transistors in the test circuit to be arranged on one side of the first connecting line far away from the display area, namely, a possibility is provided for the structure of part of the test circuit to sink between the second conductive pads. The display panel provided by the invention better utilizes the characteristics that the second conductive bonding pads are fewer than the first conductive bonding pads in quantity and can be arranged at a large interval, the second conductive bonding pads are arranged in the second direction, the switch control signal line and the reference voltage line are both positioned on one side of the switch transistor close to the display area, and at least part of the switch transistors in the test circuit are positioned on one side of the first connecting line far away from the display area, so that the arrangement area of the test circuit is not required to be reduced, the test circuit is ensured to have enough arrangement space as much as possible, the delay of screen lightening in the test process is avoided, the poor detection efficiency of a production line is improved, and a narrower frame is realized while the test requirement is met.

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising: a display area and a non-display area disposed around the display area; a plurality of scan lines extending in a first direction and a plurality of signal lines extending in a second direction, the first direction and the second direction intersecting;

the non-display area includes a bonding area including a first area including a plurality of first conductive pads and a second area including a plurality of second conductive pads; in the second direction, the second area is positioned on one side of the first area far away from the display area;

the display panel further comprises a test circuit, wherein the test circuit comprises a plurality of switch transistors which are electrically connected, the grid electrodes of the switch transistors are connected with a switch control signal line, the source electrodes of the switch transistors are connected with a reference voltage line, and the drain electrodes of the switch transistors are connected with the signal line; in the second direction, the switch control signal line and the reference voltage line are both located on a side of the switching transistor close to the display region;

in the second direction, each second conductive pad comprises a vertex or an edge close to one side of the first conductive pad, and the connection line of at least part of the vertexes or the edges is a first connection line which extends along the first direction;

in the second direction, at least part of the switch transistor is positioned on one side of the first connecting line far away from the display area;

along the first direction, at least part of the orthographic projection of the switch transistor on the light-emitting surface of the display panel is positioned between two adjacent second conductive bonding pads.

2. The display panel according to claim 1, wherein a distance between two adjacent second conductive pads is greater than a distance between two adjacent first conductive pads in the first direction.

3. The display panel of claim 1, wherein the bonding region comprises a plurality of input pads and a plurality of output pads, the input pads comprise a scan driving signal input pad and a driving chip signal input pad, and the output pads comprise a scan driving signal output pad and a driving chip signal output pad;

the driving chip signal output bonding pad is electrically connected with the signal wire;

the scanning line is connected with a scanning driving circuit, and the scanning driving signal output bonding pad is electrically connected with the scanning driving circuit;

wherein the second conductive pad is the input pad and/or the scan driving signal output pad.

4. The display panel according to claim 3, wherein the input pad and the scan driving signal output pad are located in the second region.

5. The display panel according to claim 1, wherein the plurality of first conductive pads includes at least a plurality of first sub-pads and a plurality of second sub-pads, the first sub-pads being located on one side of the second sub-pads in the first direction;

in the second direction, the distance from the first sub-pad to the first connecting line is smaller than the distance from the second sub-pad to the first connecting line.

6. The display panel according to claim 1, wherein the plurality of first conductive pads comprises at least a plurality of third sub-pads, a plurality of fourth sub-pads, and a plurality of fifth sub-pads, and the third sub-pads and the fifth sub-pads are respectively located on opposite sides of the fourth sub-pads in the first direction;

in the second direction, a distance from the third sub-pad to the first connection line is a, a distance from the fourth sub-pad to the first connection line is B, and a distance from the fifth sub-pad to the first connection line is C, wherein a is less than B and C is less than B.

7. The display panel according to claim 6, wherein a distance from the third sub-pad to the first wiring in the second direction is equal to a distance from the fifth sub-pad to the first wiring.

8. The display panel according to any one of claims 5 or 6, wherein the test circuit includes a first test circuit, a second test circuit, a third test circuit; wherein the content of the first and second substances,

in the first direction, the orthographic projection of the first test circuit on the light-emitting surface of the display panel is positioned between two adjacent second conductive pads, and the orthographic projection of the second test circuit on the light-emitting surface of the display panel is positioned on at least one side of the second area;

in the second direction, the orthographic projection of the third test circuit on the light-emitting surface of the display panel is located between the first area and the second area.

9. The display panel according to claim 8,

the first test circuit, the second test circuit, and the third test circuit share the reference voltage line and the switch control signal line.

10. The display panel according to claim 8,

the reference voltage line and the switch control signal line are extended along the first direction, and the reference voltage line and the switch control signal line are located between the third test circuit and the first test circuit in the second direction.

11. The display panel according to claim 1, wherein an orthographic projection of at least one of the switching transistors on a light emitting surface of the display panel along the first direction is located between two adjacent second conductive pads.

12. The display panel according to claim 1, wherein along the first direction, an orthographic projection of at least three of the switching transistors on a light emitting surface of the display panel is located between two adjacent second conductive pads;

at least three of the switching transistors are sequentially arranged along the first direction, or at least three of the switching transistors are sequentially arranged along the second direction.

13. The display panel according to claim 1, wherein two switching transistor groups are provided between adjacent two of the second conductive pads, each of the switching transistor groups including at least three of the switching transistors;

the two switch transistor groups are sequentially arranged along the first direction, or the two switch transistor groups are sequentially arranged along the second direction.

14. The display panel according to any one of claims 11 to 13, wherein the gate electrode of each of the switching transistors and the switching control signal line between two adjacent second conductive pads are disposed in the same layer and have an integral structure.

15. The display panel of claim 1, wherein the second conductive pads comprise at least one floating second conductive pad and a plurality of active second conductive pads, the floating second conductive pads not being switched in electrical signals;

in a direction perpendicular to the light emitting surface of the display panel, the gate of each switch transistor between two adjacent second conductive pads is overlapped with the suspended second conductive pad.

16. The display panel of claim 1, wherein the number of the reference voltage lines is at least three, and the reference voltage lines are respectively electrically connected to a red test data signal source, a green test data signal source, and a blue test data signal source.

17. A display device characterized by comprising the display panel according to any one of claims 1 to 16.