CN110190103B

CN110190103B - Display panel and display device

Info

Publication number: CN110190103B
Application number: CN201910471748.2A
Authority: CN
Inventors: 顾家昌; 袁山富; 彭涛
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2019-05-31
Filing date: 2019-05-31
Publication date: 2022-10-28
Anticipated expiration: 2039-05-31
Also published as: CN110190103A; CN115483262A

Abstract

The application provides a display panel and a display device, comprising a display area and a step area positioned outside the display area; the display panel comprises a substrate base plate and a plurality of power lines which are arranged on the substrate base plate and positioned in the display area along a first direction and extend along a second direction, wherein the first direction is vertical to the second direction; a functional device region including a plurality of functional devices and a power signal lead region including a first power lead pattern extending in the first direction are provided on the substrate base plate and located in the step region; and first insulating layers are arranged between the film layer of the first power supply lead pattern and all the film layers adopted by the functional device at intervals. According to the power supply lead structure, the first power supply lead pattern and the functional device form a vertically stacked three-dimensional space structure, the width of the step area is reduced, and the specification requirement of the limit narrow step is met.

Description

Display panel and display device

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of display, in particular to a display panel and a display device.

[ background of the invention ]

With the development of the information society, the demand of people for display devices is increasing. Display devices such as liquid crystal display devices and Organic Light-Emitting Diode (OLED) display devices have been rapidly developed. Among them, the OLED display device has many advantages such as active light emission, high contrast, fast response speed, light weight, and thin profile, and thus gradually occupies a leading position in the display field. At present, OLED display devices have been widely used in various high-performance display fields such as mobile phones, televisions, computers, smart watches, and the like.

Consumers seek narrow frames, and therefore, in the field of OLED display technology, how to reduce the frame is a technical problem which is being researched.

[ summary of the invention ]

In view of the above, embodiments of the present invention provide a display panel and a display device to solve the above technical problems.

In one aspect, an embodiment of the present invention provides a display panel, including a display area and a step area located outside the display area; the display panel comprises a substrate base plate and a plurality of power lines which are arranged on the substrate base plate and positioned in the display area along a first direction and extend along a second direction, wherein the first direction is vertical to the second direction; a functional device region including a plurality of functional devices and a power signal lead region including a first power lead pattern extending in the first direction are provided on the substrate base plate and located in the step region; and first insulating layers are arranged between the film layer of the first power supply lead pattern and all the film layers adopted by the functional device at intervals.

In another aspect, an embodiment of the present invention provides a display device, which includes the above display panel.

According to the display panel and the display device provided by the embodiment of the invention, the first insulating layer is arranged between the first power supply lead pattern and the functional device, and the first power supply lead pattern and the functional device form a vertically stacked three-dimensional space structure, so that the respective functions are realized, the width of a step area is reduced, and the specification requirement of a limit narrow step is met.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application;

FIG. 2 is a schematic cross-sectional view of AA' in the display panel of FIG. 1;

FIG. 3 is a partially enlarged view of a step area in the display panel of FIG. 1;

FIG. 4 is a partially enlarged view of a step area in a display panel according to the present application;

FIG. 5 is a schematic enlarged partial view of a step area in a display panel according to the present application;

FIG. 6 is an enlarged partial view of a step area in a display panel according to the present application;

FIG. 7 is a schematic cross-sectional view of an embodiment AA' of the display panel of FIG. 1;

FIG. 8 is a schematic cross-sectional view of an embodiment AA' of the display panel of FIG. 1;

FIG. 9 is a schematic cross-sectional view AA' of yet another embodiment of the display panel of FIG. 1;

FIG. 10 is a schematic cross-sectional view AA' of yet another embodiment of the display panel of FIG. 1;

FIG. 11 is an enlarged view of a portion of the stepped region of the display panel of FIG. 1;

fig. 12 is a schematic cross-sectional view of the display panel BB' of fig. 11;

FIG. 13 is a schematic view of a display device according to an embodiment of the present application;

[ detailed description ] embodiments

For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely a relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that although the terms first, second, third, etc. may be used to describe power supply lead patterns in embodiments of the present invention, these power supply lead patterns should not be limited to these terms. These terms are only used to distinguish the power supply lead patterns from one another. For example, the first power supply lead pattern may also be referred to as the second power supply lead pattern, and similarly, the second power supply lead pattern may also be referred to as the first power supply lead pattern, without departing from the scope of embodiments of the present invention.

As described in the background, the current "full screen" is becoming a new trend in the display technology field. In addition to screen ratio, uniformity of the border area is also an important factor in weighing the full screen. In a traditional display panel, the display panel comprises four frames, namely an upper frame, a lower frame, a left frame and a right frame, and special functional devices are not required to be arranged on the upper frame except for a packaging area; the widening of the left and the right generally requires the arrangement of a gate drive circuit and a packaging area; and the lower frame is that the step district usually need set up multiple functional circuit, power lead, encapsulation district and binding terminal, and its device that needs to set up is far more than last frame and frame about with, consequently, the width in step district is greater than last frame and the width of frame about for the uniformity of display panel frame width is poor, and "comprehensive screen" effect is poor. Based on this, the application provides a display panel can shorten the width in the bench district, satisfies the specification demand of the narrow step of limit. And the width of the frame tends to be uniform, and an excellent overall screen display effect is obtained.

Referring to fig. 1, fig. 2 and fig. 3, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application; FIG. 2 is a schematic cross-sectional view of AA' in the display panel of FIG. 1; FIG. 3 is a partially enlarged view of a step region in the display panel of FIG. 1;

as shown in fig. 1, 2 and 3, the display panel is provided with a display area AA and a step area STP located outside the display area 1. The display panel includes a substrate 110 and a plurality of power lines 201 disposed on the substrate 110 and located in the display area AA and arranged along a first direction D1 and extending along a second direction D2, wherein the first direction is perpendicular to the second direction. As shown in fig. 1, 2 and 3, a functional device region 30 including a plurality of functional devices 300 and a power signal lead region 20 including a first power supply lead pattern 202a extending in a first direction are provided on the substrate base 110 at the step region STP. The first insulating layer 144 is interposed between the film layer in which the first power supply lead pattern 202a is located and all the film layers employed in the functional device 300. The first insulating layer 144 serves as an insulating barrier for the first power supply lead pattern 202a and the functional device 300, and prevents a short circuit from occurring between the first power supply lead pattern 202a and the functional device 300, so that the product reject ratio of the display panel is reduced, and the display effect of the picture is improved.

In the embodiment of the present invention, the first power supply lead pattern 202a and the functional device 300 are located on different film layers, so the first power supply lead pattern 202a and the functional device 300 can be stacked on top of each other to form a three-dimensional structure. The first power supply lead pattern 202a and the functional device 300 need not be arranged in parallel in the first direction, reducing the space occupied by wiring in the stepped region, thereby enabling the display apparatus to realize a design with a narrower step. The width of the step area is reduced while the respective functions are realized, and the specification requirement of the limit narrow step is met.

As shown in fig. 2, the orthographic projection of the power signal lead region 20 and the functional device region 30 on the plane of the substrate 110 at least partially overlaps, so that the space occupied by the first power lead pattern and the wiring of the functional device in the step region is reduced, and the display device can realize a design with a narrower step. The overlapping area of the power signal lead area 20 and the functional device area 30 is greater than or equal to 50% of the area of the functional device area 30, and the space occupied by the first power lead pattern and the wiring of the functional device in the step area is further reduced, so that the display device can be designed with a narrower step.

In the embodiment of the present invention, the functional device region 30 includes at least one of a gate circuit region, a short circuit region or an ESD circuit region.

Referring to fig. 4, fig. 5 and fig. 6, fig. 4 is a schematic partial enlarged view of a step area in a display panel according to the present application; FIG. 5 is an enlarged partial view of a step area in a display panel according to the present application; FIG. 6 is an enlarged partial view of a step area in a display panel according to the present application;

referring to fig. 4, fig. 4 shows a short circuit region, where the short circuit region includes a plurality of short circuit units 301, the short circuit 301 includes a short transistor, the short transistor includes a short transistor active layer 301P and a short transistor gate 301G overlapped with the short transistor active layer, a short transistor source 301S is connected to a signal input line 3011, a short transistor drain 301D is connected to each data fanout line 402, and each short transistor gate 301G is connected to a control signal line 3012. When the control signal line 3012 is turned on, each shorting transistor is turned on, and the signal input line 3011 inputs a data signal to each data fanout line 402 through the shorting transistor and transmits the data signal to the data line 401 located in the display region. Thus, the whole display panel can be lightened only by the same data signal. Need not driver chip IC and participate in lighting, can detect the screen under the condition that does not bind driver chip IC, avoid binding the problem of rediscovery screen behind the driver chip IC, avoid extravagant driver chip, because driver chip is one of the most costly original paper in the display panel, consequently set up short circuit can greatly reduced manufacturing cost.

Referring to fig. 5, fig. 5 shows an ESD circuit region, i.e., an ESD protection circuit region. The ESD circuit region includes a plurality of ESD circuit cells 302, and the ESD circuit cells 302 include a first transistor and a second transistor. The gate 3021G of the first transistor is connected to the drain 3021D of the first transistor and the data fan-out line 402, and the source 3021S of the first transistor is connected to the low-level signal line VGL; the gate 3022G of the second transistor is connected to the drain 3022D of the second transistor and also connected to the high-level signal line VGH, and the source 3022S of the second transistor is connected to the data fanout line 402. When the data line 401 is subjected to static electricity, it is transferred to the data fanout line 402; if the static electricity is the super high level static electricity, the super high level static electricity is far higher than a high level signal of a grid electrode 3022G of the second transistor, so that the second transistor is turned on, and the super high level static electricity is led out to a high level signal line VGH through the second transistor; if the static electricity is at an ultra-low level, since the ultra-low level static electricity is transmitted to the gate 3021G of the first transistor, the potential is much lower than the low-level signal of the source 3021S of the first transistor, so that the first transistor is turned on, and the ultra-low level is led to the low-level signal line VGH through the first transistor. In the normal state, the voltage of the data fanout line 402 is between the high level and the low level, and the first transistor and the second transistor are turned off, so that the normal operation of the display panel is not affected. The ESD circuit of this embodiment can prevent the data line from being damaged due to the accumulation of static electricity on the data line 401 and the data fanout line 402, which causes display abnormality.

With continuing reference to fig. 6, fig. 6 shows a gate circuit region including a plurality of gate circuit units 303, the gate circuit units 303 including third and fourth transistors; a gate electrode 3031G of the third transistor is connected to the first gate signal line CKH1, and a drain electrode 3031D of the third transistor is connected to one data line 401; a gate 3032G of the fourth transistor is connected to the second gate signal line CKH2, and a drain 3032D of the fourth transistor is connected to the other data line 401; the sources 303S of the third transistor and the fourth transistor are simultaneously connected to the driving chip IC. In this embodiment, for example, the drain 3031D of the third transistor is connected to the data line of the odd-numbered group, the drain 3032D of the fourth transistor is connected to the data line of the even-numbered group, and when the first gate signal line CKH1 outputs the on-level and the second gate signal line CKH2 outputs the off-level, the data signal is transmitted from the driver chip IC to the data line of the odd-numbered group through the third transistor; when the first strobe signal line CKH1 outputs a cut-off level and the second strobe signal line CKH2 outputs a turn-on level, the data signal is transmitted to the data lines of the even group by the driving chip IC through the fourth transistor; therefore, the number of the data fan-out lines connected to the driving chip IC is reduced by half, the space occupied by the data fan-out lines can be greatly reduced, the width of a step area is reduced, and a narrow frame is realized.

In the embodiment of the present invention, the functional device region 30 includes at least one of a gate circuit region, a short circuit region or an ESD circuit region. Wherein, the power signal lead area 20 overlaps with the orthographic projection of any one of the gate circuit area, the short circuit area and the ESD circuit area on the plane of the substrate base plate 110; or, the power signal lead area 20 overlaps with the orthographic projections of any two of the gating circuit area, the short circuit area and the ESD circuit area on the plane of the substrate base plate 3; alternatively, the power supply signal lead region 20 overlaps with the orthographic projections of the gate circuit region, the shorting circuit region, and the ESD circuit region on the plane of the substrate base 3. FIG. 7 is a schematic cross-sectional view of an embodiment AA' of the display panel of FIG. 1; fig. 7 shows a case where the power supply signal lead region 20 overlaps with both the short circuit region 3010 and the gate circuit region 3030, and does not overlap with the ESD circuit region 3020.

In the embodiment of the present invention, a plurality of functional devices 300 may be disposed in the functional device region 30, and only 3 functional devices 300 are illustrated in fig. 4, 5, and 6 as an example. Functional device 300 may also include other functional devices, which are not listed here.

As shown in fig. 2 and 8, fig. 8 is a schematic cross-sectional view of AA' in yet another embodiment of the display panel of fig. 1; in the embodiment of the invention, each power line 201 is electrically connected to the first power lead pattern 202a through a first connecting line 203, and the first connecting line 203 is located in the step area. The first connection line 203 may be an extension line of the power line 201, that is: the first connecting line 203 is an extension line from the power line 201 to the step area STP from the display area AA; alternatively, the first connection line 203 may also be a separately provided connection line. In the embodiment of the present invention, the power line 201 may be a VDD signal line for generating a driving current for the driving circuit.

Further, in the embodiment of the present invention, the functional device region 30 includes a first metal layer 131 and a second metal layer 133 which are stacked from a position close to the substrate base plate 110 to a position far from the substrate base plate 110, a film layer used by the first power supply lead pattern 202a is a third metal layer 134, and the third metal layer 134 is located on a side of the first insulating layer 144 far from the substrate base plate 110.

Specifically, as shown in fig. 8, the display panel of the present application includes a substrate 110, an active layer 120, a first metal layer 131, a capacitor metal layer 132, a second metal layer 133, and a light emitting device electrically connected to the second metal layer, which are sequentially disposed on the substrate 110, and a package substrate 160; the light emitting device includes a first electrode layer 151, a second electrode layer 153, and an organic light emitting layer 152 between the first electrode layer 151 and the second electrode layer 153. A gate insulating layer 141 disposed between the active layer 120 and the first metal layer 131; a first interlayer insulating layer 142 disposed between the first metal layer 131 and the capacitor metal layer 132; a second interlayer insulating layer 143 disposed between the capacitor metal layer 132 and the second metal layer 133; a first insulating layer 144 disposed on a side of the second metal layer 133 away from the substrate base plate 110; and a second insulating layer 145 disposed between the first electrode 151 and the third metal layer 134. A planarization layer 144 between the third metal layer 134 and the first electrode layer 151, and a pixel defining layer 146 disposed between the first electrode layer 151 and the second electrode layer 153. In the embodiments of the present application, the first electrode layer is used as an anode, and the second electrode layer is used as a cathode.

The functional device 300 in the functional device region 30 needs to be provided with a corresponding transistor to realize the function of the device, and the transistor needs to be provided with the active layer 120 as a semiconductor, the first metal layer 131 as a gate, the second metal layer 133 as a source and a drain, and an insulating layer therebetween to form a transistor. Therefore, the third metal layer 134 and the first insulating layer 144 are disposed, the first power lead pattern 202a is disposed on the third metal layer 134 and overlapped with the functional device 300 to form a vertically stacked three-dimensional structure, so that the width of the step region is reduced while the respective functions are realized, and the specification requirement of the limit narrow step is met.

Further, referring to fig. 8, the film layer used by the power line 201 is the second metal layer 133, and the first metal layer is used to dispose a scan line as a gate of a transistor in the display panel. The second metal layer is used for arranging a data line. Because the data line is used for transmitting data signals, the accuracy of the brightness of the light-emitting device is determined, the data line requires small resistance, the scanning line only needs to turn on the transistor, and the requirement on voltage precision is not high. Therefore, the sheet resistance of the second metal layer is much smaller than that of the first metal layer. The power line 201 is arranged on the second metal layer 133, so that the voltage drop of the power line 201 can be reduced, and the display panel can display uniformly. An extension 203 of the power line of the second metal layer is located at the step area STP, and the extension 203 of the power line is electrically connected to the first power lead pattern 202a through a first via hole H1 formed in the first insulating layer 144; a power supply signal is transmitted to the power supply line 201 through the first power supply lead pattern 202 a. The first insulating layer 144 is spaced between the first power supply lead pattern 202a and the functional device 300 to form a vertically stacked three-dimensional space structure, so that the width of the step region is reduced while the respective functions are realized, and the specification requirement of the limit narrow step is met.

In another embodiment of the present application, please refer to fig. 10, fig. 10 is a schematic cross-sectional view of an AA' in another embodiment of the display panel of fig. 1; the film layer adopted by the power line 201 is the third metal layer 134, the extension line 203 of the power line 201 is positioned in the STP step area, and the extension line 203 of the power line is directly and electrically connected with the first power lead pattern 202 a; since the third metal layer 134 is provided with the first power lead pattern 203, the sheet resistance of the third metal layer is relatively small, and the power line 201 is provided in the third metal layer 134, so that the resistance of the power line 201 can be reduced, and the voltage drop of the power line can be reduced. Meanwhile, the space of the second metal layer can be left out and is given to the data line, the width of the data line is widened, and the voltage drop on the data line is reduced. And set up data line and power cord overlap, can reduce display panel's light tight district area, increase display panel's luminousness, be favorable to realizing fingerprint discernment under the screen or camera under the screen.

In another embodiment of the present application, referring to fig. 9, the power line 201 includes a first power line 201a and a second power line 201b, a film layer adopted by the first power line 201a is the second metal layer 133, a film layer adopted by the second power line 201b is the third metal layer 134, an extension 203b of the second power line 201b is located in the step area STP, the extension 203b of the second power line 201b is directly electrically connected to the first power lead pattern 202a, and the extension 203a of the first power line is electrically connected to the first power lead pattern 202a through a first via H1 disposed on the first insulating layer 144. As described above, the second metal layer 133 and the third metal layer 134 are both made of a material with a relatively low sheet resistance, and the first power line and the second power line are both connected to the first power lead pattern in this embodiment, which is equivalent to the first power line and the second power line being connected in parallel, so that the resistance of the power lines can be further reduced, and the voltage drop of the power lines can be reduced. And can narrow the width of power cord through parallelly connected mode, can reduce the area in display panel's opaque district, increase display panel's luminousness, be favorable to realizing fingerprint discernment under the screen or camera under the screen.

In another embodiment of the present application, please further refer to fig. 9, fig. 9 is a schematic cross-sectional view of an AA' in another embodiment of the display panel of fig. 1; the display panel of the present embodiment includes the power signal lead region 20 and a second power lead pattern 202b, wherein the second power lead pattern 202b and the first power lead pattern 202a are located in the same film layer; the display panel further includes a second insulating layer 145 positioned at a side of the second power supply lead pattern 202b away from the base substrate 110, a conductive connection layer 40 positioned at a side of the second insulating layer 145 away from the base substrate 110, and a third insulating layer 146 positioned at a side of the conductive connection layer 40 away from the base substrate 110; the display panel further includes a cathode layer 153 on a side of the second power supply lead pattern 202b away from the substrate base plate 110, the cathode layer 153 being electrically connected to the conductive connection layer 40 through a second via H2 disposed on the third insulating layer 146; the conductive connection layer 40 is electrically connected to the second power supply lead pattern 202b through a third via H3 provided in the second insulating layer 145.

The display panel generates a driving current by the pixel driving circuit, and the driving current flows through the light emitting device to make the OLED display panel emit light. The first power voltage VDD transmitted through the first power lead pattern 202a is transmitted to a data voltage signal, which is correspondingly connected to the source of the driving transistor and the gate of the driving transistor, to generate a driving current, which flows from the anode 151 of the light emitting device to the cathode 153 of the light emitting device. And the cathode potential transferred by the second power supply lead pattern 202b is transferred to the cathode of the light emitting device. Therefore, when the entire display panel emits light, all the sub-pixels of the entire display panel generate driving currents, and thus, the first and second power

supply lead patterns

202a and 202b need to withstand the passage of a large current. The first power supply lead pattern 202a and the second power supply lead pattern 202b are disposed on the third metal layer 134, so that resistance can be reduced, and voltage drop can be reduced. And the first power supply lead pattern 202a and the second power supply lead pattern 202b are arranged to overlap with the functional device 300 to form a three-dimensional space structure, and the width of the step region is reduced while the areas of the first power supply lead pattern and the second power supply lead pattern are increased. And the current tolerance capacity can be improved by increasing the areas of the first power supply lead wire pattern and the second power supply lead wire pattern, and the stability of the display panel is improved.

Further, the thickness of the second insulating layer 145 and/or the first insulating layer 144 is equal to 1.5 μm in a third direction, which is a direction perpendicular to the plane of the substrate base plate. The coupling between the signal lines can be reduced, the influence on the operation of the functional device 300 can be avoided, and display abnormality can be avoided.

In another embodiment of the present application, with reference to fig. 9, since the cathode 153 is disposed in the entire display region by an evaporation process, the cathode 153 extends to the step region in the present application, and is connected to the conductive connection layer 40 through the second via H2 and the second power lead pattern 202b through the third via H3, thereby conducting the cathode potential. Further, the conductive connection layer 40 and the anode 151 are disposed on the same layer, and the conductive connection layer 40 covers at least a portion of the first power supply lead pattern 202a and the second power supply lead pattern 202b, which may increase a contact area, reduce contact resistance, and reduce a voltage drop of a cathode potential.

In another embodiment of the present application, please continue to refer to fig. 10, in which fig. 10 is a schematic cross-sectional view of an AA' in yet another embodiment of the display panel of fig. 1; the second power supply lead pattern 202b is located on one side of the first power supply lead pattern 202a away from the display area, and the conductive connection layer 40 is electrically connected with the cathode layer 153 extending from the display area to the step area through the second via hole H2; if the second power lead pattern 202b is disposed on a side of the first power lead pattern 202a close to the display area, the second power lead pattern 202b blocks the connection between the first power lead pattern 202a and the power line 201, so that the second power lead pattern 202b is disposed away from the display area and connected to the cathode 153 through the conductive connection layer 40, and the power line 201 and the cathode 153 are electrically connected.

Furthermore, because the cathode is the evaporation process, and because there is a gap between the evaporation mask plate and the display panel in the evaporation process, the evaporated material can enter the part shielded by the mask plate through the gap. When the boundary of the cathode 153 is too close to the functional device 300, the cathode 153 may be evaporated to the bound terminal located at the side of the functional device 300 close to the cut edge, thereby short-circuiting the bound terminal, and thus, the present embodiment provides that the cathode 153 does not overlap the second power lead pattern 202 b. Therefore, the edge of the cathode 153 can be far away from the binding terminal, and the binding terminal is prevented from being short-circuited during cathode evaporation.

Further, referring to fig. 11 and 12, fig. 11 is a schematic partial enlarged view of a step area in the display panel of fig. 1; fig. 12 is a schematic cross-sectional view of the display panel BB' of fig. 11; the display panel further comprises frame areas NA located on the left side and the right side of the display area AA, and the frame areas NA are adjacent to the step areas and extend along the second direction. The second power lead pattern 202b is located on one side of the first power lead pattern 202a close to the frame region and extends from the step region to the frame region, the conductive connection layer 40 is electrically connected to the cathode layer 153 extending from the display region to the frame region through the second via H2, and the frame region NA is located on the periphery of the display region and disposed on two sides of the display region AA along the second direction. The embodiment can transmit the cathode potential to the middle of the display panel from the periphery of the display panel, reduce the voltage drop of the cathode potential and improve the display uniformity of the display panel. Further, the second power lead pattern 202b may overlap the gate driving circuit VSR, so as to reduce the width of the frame area NA and meet the requirement of a narrow frame.

An embodiment of the present invention further provides a display device, as shown in fig. 13, fig. 13 is a schematic structural diagram of the display device provided in the embodiment of the present invention, and the display device includes the display panel. The specific structure included in the display panel has been described in detail in the above embodiments, and is not described herein again. Of course, the display module shown in fig. 13 is only a schematic illustration, and the display module may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.

According to the light-emitting display panel and the display device provided by the embodiment of the invention, the first insulating layer is arranged between the first power supply lead pattern and the functional device, and the first power supply lead pattern and the functional device form a vertically stacked three-dimensional space structure, so that the width of a step area is reduced while respective functions are realized, and the specification requirement of a limit narrow step is met.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A display panel is characterized in that the display panel is provided with a display area and a step area positioned outside the display area;

the display panel comprises a substrate base plate and a plurality of power lines which are arranged on the substrate base plate and positioned in the display area along a first direction and extend along a second direction, wherein the first direction is vertical to the second direction;

a functional device area comprising a plurality of functional devices and a power signal lead area comprising a first power lead pattern extending along the first direction are arranged on the substrate base plate and positioned in the step area, the functional device area comprises a gating circuit area, and the gating circuit area extends along the first direction;

a first insulating layer is arranged between the film layer of the first power supply lead pattern and all the film layers adopted by the functional device at intervals;

in the direction perpendicular to the plane of the display panel, at least partial overlap exists between the first power supply lead pattern and the orthographic projection of the gating circuit area on the plane of the substrate base plate;

the functional device area further comprises an ESD circuit area extending along the first direction, and the orthographic projection of the first power supply lead pattern and the ESD circuit area on the plane of the substrate base plate is not overlapped;

the functional device area comprises a first metal layer, a second metal layer and a third metal layer which are arranged in a stacking mode from the position close to the substrate to the position far away from the substrate, the first metal layer is used as a grid electrode of a transistor in the functional device area, the second metal layer is used as a source drain electrode of the transistor in the functional device area, the first insulating layer is arranged on one side, far away from the substrate, of the second metal layer, the third metal layer is located on one side, far away from the substrate, of the first insulating layer, and the third metal layer is a film layer adopted by the first power supply lead pattern;

the film layer adopted by the power line is the second metal layer, the extension line of the power line is positioned in the step area, and the extension line of the power line is electrically connected with the first power supply lead pattern through a first via hole arranged in the first insulating layer; or,

the film layer adopted by the power line is the third metal layer, the extension line of the power line is positioned in the step area, and the extension line of the power line is directly electrically connected with the first power supply lead pattern; or,

the power cord includes first power cord and second power cord, the rete that first power cord adopted does the second metal level, the rete that second power cord adopted does the third metal level, the extension line of second power cord is located the step district, the extension line of second power cord direct with first power lead wire figure electricity is connected, the extension line of first power cord through set up in the first via hole on first insulation layer with first power lead wire figure electricity is connected.

2. The display panel according to claim 1, wherein the power supply signal lead area at least partially overlaps with an orthographic projection of the functional device area on a plane of the substrate base plate.

3. The display panel according to claim 2, wherein an overlapping area of the power supply signal lead region and the functional device region is greater than or equal to 50% of an area of the functional device region.

4. The display panel according to claim 1, wherein each of the power lines is electrically connected to the first power supply lead pattern through a first connection line.

5. The display panel of claim 1, wherein the functional device region further comprises a shorting circuit region.

6. The display panel according to claim 5, wherein the power supply signal lead region overlaps with an orthogonal projection of any one of the gate circuit region, the short circuit region, and the ESD circuit region on a plane of the substrate base; or,

the power supply signal lead area and any two of the gating circuit area, the short circuit area and the ESD circuit area are overlapped in the orthographic projection of the plane of the substrate base plate; or,

and the orthographic projections of the power supply signal lead area, the gating circuit area, the short circuit area and the ESD circuit area on the plane of the substrate base plate are overlapped.

7. The display panel according to claim 1, wherein the power signal lead region further comprises a second power lead pattern located in the same film layer as the first power lead pattern;

the display panel further comprises a second insulating layer positioned on one side, far away from the substrate, of the second power supply lead pattern, a conductive connecting layer positioned on one side, far away from the substrate, of the second insulating layer, and a third insulating layer positioned on one side, far away from the substrate, of the conductive connecting layer;

the display panel further comprises a cathode layer positioned on one side, far away from the substrate, of the second power supply lead pattern, and the cathode layer is electrically connected with the conductive connecting layer through a second through hole arranged in the third insulating layer;

the conductive connecting layer is electrically connected with the second power supply lead pattern through a third via hole arranged in the second insulating layer.

8. The display panel according to claim 7, wherein the second power supply lead pattern is located on a side of the first power supply lead pattern away from the display region, and the conductive connection layer is electrically connected to the cathode layer extending from the display region to the step region through the second via hole; or,

the second power supply lead pattern is located on one side, close to the frame area, of the first power supply lead pattern and extends from the step area to the frame area, the conductive connecting layer is electrically connected with the cathode layer extending from the display area to the frame area through the second through hole, and the frame area is located on the periphery of the display area and arranged along the second direction.

9. The display panel according to claim 7, wherein a thickness of the first insulating layer in a third direction is greater than or equal to 1.5 μm, and wherein the third direction is a direction perpendicular to a plane of the substrate base plate.

10. The display panel according to claim 7, wherein a thickness of the second insulating layer in a third direction is greater than or equal to 1.5 μm, and wherein the third direction is a direction perpendicular to a plane of the substrate base plate.

11. A display device comprising the display panel according to any one of claims 1 to 10.