CN114639328A

CN114639328A - Display panel and display device

Info

Publication number: CN114639328A
Application number: CN202210280898.7A
Authority: CN
Inventors: 马宏伟; 尚庭华; 李波; 齐琦; 杨慧娟; 周洋; 刘彪
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2022-03-21
Filing date: 2022-03-21
Publication date: 2022-06-17

Abstract

The utility model provides a display panel and display device, belongs to and shows technical field. The display panel comprises a substrate with a first display area and a second display area and a plurality of first pixels, wherein the first pixels comprise pixel circuits and light-emitting elements which are respectively positioned in the first display area and the second display area, and the pixel circuits and the light-emitting elements are connected through transparent wires. And the pixel circuits included in only one column of the first pixels in at least two adjacent columns of the first pixels are connected with the test circuit. Therefore, the test circuit can reliably detect whether the transparent conducting wires connected with the pixel circuits in the first pixels of the two adjacent columns are short-circuited or not by collecting the pixel charge quantity at the connecting nodes of the pixel circuits and the light-emitting elements, and the problem that the two transparent conducting wires cannot be detected to be short-circuited in the related technology is solved.

Description

Display panel and display device

Technical Field

The present disclosure relates to display technologies, and particularly to a display panel and a display device.

Background

The method is characterized in that hardware structures like a photosensitive sensor or an acoustic sensor are hidden below a screen of the display device, so that the method becomes a brand new technology for improving the screen occupation ratio of the display device at present.

In the related art, a display panel in a display device in which a hardware structure is hidden generally includes: a substrate, and a pixel circuit and a light emitting element over the substrate. The substrate has a first display region for normal display and a second display region for setting a hardware structure, the pixel circuit is located in the first display region, and the light emitting element is located in the first display region and the second display region. The pixel circuit is connected with the light-emitting element to drive the light-emitting element to emit light.

Disclosure of Invention

The application provides a display panel and display device can solve the problem that can't detect the short circuit that takes place between the adjacent transparent conductor among the correlation technique, technical scheme is as follows:

in one aspect, there is provided a display panel including:

a substrate having a first display area and a second display area, the first display area at least partially surrounding the second display area;

a plurality of data lines positioned in the first display area;

a plurality of transparent wires positioned in the first display area and the second display area;

the first pixel circuit is connected with the data line, is also connected with the first light-emitting element through the transparent conducting wire, and is used for driving the first light-emitting element to emit light based on a signal provided by the data line;

the first pixel circuits in the same column are connected with the same data line, and in at least two adjacent columns of the first pixel circuits, the first pixel circuits in one column are also connected with the test circuit through the data line, and the first pixel circuits in the other column are not connected with the test circuit.

Optionally, at least two transparent wires of the plurality of transparent wires are located at different layers, and at least two transparent wires are located at the same layer;

the transparent conducting wire connected with the first pixel circuit in one column and the transparent conducting wire connected with the first pixel circuit in the other column are positioned on the same layer.

Optionally, the plurality of first pixels include first pixels of at least two colors;

the first pixels including the first pixel circuits of the one column are the same color as the first pixels including the first pixel circuits of the other column.

Optionally, for a plurality of first pixels of the same color, in the first pixel circuits included in every two adjacent columns of the first pixels, the first pixel circuit in one column is connected to the test circuit through the data line, and the first pixel circuit in the other column is not connected to the test circuit.

Optionally, for a plurality of first pixels of the same color, the first pixel circuits in the first pixels in the odd-numbered columns are connected to the test circuit through the data lines, and the first pixel circuits in the first pixels in the even-numbered columns are not connected to the test circuit.

Optionally, the plurality of first pixels include: a plurality of green first pixels, a plurality of red first pixels, and a plurality of blue first pixels;

the plurality of transparent conductive lines includes: the first transparent wires, the second transparent wires and the third transparent wires are respectively positioned on different layers;

in the green first pixel, a first pixel circuit is connected with a first light-emitting element through the first transparent conducting wire;

in the red first pixel, a first pixel circuit is connected with a first light-emitting element through the second transparent conducting wire;

in the blue first pixel, the first pixel circuit is connected with the first light-emitting element through the third transparent wire.

Optionally, the first pixel circuit in the green first pixel is close to the second display region relative to the first pixel circuit in the red first pixel, and is close to the second display region relative to the first pixel circuit in the blue first pixel.

Optionally, the plurality of first pixels are sequentially arranged according to a red first pixel, a green first pixel, a blue first pixel and a green first pixel.

Optionally, the substrate further has a non-display area, the non-display area at least partially surrounding the first display area; the display panel further includes:

the pixel circuit comprises a plurality of test probes positioned in the non-display area, the first pixel circuits in a column are connected with the test probes through data lines, and the test probes are used for being connected with test pins in the test circuits.

Optionally, the first light emitting element includes: an anode and a cathode;

wherein the first pixel circuit is connected to the anode and is configured to transmit a light emission driving signal to the anode, the cathode is connected to a common power source terminal, and the first light emitting element is configured to emit light based on the light emission driving signal and a power source signal supplied from the common power source terminal.

Optionally, the second display area is a light-transmitting display area.

Optionally, the display panel further includes:

and the second pixel circuits are respectively connected with the data lines and the second light-emitting elements and are used for driving the second light-emitting elements to emit light based on data signals provided by the data lines.

In another aspect, there is provided a display device including: a photosensor, and the display panel as described in the above aspect;

wherein the photosensitive sensor is located in a second display area of the display panel.

To sum up, the beneficial effects brought by the technical scheme provided by the embodiment of the application at least can include:

a display panel and a display device are provided. The display panel comprises a substrate with a first display area and a second display area and a plurality of first pixels, wherein the first pixels comprise pixel circuits and light-emitting elements which are respectively positioned in the first display area and the second display area, and the pixel circuits and the light-emitting elements are connected through transparent wires. And the pixel circuits included in only one column of the first pixels in at least two adjacent columns of the first pixels are connected with the test circuit. Therefore, the test circuit can reliably detect whether the transparent conducting wire connected with the pixel circuit in the first pixels of the two adjacent columns is short-circuited or not by collecting the pixel charge quantity at the connection node of the pixel circuit and the light-emitting element, and the problem that two transparent conducting wires cannot be detected to be short-circuited in the related technology is solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic partial structure diagram of a display panel according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of another display panel provided in the embodiment of the present application;

FIG. 5 is a layout of the structure in the second display area in the structure shown in FIG. 4;

fig. 6 is a film structure diagram of a transparent conductive line provided in an embodiment of the present application;

fig. 7 is a partial structural layout of a display panel according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a second pixel according to an embodiment of the present disclosure;

fig. 9 is a circuit structure diagram of a first pixel according to an embodiment of the present application;

fig. 10 is a circuit configuration diagram of a first pixel at one stage according to an embodiment of the present application;

fig. 11 is a circuit configuration diagram of a first pixel at another stage according to an embodiment of the present application;

fig. 12 is a circuit configuration diagram including two first pixels according to an embodiment of the present application;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clear, the following detailed description of the embodiments of the present application will be made with reference to the accompanying drawings.

With the progress of display technology and the increase of the demand of consumers for screen occupation, the development of display panels in display devices (e.g., mobile phones) to truly full-screen display is more and more urgent. To achieve a true full-screen design, a series of display panels with opaque regular display areas and transparent display areas have been developed. In this type of display panel, some hardware structures can be arranged in the light-transmitting display area, so that holes do not need to be dug on the screen of the display panel. For example, the hardware structure typically includes an acoustic sensor or a light-sensitive sensor (e.g., a camera). Taking a hardware structure as an example of a camera, in this type of display panel, the camera may be considered to be hidden under a screen, and the transparent display area may also be referred to as an under-screen camera (FDC) area.

Further, on the basis of this arrangement, in order to ensure a good light transmittance of the light-transmissive display region, a plurality of pixel circuits for driving the plurality of light-emitting elements in the light-transmissive display region to emit light are generally arranged in the normal display region, and the plurality of pixel circuits are connected to the plurality of light-emitting elements in the light-transmissive display region through transparent wires. However, because the transparent wires have good light transmittance, when two adjacent transparent wires are short-circuited, the short-circuited transparent wires cannot be detected by the current AOI photographing mode. In addition, in the test stage, a monochrome screen lighting test is generally performed on a display panel (cell), which also causes a problem that a transparent wire connected to a pixel circuit in a pixel of the same color is short-circuited. Ultimately resulting in a low yield of the display device.

The embodiment of the application provides a display panel, and the short circuit problem that appears between two adjacent transparent conducting wires in the display panel can be reliably detected, so that the good yield of the display device is ensured.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application. As shown in fig. 1, the display panel includes:

a substrate 01, the substrate 01 having a first display area a1 and a second display area a2, the first display area a1 at least partially surrounding the second display area a 2. For example, fig. 1 shows the second display area a2 located at the top right middle position of the substrate 01 and having a circular shape. The first display area a1 has a rectangular shape. Also, each side of the first display area a1 having a rectangular shape surrounds the second display area a2, i.e., the second display area a2 is surrounded by the first display area a 1.

Of course, in some other embodiments, the second display area a2 may not be located at the top center of the substrate 01 shown in fig. 1, but may be located at other positions. For example, in connection with fig. 1, the second display area a2 may be located at an upper left corner position or an upper right corner position of the substrate 01. The embodiment of the present application does not limit this.

Also, in the embodiment of the present application, the first display region a1 may be provided as a non-transmissive display region, i.e., a normal display region, and the second display region a2 may be provided as a transmissive display region. That is, the first display region a1 described in the embodiment of the present application is opaque, and the second display region a2 is transparent. Thus, as described in the above embodiments, the required hardware structures such as the camera can be directly disposed in the second display area a2 without digging a hole on the display panel, and a solid foundation is laid for realizing a true full screen without affecting normal display. On this basis, the second display area a2 described in the embodiments of the present application may be referred to as an FDC area.

It should be noted that the area of the first display area a1 is generally much larger than that of the second display area a2, and fig. 1 is only a schematic illustration of the positional relationship and does not limit the area of each display area.

With continued reference to fig. 1, the display panel further includes: a plurality of Data lines Data located in the first display area a1, a plurality of transparent conductive lines L1 located in the first display area a1 and the second display area a2, and a plurality of first pixels 02 arranged in an array. The array arrangement may refer to: the plurality of first pixels 02 are arranged in rows and columns, i.e. the display panel comprises a plurality of rows and a plurality of columns of the first pixels 02.

The first pixel 02 includes a first pixel circuit 021 in the first display area a1 and a first light-emitting element 022 in the second display area a2, and the first pixel circuit 021 is connected to a Data line Data and is also connected to the first light-emitting element 022 through a transparent wire L1, and is configured to drive the first light-emitting element 022 to emit light based on a signal (which may be referred to as a Data signal) supplied from the Data line Data. For example, the first pixel circuit 021 may transmit a driving current to the first light-emitting element 022 to drive the first light-emitting element 022 to emit light.

Note that each of the first pixels 02 may include the first pixel circuit 021 and the first light-emitting element 022, or at least part of the first pixels 02 includes the first pixel circuit 021 and the first light-emitting element 022 in the plurality of first pixels 02. The embodiment of the present application is described taking as an example that each of the first pixels 02 includes a first pixel circuit 021 and a first light emitting element 022.

The first pixel circuit 021 included in the first pixel 02 is disposed in the first display area a1, and the first pixel circuit 021 and the first light-emitting element 022 are connected by the transparent wire L1, so that the light-transmitting effect of the second display area a2 can be ensured to be good, that is, the light transmittance is high.

In the embodiment of the present application, the first pixel circuits 021 in the same column may be connected to the same Data line Data, and the first pixel circuits 021 in different columns may be connected to different Data lines Data. That is, the plurality of columns of the first pixel circuits 021 and the plurality of Data lines Data may be connected in a one-to-one correspondence.

On the basis, referring to fig. 2, the display panel includes a plurality of rows of first pixel circuits 021, at least two adjacent rows of first pixel circuits 021, one row of first pixel circuits 021 is further connected to a test circuit (which may also be referred to as a test device) through a Data line Data, and the other row of first pixel circuits 021 is not connected to the test circuit. That is, in the first pixel circuits 021 of at least two adjacent columns described in the embodiment of the present application, only one column of the first pixel circuits 021 may be connected to the test circuit, so that the test circuit can reliably detect whether the transparent conductive line L1 connected to the first pixel circuit 021 of one column is short-circuited with the transparent conductive line L1 connected to the first pixel circuit 021 of the other column.

For example, the test circuit may be an Array Test (AT) circuit, and a plurality of test pins (pins), abbreviated as AT pins, may be disposed in the AT circuit. Referring to fig. 2, the first pixel circuit 021 described in this embodiment of the present application may be connected to the AT Pin through the Data line Data, and the AT Pin connected to different first pixel circuits 021 is different. Fig. 2 shows the four rows of the first pixel circuits 021 in total, from left to right, in the adjacent first row of the first pixel circuits 021 and the second row of the first pixel circuits 021, only the Data line Data connected to the second row of the first pixel circuits 021 is connected to the AT Pin. And, in the adjacent third and fourth columns of the first pixel circuits 021, only the Data line Data connected to the fourth column of the first pixel circuit 021 is connected to the AT Pin. Accordingly, for the adjacent second column first pixel circuit 021 and third column first pixel circuit 021, it can be considered that only the Data line Data to which the second column first pixel circuit 021 is connected is also connected to the AT Pin.

With reference to fig. 1 and 2, if the transparent conductive line L1 connected to the first pixel circuit 021 in one row is shorted with the transparent conductive line L1 connected to the first pixel circuit 021 in another row, the short circuit problem shown in fig. 2 occurs between the connection node N0 of the first pixel circuit 021 and the first light emitting element 022 in the one row and the connection node N0 of the first pixel circuit 021 and the first light emitting element 022 in the other row. Further, the amount of the pixel charge at the connection node N0 changes. Based on this, the test circuit can collect the pixel charge amount at the connection node N0 through the connected Data line Data, and detect whether the transparent wire L1 connected to the first pixel circuit 021 in one column is short-circuited with the transparent wire L1 connected to the first pixel circuit 021 in another column based on the pixel charge amount. Alternatively, the first light emitting element 022 may include an Anode (Anode) and a Cathode (Cathode), the first pixel circuit 021 may be connected to the Anode, and accordingly, the connection node N0 may refer to a pixel Anode node.

In addition, if the first pixel circuits 021 in two adjacent columns are connected to the test circuit through the Data lines Data, when the transparent conductive line L1 connected to the first pixel circuits 021 in the two adjacent columns is short-circuited, the pixel charge amount at the connection node N0 between the first pixel circuit 021 in each column and the first light emitting element 022 is fed back to the test circuit through the Data lines Data, that is, the test circuit obtains the pixel charge amount at the connection node N0 between the first pixel circuit 021 in the two adjacent columns and the first light emitting element 022 in the first pixel circuit 021 in each column. Thus, the pixel charge amount of the connection node N0 which is collected by the test circuit and short-circuited is not obviously different from or even has no difference from the pixel charge amount of the connection node N0 which is not short-circuited normally. Further, the short circuit of the transparent conductive line L1 still cannot be reliably detected.

In the embodiment of the present application, only one of the two adjacent columns of the first pixel circuits 021 is connected to the test circuit through the Data line Data, so that when the transparent conductive line L1 connected to the two columns of the first pixel circuits 021 is short-circuited, the pixel charge amount at the connection node N0 of the first pixel circuit 021 and the first light emitting element 022, which is not connected to the test circuit, is not transmitted to the test circuit through the Data line Data connected thereto, but is short-circuited through the Data line Data connected thereto, and the first pixel circuit 021 connected to the test circuit is fed back to the test circuit through the Data line Data connected thereto. At this time, the pixel charge amount of the connection node N0 at the short circuit position detected by the test circuit is obviously larger than the pixel charge amount of the connection node N0 at which the short circuit does not occur normally, so that the problem of the short circuit between the transparent wires L1 can be reliably detected.

In summary, the present embodiment provides a display panel, which includes a substrate having a first display region and a second display region, and a plurality of first pixels, where a pixel circuit and a light emitting element included in each of the first pixels are respectively located in the first display region and the second display region, and the pixel circuit and the light emitting element are connected by a transparent wire. And the pixel circuits included in only one column of the first pixels in at least two adjacent columns of the first pixels are connected with the test circuit. Therefore, the test circuit can reliably detect whether the transparent conducting wires connected with the pixel circuits in the first pixels of the two adjacent columns are short-circuited or not by collecting the pixel charge quantity at the connecting nodes of the pixel circuits and the light-emitting elements, and the problem that the two transparent conducting wires cannot be detected to be short-circuited in the related technology is solved.

In addition, only one row of first pixel circuits is connected with the test circuit in at least two adjacent rows of first pixel circuits, so that the difference between the pixel charge quantity of the short-circuited connection node collected by the test circuit and the pixel charge quantity of the short-circuited connection node is obvious, and the test circuit can be further ensured to reliably detect whether the two transparent conducting wires are short-circuited or not.

Alternatively, as described in the above embodiments, the second display region a2 may be a light-transmitting display region. The second display area a2 may also be referred to as an FDC area on the basis of the camera being disposed in the second display area a 2.

Optionally, in the embodiment of the present application, the material of the transparent conductive line L1 may include: indium Tin Oxide (ITO) material. Accordingly, the transparent conductive line L1 may also be referred to as an ITO trace. The following embodiments are all described by taking the transparent conductive line L1 as an example of an ITO trace. Of course, in some other embodiments, the material of the transparent conductive line L1 may also be other transparent materials, for example, Indium Gallium Zinc Oxide (IGZO), which is not limited in this embodiment.

Alternatively, referring to another display panel shown in fig. 3, the substrate 01 described in this embodiment may further have a non-display region B1, and the non-display region B1 may at least partially surround the first display region a 1.

For example, in the display panel shown in fig. 3, the non-display region B1 included in the substrate 01 is located directly above the substrate 01 and is adjacent to the first display region a 1. That is, only one side of the first display area a1 is surrounded by the non-display area B1. Of course, in some other embodiments, the non-display area B1 may not be located directly above the substrate 01 shown in fig. 1, but may be located in other positions. For example, in conjunction with fig. 3, the non-display region B1 may be located at a position directly below the substrate 01 and adjacent to the first display region a 1. The embodiment of the present application does not limit this.

On this basis, as can be seen with continued reference to fig. 3, the display panel may further include: a plurality of test probes (Pad) located in the non-display region B1, a column of the first pixel circuits 021 can be connected to the test probes Pad through the Data lines Data, and the test probes Pad are used to connect to the test pins AT Pin in the test circuit AT. That is, the Data line Data to which the first pixel circuit 021 is connected may be indirectly connected to the test circuit through the test probe Pad located on the display panel. Accordingly, the pixel charge amount may be fed back to the test circuit through the Data line Data via the test probe Pad.

Optionally, in the plurality of transparent conductive lines L1 described in the embodiment of the present application, at least two transparent conductive lines L1 may be located in different layers, and at least two transparent conductive lines L1 may be located in the same layer. That is, there is at least a portion of the transparent conductive line L1 located at the same layer, and at least another portion of the transparent conductive line L1 located at a different layer.

On this basis, the transparent conductive line L1 connected to the first pixel circuits 021 in one row and the transparent conductive line L1 connected to the first pixel circuits 021 in another row can be located in the same layer. That is, in the embodiment of the present application, the connected transparent conductive line L1 may be located on the same layer, and in the two adjacent columns of the first pixel circuits 021, only one column of the first pixel circuits 021 may be connected to the test probe Pad through the Data line Data. Accordingly, the test circuit may detect whether a short circuit occurs between two adjacent transparent conductive lines L1 located on the same layer. The arrangement ensures the detection reliability because the probability of short circuit between two adjacent transparent conducting wires L1 in the same layer is high.

For example, referring to another display panel shown in fig. 4 and, based on fig. 4, a structural layout in a second display area a2 shown in fig. 5, a plurality of transparent conductive lines L1 described in the embodiments of the present application may include: a plurality of first transparent conductive lines L1 (labeled ITO1 in the figure), a plurality of second transparent conductive lines L1 (labeled ITO2 in the figure), and a plurality of third transparent conductive lines L1 (labeled ITO3 in the figure) in the same layer, wherein the first transparent conductive lines L1, the second transparent conductive lines L1, and the third transparent conductive lines L1 are respectively positioned in different layers. I.e. may comprise three types of transparent conductors at different layers. On this basis, the transparent conductive line L1 connected to the first pixel circuit 021 in one column and the transparent conductive line L1 connected to the first pixel circuit 021 in the other column may be two first transparent conductive lines L1 (i.e., ITO1) located on the same layer, and as described in the above embodiments, the two first transparent conductive lines L1 located on the same layer are adjacent to each other.

Optionally, fig. 6 shows a film layer structure diagram including ITO1 traces, ITO2 traces, and ITO3 traces. Referring to fig. 6, it can be seen that ITO3 trace, ITO2 trace, and ITO1 trace are stacked in sequence in a direction away from the substrate 01. And, an insulating layer (not shown) is further included between each two adjacent transparent wires to insulate the two adjacent transparent wires, so as to avoid signal crosstalk. In addition, fig. 6 also shows the connection of ITO1 traces to the Anode.

Wherein, being located at the same layer may mean: and forming a film layer for forming a specific pattern by using the same film forming process, and patterning the film layer by using the same mask plate through a one-time composition process to form a layer structure. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or portions located at the "same layer" are made of the same material and are formed through the same patterning process. As such, manufacturing processes and manufacturing costs may be saved, and manufacturing efficiency may be accelerated. In the embodiment of the present application, the transparent conductive lines on the same layer refer to transparent conductive lines formed on the same layer at one time by using the same material.

Alternatively, in the embodiment of the present application, the plurality of first pixels 02 may include first pixels 02 of at least two colors. That is, the display panel may include a plurality of colors of the plurality of first pixels 02. On this basis, the color of the first pixel 02 including one row of the first pixel circuits 021 can be the same as that of the first pixel 02 including the other row of the first pixel circuits 021. That is, in the embodiment of the present application, the first pixel circuits 021 included in only one column of the first pixels 02, which may be two columns of the first pixels 02 of the same color, are connected to the test probes Pad through the Data lines Data. Here, for the first pixels 02 of the same color, the transparent conductive lines L1 connected to the first pixel circuits 021 included in the first pixels 02 of two adjacent columns are usually located in the same layer. Furthermore, in the embodiment of the present application, the first pixel circuits 021 of two columns that are adjacent to each other and connected with the transparent conducting wire L1 are located in the same layer, and only one column of the first pixel circuits 021 is connected with the test probe Pad through the Data line Data.

For example, as can be seen from fig. 4 and 5, the plurality of first pixels 02 described in the embodiment of the present application may include: a plurality of Green (Green, G) first pixels 02, a plurality of Red (Red, R) first pixels 02 and a plurality of Blue (Blue, B) first pixels 02. That is, the display panel may include a plurality of first pixels 02 of three colors of red R, green G, and blue B. Fig. 5 shows the anode of the first light emitting element 022. Of course, in some other embodiments, the first pixel 02 may also be included, such as white (W).

In the first pixel 02 of green G, the first pixel circuit 021 can be connected to the first light-emitting element 022 through a first transparent wire L1 (i.e., an ITO1 trace). In the first pixel 02 of red R, the first pixel circuit 021 may be connected to the first light emitting element 022 through a second transparent wire L1 (i.e., an ITO2 trace). In the first pixel 02 of blue B, the first pixel circuit 021 may be connected to the first light emitting element 022 through a third transparent wire L1 (i.e., an ITO3 trace). Of course, in some other embodiments, for each color of the first pixels 021, a portion of the first pixels 02 are connected to the first light emitting element 022 through ITO1 traces, and another portion of the first pixels 02 are connected to the first light emitting element 022 through ITO2 traces and/or ITO3 traces. The embodiment of the present application does not limit this.

It should be noted that, since the phosphor efficiency of the first pixel 02 of green G is highest relative to the phosphor efficiency of the first pixels 02 of other colors (e.g., the first pixel 02 of red R and the first pixel 02 of blue B), the light-emitting current required to be applied to the first pixel 02 of green G is generally the smallest at the same gray level (particularly, at a low gray level). Since the parasitic capacitance Cp1 at the pixel anode node N0 of each first pixel 02 is positively correlated with the length of the connected transparent wire L1, and the larger the parasitic capacitance Cp1 is, the longer the charging time required before the first pixel 02 is turned on is, so if the parasitic capacitance Cp1 at the pixel anode node N0 of the first pixel 02 of green G is larger, the turn-on speed of the first pixel 02 of green G is obviously lower than the turn-on speed of the first pixels 02 of other colors, and finally the color coordinates of the display screen in the second display area a2 (i.e., FDC) are abnormal, and the display effect is poor.

Therefore, when wiring (herein, specifically, ITO routing) is performed, the first light emitting element 022 in the first pixel 02 of green G is preferentially connected to the first pixel circuit 021 closest to the second display area a2, so as to ensure that the ITO routing (i.e., the ITO1 routing shown in the figure) connected to the first pixel circuit 021 in the first pixel 02 of green G is shortest, so that the parasitic capacitance Cp1 at the pixel anode node N0 in the first pixel 02 of green G is smaller, and color coordinate abnormality is avoided. That is, as shown in fig. 4, in the embodiment of the present application, the first pixel circuit 021 in the first pixel 02 of green G is close to the second display region a2 with respect to the first pixel circuit 021 in the first pixel 02 of red R, and is close to the second display region a2 with respect to the first pixel circuit 021 in the first pixel 02 of blue B. At this time, in the first pixel 02 of green G, the ITO1 traces connected to each two adjacent first pixel circuits 021 are located on the same layer, and there is a risk of short circuit in the process. If the short-circuit failure cannot be detected timely and reliably, the yield of the display device that is finally delivered is poor. The embodiment of the application detects the pixel charge amount by adopting the test circuit, so that the problem of poor short circuit can be timely and reliably detected, and the good delivery yield of the display device is ensured.

Alternatively, referring to fig. 4, it can be seen that, along the pixel row direction, a plurality of first pixels 02 may be sequentially arranged in a manner that one first pixel 02 of red R, one first pixel 02 of green G, one first pixel 02 of blue B, and one first pixel 02 of green G are sequentially arranged. Of course, in some other embodiments, the plurality of first pixels 02 of different colors may be arranged in other manners, such as arranging the first pixel 02 of one red R, the first pixel 02 of one green G, and the first pixel 02 of one blue B in sequence. The arrangement of the first pixels 02 is not limited in this embodiment. In conjunction with fig. 4, the following means: the arrangement of the first light emitting element 022 (e.g., the Anode electrode shown in fig. 5) of the first pixel 02 in the second display region a 2.

Alternatively, for a plurality of first pixels 02 of the same color, in the first pixel circuits 021 included in every two adjacent columns of the first pixels 02, the first pixel circuit 021 in one column may be connected to the test circuit through the Data line Data, and the first pixel circuit 021 in the other column may not be connected to the test circuit. That is, in the embodiment of the present application, in any two adjacent columns of the first pixels 02 with the same color, the first pixel circuit 021 included in only one column of the first pixels 02 is connected to the test circuit.

For example, taking the structures shown in fig. 3 and 4 as examples, fig. 7 shows an equivalent structure diagram of a display panel. Referring to fig. 7, it can be seen that, for a plurality of first pixels 02 of the same color, the first pixel circuits 021 in the first pixels 02 in the odd columns are connected to the test circuit through the Data lines Data, and the first pixel circuits 021 in the first pixels 02 in the even columns are not connected to the test circuit. For example, referring to fig. 7, among the plurality of first pixels 02 of green G, from left to right, the first column of first pixels 02, the third column of first pixels 02, the fifth column of first pixels 02, and the seventh column of first pixels 02 are respectively connected to the test probe Pad. The same applies to the first pixels 02 of other colors, and details thereof are not repeated herein. The respective test probes Pad shown in fig. 7 are sequentially arranged in the pixel row direction, and fig. 7 numbers the test probes Pad at different positions, which are 1 to 10, respectively.

Of course, in some embodiments, the first pixel circuit 021 in the first pixel 02 in the even column can be connected to the test circuit through the Data line Data, and the first pixel circuit 021 in the first pixel 02 in the odd column can be not connected to the test circuit. The embodiment of the present application does not limit this.

Optionally, as can be seen with continued reference to fig. 4, the display panel described in the embodiment of the present application may further include: a plurality of second pixels 03. As can be seen from fig. 8, the second pixel 03 may include a second pixel circuit 031 and a second light-emitting element 032 located in the first display region a1, where the second pixel circuit 031 is respectively connected to the Data line Data and the second light-emitting element 032, and can be used to drive the second light-emitting element 032 to emit light based on the Data signal provided by the Data line Data. As shown in fig. 4, the second pixel 03 may also include a second pixel 03 of green G, a second pixel 03 of red R, and a second pixel 03 of blue B, which are arranged in the same manner as the first pixel 02, and thus, the description thereof is omitted.

It should be noted that each of the second pixels 03 may include a second pixel circuit 031 and a second light-emitting element 032, or at least some of the second pixels 03 include a second pixel circuit 031 and a second light-emitting element 032. In the embodiment of the present application, each of the second pixels 03 includes a second pixel circuit 031 and a second light-emitting element 032.

Alternatively, referring to fig. 4, the second pixel 03 in the same column as the first pixel 02 may be connected to the same Data line Data. Also, the first pixel 02 and the second pixel 03 in the same column may share the same Data line Data. And, each adjacent two columns of the first pixel circuits 021 may include a plurality of rows and a plurality of columns of the second pixels 03, that is, each column of the first pixel circuits 021 may be interspersed among the plurality of second pixels 03. The first pixel circuit 021 and the first light emitting element 022 are sequentially arranged in a pixel row direction. Note that, since the first pixel circuit 021 in the first display region a1 is not connected to the light emitting element in the first display region a1, the first pixel circuit 021 may be referred to as a dummy (dummy) pixel circuit.

Alternatively, fig. 9 shows a circuit configuration diagram of the first pixel. As shown in fig. 9, in the first pixel 02, the first pixel circuit 021 may include: seven transistors T1 to T7, and one capacitor C0.

Wherein one end of the capacitor C0 may be connected to the charging power source terminal ELVDD, and the other end may be connected to the first node N1. The capacitor C0 may be used to store the potential at the first node N1 based on the power supply signal provided from the charging power supply terminal ELVDD.

A Gate of the first transistor T1 may be connected to the first Gate signal terminal Gate1, a first pole of the first transistor T1 may be connected to the first node N1, and a second pole of the first transistor T1 may be connected to the second node N2. When the potential of the first Gate driving signal provided by the first Gate signal terminal Gate1 is the active potential, the first transistor T1 may be turned on. At this time, the first node N1 and the second node N2 are communicated, and accordingly, the potential of the first node N1 and the potential of the second node N2 may affect each other. And, when the potential of the first gate driving signal is the inactive potential, the first transistor T1 may be turned off. That is, the first transistor T1 may be used to adjust the potentials of the first node N1 and the second node N2 in response to the first gate driving signal. The first transistor T1 may also be referred to as a compensation transistor.

A gate of the second transistor T2 may be connected to the first Reset signal terminal Reset1, a first pole of the second transistor T2 may be connected to the initial power source terminal Vinit, and a second pole of the second transistor T2 may be connected to the first node N1. The second transistor T2 may be turned on when the potential of the first Reset signal supplied from the first Reset signal terminal Reset1 is an active potential, and the initialization power source terminal Vinit may transmit an initialization power source signal to the first node N1. And, when the potential of the first reset signal is the inactive potential, the second transistor T2 may be turned off. That is, the second transistor T2 may be used to control the initialization power source terminal Vinit to transmit an initialization power source signal to the first node N1 in response to the first reset signal to reset the first node N1. The second transistor T2 may also be referred to as a reset transistor.

A gate of the seventh transistor T7 may be connected to the second Reset signal terminal Reset2, first poles of the seventh transistors T7 may each be connected to the initial power source terminal Vinit, and a second pole of the seventh transistor T7 may be connected to an anode of the first light emitting element 022 (i.e., the pixel anode node N0). The seventh transistor T7 may be turned on when the potential of the second Reset signal supplied from the second Reset signal terminal Reset2 is an active potential, and the initialization power source terminal Vinit may transmit an initialization power source signal to the pixel anode node N0. And, when the potential of the second reset signal is the inactive potential, the seventh transistor T7 may be turned off. That is, the seventh transistor T7 may be used to control the initialization power source terminal Vinit to transmit an initialization power source signal to the pixel anode node N0 in response to the second reset signal to reset the pixel anode node N0. The seventh transistor T7 may also be referred to as a reset transistor.

A Gate of the fourth transistor T4 may be connected to the second Gate signal terminal Gate2, a first pole of the fourth transistor T4 may be connected to the Data line Data, and a second pole of the fourth transistor T4 may be connected to the third node N3. When the potential of the second Gate driving signal provided by the second Gate signal terminal Gate2 is the active potential, the fourth transistor T4 may be turned on. At this time, the Data line Data and the third node N3 are connected, and accordingly, the Data line Data may transmit a Data signal to the third node N3, or the Data line Data may collect a potential of the third node N3 and feed back the potential to the test circuit. And, when the potential of the second gate driving signal is the inactive potential, the fourth transistor T4 may be turned off. That is, the fourth transistor T4 may be used to control the turn-on and turn-off of the Data line Data and the third node N3 in response to the second gate driving signal. The fourth transistor T4 may also be referred to as a data write transistor.

A gate of the fifth transistor T5 may be connected to the first emission control terminal EM1, a first pole of the fifth transistor T5 may be connected to the charging power source terminal ELVDD, and a second pole of the fifth transistor T5 may be connected to the third node N3. The fifth transistor T5 may be turned on when the potential of the first lighting control signal supplied from the first lighting control terminal EM1 is an active potential, and at this time, the charging power source terminal ELVDD may transmit a charging power source signal to the third node N3. And, when the potential of the first light emission control signal is the inactive potential, the fifth transistor T5 may be turned off. That is, the fifth transistor T5 may be used to control the charging power source terminal ELVDD to transmit the charging power source signal to the second node N2 in response to the first light-emitting control signal. The fifth transistor T5 may also be referred to as a light emission control transistor.

A gate of the sixth transistor T6 may be connected to the second light emission control terminal EM2, a first pole of the sixth transistor T6 may be connected to the second node N2, and a second pole of the sixth transistor T6 may be connected to the pixel anode node N0. When the potential of the second light emission control signal provided by the second light emission control terminal EM2 is an active potential, the sixth transistor T6 may be turned on, and at this time, the second node N2 and the pixel anode node N0 may be connected. And, when the potential of the second light emission control signal is the inactive potential, the sixth transistor T6 may be turned off. That is, the sixth transistor T6 may be used to control the on/off of the second node N2 and the pixel anode node N0 in response to the second light emission control signal. The sixth transistor T6 may also be referred to as a light emission control transistor.

A gate of the third transistor T3 may be connected to the first node N1, a first pole of the third transistor T3 may be connected to the third node N3, and a second pole of the third transistor T3 may be connected to the second node N2. The third transistor T3 may be turned on when the potential of the first node N1 is an active potential, and at this time, the third transistor T3 may transmit an alternative driving signal to the second node N2 based on the potential of the first node N1 and the potential of the third node N3. When the second node N2 and the pixel anode node N0 are turned on, the potential of the second node N2 (i.e., the alternative driving signal) can be changed to the light-emitting driving signal through the sixth transistor T6, and is transmitted to the pixel anode node N0. A cathode of the first light emitting element 022 is connected to the common power source terminal ELVSS, and the first light emitting element 022 may emit light under a voltage difference of the light emission driving signal and a power source signal supplied from the common power source terminal ELVSS. And, when the potential of the first node N1 is an inactive potential, the third transistor T3 may be turned off. That is, the third transistor T3 may be used to transmit an alternative driving signal for generating a light emission driving signal to the second node N2 based on the potential of the first node N1 and the potential of the third node N3. The third transistor T3 may be referred to as a driving transistor.

As can be seen from the above embodiments, the first pixel circuit 021 can charge the potential of the pixel anode node N0 to a certain potential (the potential after charging is different, typically 1V to 5V, at different gray scales) from the potential of the initial power signal (typically-3V) through the third transistor T3, the fifth transistor T5 and the sixth transistor T6, so that the anode and the cathode have a certain potential difference, and the light-emitting material located between the anode and the cathode is driven to emit light, i.e., the first light-emitting element 022 emits light. The first light emitting element 022 is an Organic Light Emitting Diode (OLED).

Of course, in some other embodiments, the first pixel circuit 021 may be connected to a cathode of the first light emitting element 022, and an anode of the first light emitting element 022 is connected to the common power terminal ELVDD. That is, the anode and the cathode of the first light emitting element 022 may be replaced with each other. In addition, fig. 9 also shows a parasitic capacitance Cp1 existing at the pixel anode node N0 and a parasitic capacitance Cp2 existing on the Data line Data, and the pixel charge amount collected by the test circuit may refer to the charge amount stored in the parasitic capacitance Cp 1.

Alternatively, in the embodiment of the present application, the transistors used in the first pixel circuit 021 may all be thin film transistors or field effect transistors or other devices with the same characteristics, and the transistors used in the embodiment of the present application are mainly switching transistors according to the function in the circuit. Since the source and drain of the switching transistor used herein are symmetrical, the source and drain may be interchanged. In the embodiments of the present application, the source is referred to as a first pole and the drain is referred to as a second pole, or the drain is referred to as a first pole and the source is referred to as a second pole. The form in the drawing provides that the middle end of the transistor is a grid, the signal input end is a source, and the signal output end is a drain. In addition, the transistors used in the embodiments of the present application may include any one of a P-type transistor and an N-type transistor, and as shown in fig. 3, the transistors shown are all P-type transistors. The P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and the N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. That is, for a P-type transistor, the active potential may be low relative to the inactive potential; for an N-type transistor, the active potential may be high relative to the inactive potential. The effective potential and the ineffective potential represent only 2 different state quantities of the potential of the signal, and do not represent that the effective potential and the ineffective potential have specific values.

It should be noted that the first pixel circuit 021 shown in fig. 9 can be regarded as a pixel circuit of a 7T1C (i.e., including 7 transistors and 1 capacitor) structure. In some other embodiments, the first pixel circuit 021 can also be a pixel circuit with other structures (e.g., 6T1C), which is not limited in this application.

The principle of collecting the pixel charge amount by the test circuit based on the first pixel circuit 021 shown in fig. 9 is explained as follows: wherein the acquisition process may comprise two phases. In the phase T1, in conjunction with fig. 10, the signals provided by the respective signal terminals may be set such that only the seventh transistor T7 is turned on and the remaining transistors (i.e., the first to sixth transistors T1 to T6) are all turned off. Further, the initialization power supply terminal Vinit may transmit an initialization power supply signal to the pixel anode node N0 through the seventh transistor T7, thereby resetting the pixel anode node N0. In the stage T2, in conjunction with fig. 11, the signals provided by the respective signal terminals may be set such that the third transistor T3, the fourth transistor T4 and the sixth transistor T6 are all turned on, and the remaining transistors (i.e., the first transistor T1, the second transistor T2, the fifth transistor T5 and the seventh transistor T7) are all turned off. Furthermore, the pixel charge amount at the pixel anode node N0 can be fed back to the Data line Data through the turned-on third transistor T3, fourth transistor T4 and sixth transistor T6, and then fed back to the test circuit through the detection probe PAD connected to the Data line Data, so that the test circuit can analyze and judge the abnormal potential by comparing the pixel charge amounts collected from different pixel anode nodes N0, and detect whether the transparent conductive line L1 is short-circuited. In fig. 10 and 11, the transistor is off is indicated by an "x" symbol.

Taking the first pixel circuit 021 shown in fig. 9 as an example, fig. 12 shows a circuit structure diagram of the first pixels 02 of two adjacent green colors G located in different columns, and in the first pixels 02 of the two adjacent green colors G, the transparent wires L1 connected to the first pixel circuit 021 are all ITO1 routing lines located in the same layer. Referring to fig. 12, it can be seen that, of the adjacent two green G first pixels 02, the first pixel circuit 021 in only one first pixel 02 is connected to the inspection probe Pad through the Data line Data. When the ITO1 traces connected to the two first pixel circuits 021 are short-circuited, it can be seen from fig. 12 that the pixel anode node N0 is short-circuited. Furthermore, the pixel charge amount AT the short-circuit position can be fed back to the test Pin AT Pin of the test circuit through the Data line Data, so that the test circuit can timely and reliably detect the short-circuit defect.

It should be noted that the second pixel 03 includes the second pixel circuit 031 which has the same circuit structure as the first pixel circuit 021, and both of them have the 7T1C structure shown in fig. 9. Alternatively, the circuit structure of the second pixel circuit 031 and the circuit structure of the first pixel circuit 021 may be different. For example, the circuit structure of the first pixel circuit 021 is 7T1C shown in fig. 9, and the circuit structure of the second pixel circuit 031 is 6T 1C. The embodiment of the present application does not limit this.

In addition, only one row of first pixel circuits is connected with the test circuit in at least two adjacent rows of first pixel circuits, so that the difference between the pixel charge quantity of the short-circuited connecting node collected by the test circuit and the pixel charge quantity of the non-short-circuited connecting node is obvious, and whether the short circuit occurs between the two transparent conducting wires is reliably detected by the test circuit.

Fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application. As shown in fig. 13, the display device includes: a photosensor S1, and a display panel 00 as shown in the above figures.

In conjunction with fig. 1, the photo sensor S1 may be located in the second display region a2 of the display panel 00. The photo sensor S1 may be used to implement a photographing function. Among them, fig. 13 also shows a first display area a1 and a non-display area B1.

Alternatively, the second display area a2 may be rectangular, and the area of the orthographic projection of the photosensor S1 on the substrate base plate 01 may be smaller than or equal to the area of the inscribed circle of the second display area a 2. That is, the size of the region where the photo sensor S1 is located may be smaller than or equal to the size of the inscribed circle of the second display region a 2. For example, referring to fig. 13, the display device is shown in which the photo sensor S1 is located in an area having a size equal to that of the inscribed circle Y0 of the second display region a2, i.e., the area where the photo sensor S1 is located may be circular in shape, and accordingly, the area where the photo sensor S1 is located may also be referred to as a light transmission hole. Of course, in some embodiments, the second display area A2 may have a shape other than a rectangle, such as an oval or a circle as shown in FIG. 1.

It should be noted that the display device may further include: an acoustic sensor, which may also be located in the second display area a2, i.e., the acoustic sensor is also hidden under the screen of the display panel 00, to reliably improve the screen occupation ratio of the display device. Of course, in some embodiments, other hardware structures included in the display device besides the light-sensitive sensor and the acoustic sensor may also be disposed in the second display area a 2.

Optionally, still referring to fig. 13, it can be seen that the display device provided in the embodiment of the present application may further include: a driving circuit 10, in conjunction with fig. 1, the driving circuit 10 may be connected to a plurality of Data lines Data in the display panel 00, and is used to provide Data signals to the plurality of Data lines Data. The driving circuit 10 may also be referred to as a source integrated circuit (Driver IC).

Fig. 13 schematically shows the position of the driving circuit 10, and the driving circuit 10 may be located on the right side, the left side, or the upper side of the display panel 00.

Optionally, the display device described in the embodiment of the present application may be: an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, a display and any product or component with a display function.

The terminology used in the description of the embodiments section of the present application is for the purpose of explanation only of the examples of the present application and is not intended to be limiting of the present application. Unless otherwise defined, technical or scientific terms used in the embodiments of the present application should have the ordinary meaning as understood by those having ordinary skill in the art to which the present application belongs.

As used in the specification and claims of this application, the terms "first," "second," or "third," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalents, and does not exclude other elements or items.

"upper", "lower", "left", or "right", etc. are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes. "connect" or "couple" refers to an electrical connection.

"and/or" means that three relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the gate driving circuit, the shift register unit, each circuit and the sub-circuit described above may refer to the corresponding processes in the method embodiments, and are not described herein again.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A display panel, comprising:

a plurality of data lines positioned in the first display area;

2. The display panel according to claim 1, wherein at least two transparent wires are located on different layers and at least two transparent wires are located on the same layer;

3. The display panel according to claim 1, wherein the plurality of first pixels include first pixels of at least two colors;

4. The display panel according to claim 3, wherein, for a plurality of first pixels of the same color, every two adjacent columns of the first pixels include first pixel circuits, one column of the first pixel circuits is connected to the test circuit through the data line, and the other column of the first pixel circuits is not connected to the test circuit.

5. The display panel according to claim 4, wherein for a plurality of first pixels of the same color, the first pixel circuits in the first pixels in the odd-numbered columns are connected to a test circuit through a data line, and the first pixel circuits in the first pixels in the even-numbered columns are not connected to the test circuit.

6. The display panel according to any one of claims 3 to 5, wherein the plurality of first pixels include: a plurality of green first pixels, a plurality of red first pixels, and a plurality of blue first pixels;

in the first green pixel, a first pixel circuit is connected with a first light-emitting element through the first transparent conducting wire;

7. The display panel according to claim 6, wherein the first pixel circuit in the first pixel of green color is adjacent to the second display region with respect to the first pixel circuit in the first pixel of red color, and is adjacent to the second display region with respect to the first pixel circuit in the first pixel of blue color.

8. The display panel according to claim 6, wherein the plurality of first pixels are arranged in order of one red first pixel, one green first pixel, one blue first pixel, and one green first pixel in a pixel row direction.

9. The display panel according to any one of claims 1 to 5, wherein the substrate further has a non-display region at least partially surrounding the first display region; the display panel further includes:

10. The display panel according to any one of claims 1 to 5, wherein the first light-emitting element comprises: an anode and a cathode;

11. The display panel according to any one of claims 1 to 5, wherein the second display region is a light-transmissive display region.

12. The display panel according to any one of claims 1 to 5, characterized by further comprising:

13. A display device, characterized in that the display device comprises: a photosensor, and the display panel of any one of claims 1 to 12;