CN109449196B

CN109449196B - Display panel and display device

Info

Publication number: CN109449196B
Application number: CN201811637212.5A
Authority: CN
Inventors: 李波
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2020-08-18
Anticipated expiration: 2038-12-29
Also published as: CN109449196A

Abstract

The invention provides a display panel and a display device, comprising: the display device comprises a display area, a first light source and a second light source, wherein the display area comprises a first pixel area and a second pixel area, the first pixel area and the second pixel area are arranged in a first direction, and the distance between the center of the display area and the first pixel area in the first direction is smaller than the distance between the center of the display area and the second pixel area in the first direction; the display panel comprises a plurality of first pixel circuits positioned in the first pixel area and a plurality of second pixel circuits positioned in the second pixel area; the first pixel circuit includes a first data line extending in a second direction, the second pixel circuit includes a second data line extending in the second direction, and the first direction is perpendicular to the second direction; the distance between two first data lines of two first pixel circuits adjacent in the first direction is a first data line distance; the distance between two second data lines of two second pixel circuits adjacent in the first direction is a second data line distance; the first data line pitch is smaller than the second data line pitch.

Description

Display panel and display device

[ technical field ] A method for producing a semiconductor device

The present invention relates to the field of organic light emitting display technologies, and in particular, to a display panel and a display device.

[ background of the invention ]

Organic light emitting display devices are widely used and continue to be developed. A major trend in current organic light emitting display devices is to narrow the bezel.

However, when the frame of the organic light emitting display device is narrow, the distance between the metal wires is too small; this limits the narrowing of the bezel of the organic light emitting display device.

[ summary of the invention ]

In order to solve the above technical problems, the present invention provides a display panel and a display device.

In one aspect, a display panel includes: a display area including a first pixel area and a second pixel area, the first pixel area and the second pixel area being arranged in a first direction, a distance between a center of the display area and the first pixel area in the first direction being smaller than a distance between the center of the display area and the second pixel area in the first direction;

the display panel comprises a plurality of first pixel circuits positioned in the first pixel area and a plurality of second pixel circuits positioned in the second pixel area;

the first pixel circuit includes a first data line extending in a second direction, the second pixel circuit includes a second data line extending in the second direction, and the first direction is perpendicular to the second direction;

a pitch between two first data lines of two first pixel circuits adjacent in the first direction is a first data line pitch; a pitch between two of the second data lines of two of the second pixel circuits adjacent in the first direction is a second data line pitch;

the first data line pitch is smaller than the second data line pitch.

Optionally, the display panel further comprises a bezel region surrounding the display region;

the display panel further comprises a fan-out area positioned in the frame area, the fan-out area comprises a plurality of first fan-out lines and a plurality of second fan-out lines, the first fan-out lines are electrically connected with the first data lines, and the second fan-out lines are electrically connected with the second data lines;

on one side of the fan-out area close to the display area, the distance between two adjacent first fan-out lines is smaller than the distance between two adjacent second fan-out lines.

the display panel further comprises a first fan-out area and a second fan-out area, wherein the first fan-out area and the second fan-out area are located in the frame area, the first fan-out area comprises a plurality of first fan-out lines, the second fan-out area comprises a plurality of second fan-out lines, the first fan-out lines are electrically connected with the first data lines, and the second fan-out lines are electrically connected with the second data lines;

the collection position of the first fan-out lines in the first fan-out area is separated from the collection position of the second fan-out lines in the second fan-out area.

the display panel further comprises a first overline, a second overline and a third overline which are positioned in the frame area, wherein the first overline and the second overline extend in the first direction, and a plurality of the third overlines extend in the second direction;

the first overline is close to the display area, the second overline is positioned on one side of the first overline far away from the display area, and the third overline is positioned between the first overline and the second overline;

the display panel further comprises a first power line and a second power line which are located in the display area, the first power line is electrically connected with the first overline, the second power line is electrically connected with the first overline, the first overline is electrically connected with the third overline, and the third overline is electrically connected with the second overline.

Optionally, the third plurality of flying leads comprises a third plurality of flying leads and a third plurality of flying leads;

an extension line of the third crossover line intersects with the first pixel region, and an extension line of the third crossover line intersects with the second pixel region;

the distance between two adjacent third overlines is smaller than that between two adjacent third overlines.

Optionally, the first pixel circuit includes a first initialization transistor of a single gate, a first initialization transistor of a second gate, a first scan line extending in the first direction;

the grid electrode of the first initialization transistor and the grid electrode of the first second initialization transistor are positioned on the first scanning line.

Optionally, the second pixel circuit comprises a second initialization transistor, a second initialization transistor and a second scanning line which are double-gated;

the second scanning line comprises a linear part extending in the first direction and a convex part extending in the second direction, and the linear part is connected with the convex part;

the first grid electrode of the second initialization transistor and the grid electrode of the second initialization transistor are positioned at the straight line part, and the second grid electrode of the second initialization transistor is positioned at the convex part;

in the first direction, the second gate of the second initialization transistor is located between the first gate of the second initialization transistor and the gate of the second initialization transistor.

Optionally, a distance between the gate of the first initialization transistor a and the gate of the first initialization transistor b is a first initialization transistor pitch, and a distance between the first gate of the second initialization transistor b and the gate of the second initialization transistor b is a second initialization transistor pitch;

the first initialization transistor pitch is less than the second initialization transistor pitch.

Optionally, the first pixel circuit includes a first power supply line extending in the second direction;

the first scanning line is positioned on a first metal layer, the first data line and the first power line are positioned on a second metal layer, and the second metal layer is positioned on the first metal layer;

the first power line overlaps with a gate of the first initialization transistor, and the first power line overlaps with a gate of the first second initialization transistor.

Optionally, the second pixel circuit includes a second power supply line extending in the second direction;

the second scanning line is positioned on the first metal layer, and the second data line and the second power line are positioned on the second metal layer;

the second power supply line overlaps with the first gate of the second initialization transistor, and the second power supply line does not overlap with the gate of the second initialization transistor.

Optionally, a distance between the first power line and the gate of the first second initialization transistor is a first power line transistor pitch, and a distance between the second power line and the gate of the second initialization transistor is a second power line transistor pitch;

the first power line transistor pitch is smaller than the second power line transistor pitch.

Optionally, a distance between the first data line and the first power line is a first data line power line pitch, and a distance between the second data line and the second power line is a second data line power line pitch;

the first data line power line pitch is substantially equal to the second data line power line pitch.

Optionally, the first pixel circuit includes a first driving transistor, a first connection line, and a first second connection line;

the grid electrode of the first driving transistor is positioned on the first metal layer, the first A connecting line is positioned on the second metal layer, and the first B connecting line is positioned on the semiconductor layer;

the semiconductor layer is positioned on one side of the first metal layer far away from the second metal layer;

the grid electrode of the first driving transistor is electrically connected with the first A connecting line, the first A connecting line is electrically connected with the first B connecting line, and the first B connecting line is electrically connected with the source electrode or the drain electrode of the first A initialization transistor;

the first pixel circuit comprises a first shielding electrode plate, and the first shielding electrode plate is positioned on a third metal layer;

the third metal layer is located between the first metal layer and the second metal layer;

the first shielding electrode plate interrupts a connection line between the first data line and the first second connection line.

Optionally, the second pixel circuit includes a second driving transistor, a second connecting line, and a second connecting line;

the grid electrode of the second driving transistor is positioned on the first metal layer, the second connecting line is positioned on the second metal layer, and the second connecting line is positioned on the semiconductor layer;

the grid electrode of the second driving transistor is electrically connected with the second connecting wire, the second connecting wire is electrically connected with the second diethyl connecting wire, and the second diethyl connecting wire is electrically connected with the source electrode or the drain electrode of the second initialization transistor;

the second pixel circuit comprises a second shielding electrode plate, and the second shielding electrode plate is positioned on the third metal layer;

the second shielding electrode plate interrupts the connection between the second data line and the second connecting line;

the area of the first shielding electrode plate is larger than that of the second shielding electrode plate.

Optionally, the first pixel circuit comprises a first reference line extending in the first direction;

the first reference line is positioned on the third metal layer and is electrically connected with a source electrode or a drain electrode of the first second initialization transistor;

the first reference line is located on one side, away from the first shielding electrode plate, of the first scanning line.

Optionally, the second pixel circuit comprises a second reference line extending in the first direction;

the second reference line is positioned on the third metal layer and is electrically connected with the source electrode or the drain electrode of the second diethyl initialization transistor;

the second reference line is located on one side of the second scanning line close to the second shielding electrode plate.

In another aspect, a display device includes the display panel.

In the invention, the first pixel circuit comprises a first data line, the second pixel circuit comprises a second data line, the fan-out area is provided with a first fan-out line and a second fan-out line, the first fan-out line is electrically connected with the first data line through the multi-path selection circuit, and the second fan-out line is electrically connected with the second data line through the multi-path selection circuit; the first data line is close to the center of the display area, and the second data line is far away from the center of the display area; correspondingly, the first fan-out line is close to the center of the fan-out area, and the second fan-out line is far away from the center of the fan-out area; when the size of the fan-out area in the second direction is smaller, the first fan-out line is straighter, and the second fan-out line is more inclined. Meanwhile, the distance between two adjacent first data lines is smaller than the distance between two adjacent second data lines; correspondingly, on one side of the fan-out area close to the display area, the distance between two adjacent first fan-out lines is smaller than the distance between two adjacent second fan-out lines; this makes the first fanout line denser and the second fanout line more sparser. When the size of the fan-out area in the second direction is smaller, although the first fan-out lines become denser, the first fan-out lines are straighter, so that the distance between two adjacent first fan-out lines is moderate; although the second fanout lines are relatively inclined, the second fanout lines become relatively sparse, so that the distance between two adjacent second fanout lines is moderate; the fan-out area may be smaller in size in the second direction. Thus, the frame region of the display panel may be narrow.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic plan view of a prior art display panel 100;

FIG. 2 is another schematic plan view of a prior art display panel 100;

FIG. 3 is a schematic plan view of a display area AA200 of a display panel 200 according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a first pixel circuit PX210 in a display panel 200 according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of the semiconductor layer POLY200 in the first pixel circuit PX210 according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of the first metal layer M210 in the first pixel circuit PX210 according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of the third metal layer M230 in the first pixel circuit PX210 according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of the second metal layer M220 in the first pixel circuit PX210 according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a second pixel circuit PX220 in a display panel 200 according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of the semiconductor layer POLY200 in the second pixel circuit PX220 according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of the first metal layer M210 in the second pixel circuit PX220 according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of the third metal layer M230 in the second pixel circuit PX220 according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of the second metal layer M220 in the second pixel circuit PX220 according to an embodiment of the present invention;

FIG. 14 is a schematic plan view of another display panel 200 according to an embodiment of the invention;

FIG. 15 is a schematic plan view of another display panel 200 according to an embodiment of the invention;

fig. 16 is a schematic plan view of a display device 300 according to an embodiment of the invention.

[ detailed description ] embodiments

For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is only one type of association relationship that describes the associated object, meaning that three types of relationships may exist, e.g., a second direction and/or a first direction, may mean: the second direction exists alone, the second direction and the first direction exist simultaneously, and the first direction exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that although the terms first, second, etc. may be used herein to describe devices in accordance with embodiments of the present invention, these devices should not be limited by these terms. These terms are only used to distinguish one device from another. For example, a first device may also be referred to as a second device, and similarly, a second device may also be referred to as a first device, without departing from the scope of embodiments of the present invention.

FIG. 1 is a schematic plan view of a prior art display panel 100; fig. 2 is another schematic plan view of the prior art display panel 100.

As shown in fig. 1 and 2, in the prior art, the display panel 100 includes a display area AA100 and a frame area NA100, where the frame area NA100 includes a circuit area DA100 and a fan-out area FA 100; the display panel 100 includes a DATA line DATA100 located in the display area AA100, a multiplexing circuit D100 located in the circuit area DA100, and a fan-out line F100 located in the fan-out area FA100, wherein the multiplexing circuit D100 is located between the DATA line DATA100 and the fan-out line F100; the DATA line DATA100 is connected with the multi-path selection circuit D100, and the multi-path selection circuit D100 is connected with the fanout line F100; the DATA lines DATA100 are arranged at equal intervals in a first direction X, the DATA lines DATA100 extend in a second direction Y, and the first direction X is perpendicular to the second direction Y; accordingly, the fanout lines F100 are disposed at equal intervals on a side adjacent to the multiplexing circuit D100; a dimension G101 of the fan-out area FA100 in the second direction Y in fig. 1 is larger than a dimension G102 of the fan-out area FA100 in the second direction Y in fig. 2. As shown in fig. 1, when the dimension G101 of the fan-out area FA100 in the second direction Y is large, the fan-out lines F100 are straight and the spacing between the fan-out lines F100 is large at the center of the fan-out area FA 100; moreover, at two sides of the fan-out area FA100, the inclination of the fan-out lines F100 is moderate, and the space between the fan-out lines F100 is moderate. As shown in fig. 2, when the dimension G102 of the fan-out area FA100 in the second direction Y becomes smaller, the fan-out lines F100 remain straighter and the spacing between the fan-out lines F100 remains larger at the center of the fan-out area FA 100; however, at both sides of the fan-out area FA100, the fan-out lines F100 become more inclined, and the pitch between the fan-out lines F100 becomes too small; the size of the fan-out area FA100 in the second direction Y may not be small. This limits the narrowing of the frame of the display panel 100.

FIG. 3 is a schematic plan view of a display area AA200 of a display panel 200 according to an embodiment of the present invention; fig. 4 is a schematic structural diagram of a first pixel circuit PX210 in a display panel 200 according to an embodiment of the present invention; fig. 5 is a schematic structural diagram of the semiconductor layer POLY200 in the first pixel circuit PX210 according to an embodiment of the present invention; fig. 6 is a schematic structural diagram of the first metal layer M210 in the first pixel circuit PX210 according to an embodiment of the present invention; fig. 7 is a schematic structural diagram of the third metal layer M230 in the first pixel circuit PX210 according to an embodiment of the present invention; fig. 8 is a schematic structural diagram of the second metal layer M220 in the first pixel circuit PX210 according to an embodiment of the present invention; fig. 9 is a schematic structural diagram of a second pixel circuit PX220 in a display panel 200 according to an embodiment of the present invention; fig. 10 is a schematic structural diagram of the semiconductor layer POLY200 in the second pixel circuit PX220 according to an embodiment of the present invention; fig. 11 is a schematic structural diagram of the first metal layer M210 in the second pixel circuit PX220 according to an embodiment of the present invention; fig. 12 is a schematic structural diagram of the third metal layer M230 in the second pixel circuit PX220 according to an embodiment of the present invention; fig. 13 is a schematic structural diagram of the second metal layer M220 in the second pixel circuit PX220 according to an embodiment of the present invention.

As shown in fig. 3, in the embodiment of the present invention, the display panel 200 includes: a display area AA200, wherein the display area AA200 includes a first pixel area AA201 and a second pixel area AA202, the first pixel area AA201 and the second pixel area AA202 are arranged in a first direction X, and a distance between a center of the display area AA200 and the first pixel area AA201 in the first direction X is smaller than a distance between the center of the display area AA200 and the second pixel area AA202 in the first direction X;

the display panel 200 includes a plurality of first pixel circuits PX210 located in the first pixel area AA201, a plurality of second pixel circuits PX220 located in the second pixel area AA 202;

the first pixel circuit PX210 includes a first DATA line DATA210 extending in a second direction Y, and the second pixel circuit PX220 includes a second DATA line DATA220 extending in the second direction Y, the first direction X being perpendicular to the second direction Y;

a pitch between two first DATA lines DATA210 of two first pixel circuits PX210 adjacent in the first direction X is a first DATA line pitch; a pitch between two second DATA lines DATA220 of two second pixel circuits PX220 adjacent in the first direction X is a second DATA line pitch;

the first data line pitch is smaller than the second data line pitch.

As shown in fig. 3, in the embodiment of the present invention, the display panel 200 further includes a frame area NA200 surrounding the display area AA 200; the frame area NA200 comprises a circuit area DA200 and a fan-out area FA 200; the circuit area DA200 is located between the display area AA200 and the fan-out area FA 200; the display panel 200 further includes a multi-path selection circuit D200 located in the circuit area DA200, a plurality of first fan-out lines F210 and a plurality of second fan-out lines F220 located in the fan-out area FA 200; the first fanout line F210 is electrically connected to the first DATA line DATA210 through the multiplexing circuit D200, and the second fanout line F220 is electrically connected to the second DATA line DATA220 through the multiplexing circuit D200.

In the embodiment of the present invention, the first pixel circuit PX210 includes a first DATA line DATA210, the second pixel circuit PX220 includes a second DATA line DATA220, the fan-out area FA200 is provided with a first fan-out line F210 and a second fan-out line F220, the first fan-out line F210 is electrically connected to the first DATA line DATA210 through the multi-path selection circuit D200, and the second fan-out line F220 is electrically connected to the second DATA line DATA220 through the multi-path selection circuit D200; the first DATA line DATA210 is close to the center of the display area AA200, and the second DATA line DATA220 is far from the center of the display area AA 200; accordingly, the first fanout line F210 is close to the center of the fanout area FA200, and the second fanout line F220 is far from the center of the fanout area FA 200; when the fan-out area FA200 is smaller in the second direction Y, the first fan-out line F210 is straighter and the second fan-out line F220 is more inclined. Meanwhile, the distance between two adjacent first DATA lines DATA210 is smaller than the distance between two adjacent second DATA lines DATA 220; correspondingly, on one side of the fan-out area FA200 close to the display area AA200, the distance between two adjacent first fan-out lines F210 is smaller than the distance between two adjacent second fan-out lines F220; this may make the first fanout line F210 denser and the second fanout line F220 more sparse. When the size of the fan-out area FA200 in the second direction Y is smaller, although the first fan-out lines F210 become denser, the first fan-out lines F210 are straighter, so that the distance between two adjacent first fan-out lines F210 is moderate; although the second fanout lines F220 are relatively inclined, the second fanout lines F220 become relatively sparse, so that the distance between two adjacent second fanout lines F220 is moderate; the size of the fan-out area FA200 in the second direction Y may be small. Accordingly, the frame area NA200 of the display panel 200 may be narrower.

As shown in fig. 3 to 13, the first pixel area AA201 is located between two second pixel areas AA 202. The display panel 200 further includes a semiconductor layer POLY200, a first metal layer M210, a third metal layer M230, and a second metal layer M220 sequentially disposed on the substrate.

As shown in fig. 4 to 8, the first pixel circuit PX210 includes a first SCAN line SCAN211, a first second SCAN line SCAN212, a first emission line EMIT210, a first gate metal plate MG210, a first reference line VREF210 in the third metal layer M230, a first DATA line DATA210 in the second metal layer M220, and a first power line PVDD 210; the semiconductor layer POLY200 overlaps the first SCAN line SCAN211 to form a first initialization transistor T215 and a first second initialization transistor T217, the semiconductor layer POLY200 overlaps the first second SCAN line SCAN212 to form a first data write transistor T212 and a first second data write transistor T214, and the semiconductor layer POLY200 overlaps the first emission line EMIT210 to form a first emission control transistor T211 and a first second emission control transistor T216; the semiconductor layer POLY200 overlaps the first gate metal plate MG210 to constitute a first driving transistor T213, and the first driving transistor T213 overlaps the first storage capacitor C210.

A control electrode of the first initialization transistor T215 is electrically connected to the first SCAN line SCAN211, a first electrode of the first initialization transistor T215 is connected to the first reference line VREF210, and a second electrode of the first initialization transistor T215 is connected to the gate electrode of the first driving transistor T213. A control electrode of the first second initialization transistor T217 is connected to the first SCAN line SCAN211, a first electrode of the first second initialization transistor T217 is connected to the first reference line VREF210, and a second electrode of the first second initialization transistor T217 is connected to the organic light emitting diode in the display panel 200.

A control electrode of the first a DATA writing transistor T212 is connected to the first b SCAN line SCAN212, a first electrode of the first a DATA writing transistor T212 is connected to the first DATA line DATA210, and a second electrode of the first a DATA writing transistor T212 is connected to a first electrode of the first driving transistor T213. A control electrode of the first second data writing transistor T214 is connected to the first second SCAN line SCAN212, a first electrode of the first second data writing transistor T214 is connected to a gate electrode of the first driving transistor T213, and a second electrode of the first second data writing transistor T214 is connected to a second electrode of the first driving transistor T213.

A control electrode of the first emission control transistor T211 is connected to the first emission line EMIT210, a first electrode of the first emission control transistor T211 is connected to the first power line PVDD210, and a second electrode of the first emission control transistor T211 is connected to a first electrode of the first driving transistor T213. A control electrode of the first second emission control transistor T216 is connected to the first emission line EMIT210, a first electrode of the first second emission control transistor T216 is connected to a second electrode of the first driving transistor T213, and a second electrode of the first second emission control transistor T216 is connected to the organic light emitting diode in the display panel 200.

A first electrode of the first storage capacitor C210 is connected to the first power line PVDD210, and a second electrode of the first storage capacitor C210 is connected to the gate of the first driving transistor T213.

As shown in fig. 9 to 13, the second pixel circuit PX220 includes a second SCAN line SCAN221, a second SCAN line SCAN222, a second emission line EMIT220, a second gate metal plate MG220, a second reference line VREF220, a second DATA line DATA220, and a second power line PVDD220, which are disposed in the first metal layer M210, a third metal layer M230, and a third metal layer M220; the semiconductor layer POLY200 overlaps the second scanning line SCAN221 to form a second initialization transistor T225 and a second initialization transistor T227, the semiconductor layer POLY200 overlaps the second scanning line SCAN222 to form a second data writing transistor T222 and a second data writing transistor T224, and the semiconductor layer POLY200 overlaps the second emission line EMIT220 to form a second emission control transistor T221 and a second emission control transistor T226; the semiconductor layer POLY200 overlaps the second gate metal plate MG220 to constitute a second driving transistor T223, and the second driving transistor T223 overlaps the second storage capacitor C220.

A control electrode of the second initialization transistor T225 is electrically connected to the second SCAN line SCAN221, a first electrode of the second initialization transistor T225 is connected to the second reference line VREF220, and a second electrode of the second initialization transistor T225 is connected to the gate electrode of the second driving transistor T223. A control electrode of the second initializing transistor T227 is connected to the second SCAN line SCAN221, a first electrode of the second initializing transistor T227 is connected to the second reference line VREF220, and a second electrode of the second initializing transistor T227 is connected to the organic light emitting diode in the display panel 200.

A control electrode of the second DATA writing transistor T222 is connected to the second SCAN line SCAN222, a first electrode of the second DATA writing transistor T222 is connected to the second DATA line DATA220, and a second electrode of the second DATA writing transistor T222 is connected to the first electrode of the second driving transistor T223. A control electrode of the second data writing transistor T224 is connected to the second scanning line SCAN222, a first electrode of the second data writing transistor T224 is connected to a gate electrode of the second driving transistor T223, and a second electrode of the second data writing transistor T224 is connected to a second electrode of the second driving transistor T223.

A control electrode of the second emission control transistor T221 is connected to the second emission line EMIT220, a first electrode of the second emission control transistor T221 is connected to the second power line PVDD220, and a second electrode of the second emission control transistor T221 is connected to the first electrode of the second driving transistor T223. A control electrode of the second light emitting control transistor T226 is connected to the second emission line EMIT220, a first electrode of the second light emitting control transistor T226 is connected to a second electrode of the second driving transistor T223, and a second electrode of the second light emitting control transistor T226 is connected to the organic light emitting diode in the display panel 200.

A first electrode of the second storage capacitor C220 is connected to the second power line PVDD220, and a second electrode of the second storage capacitor C220 is connected to the gate of the second driving transistor T223.

As shown in fig. 3, in the embodiment of the present invention, the display panel 200 further includes a frame area NA200 surrounding the display area AA 200; the display panel 200 further includes a fan-out area FA200 located in the frame area NA200, where the fan-out area FA200 includes a plurality of first fan-out lines F210 and a plurality of second fan-out lines F220, the first fan-out lines F210 are electrically connected to the first DATA lines DATA210, and the second fan-out lines F220 are electrically connected to the second DATA lines DATA 220; on one side of the fan-out area FA200 close to the display area AA200, a spacing between two adjacent first fan-out lines F210 is smaller than a spacing between two adjacent second fan-out lines F220.

In the embodiment of the present invention, the display panel 200 further includes a circuit area DA 200; the circuit area DA200 is located between the display area AA200 and the fan-out area FA 200; the display panel 200 further includes a multiplexing circuit D200 located in the circuit area DA 200; the first fanout line F210 is electrically connected to the first DATA line DATA210 through the multiplexing circuit D200, and the second fanout line F220 is electrically connected to the second DATA line DATA220 through the multiplexing circuit D200. Specifically, the first fanout line F210 and the second fanout line F220 are located in the first metal layer M210, the first DATA line DATA210 is electrically connected to the multi-way selection circuit D200 through a first connection line, the second DATA line DATA220 is electrically connected to the multi-way selection circuit D200 through a second connection line, and the first connection line and the second connection line are located in the first metal layer M210.

In the embodiment of the present invention, on one side of the fan-out area FA200 close to the display area AA200, a distance between two adjacent first fan-out lines F210 is smaller than a distance between two adjacent second fan-out lines F220; this may make the first fanout line F210 denser and the second fanout line F220 more sparse; moreover, the first fanout line F210 is relatively straight, and the second fanout line F220 is relatively inclined. When the size of the fan-out area FA200 in the second direction Y is smaller, although the first fan-out lines F210 become denser, the first fan-out lines F210 are straighter, so that the distance between two adjacent first fan-out lines F210 is moderate; although the second fanout lines F220 are relatively inclined, the second fanout lines F220 become relatively sparse such that a distance between two adjacent second fanout lines F220 is moderate. Accordingly, the size of the fan-out area FA200 in the second direction Y may be small.

Fig. 14 is a schematic plan view of another display panel 200 according to an embodiment of the invention.

As shown in fig. 14, in the embodiment of the present invention, the display panel 200 further includes a frame area NA200 surrounding the display area AA 200; the display panel 200 further includes a first fan-out area FA210 and a second fan-out area FA220 located in the frame area NA200, the first fan-out area FA210 includes a plurality of first fan-out lines F210, the second fan-out area FA220 includes a plurality of second fan-out lines F220, the first fan-out lines F210 are electrically connected to the first DATA lines DATA210, and the second fan-out lines F220 are electrically connected to the second DATA lines DATA 220; the convergence of the plurality of first fan-out lines F210 in the first fan-out area FA210 is separated from the convergence of the plurality of second fan-out lines F220 in the second fan-out area FA 220.

In an embodiment of the present invention, the first fan-out area FA210 is located between two second fan-out areas FA 220. The size of the first fan-out area FA210 in the first direction X and the size of the second fan-out area FA220 in the first direction X are smaller; at the center of the first fan-out area FA210, the first fan-out line F210 is straight; at the center of the second fan-out area FA220, the second fan-out line F220 is straight; at both sides of the first fan-out area FA210, the inclination of the first fan-out line F210 is moderate; at both sides of the second fan-out region FA220, the inclination of the second fan-out line F220 is moderate; when the size of the fan-out area FA200 in the second direction Y is small, the interval between two adjacent first fan-out lines F210 is moderate at both sides of the first fan-out area FA210, and the interval between two adjacent second fan-out lines F220 is moderate at both sides of the second fan-out area FA 220. Accordingly, the size of the first fan-out area FA210 in the second direction Y and the size of the second fan-out area FA220 in the second direction Y may be smaller.

Fig. 15 is a schematic plan view of another display panel 200 according to an embodiment of the invention.

As shown in fig. 15, in the embodiment of the present invention, the display panel 200 further includes a frame area NA200 surrounding the display area AA 200; the display panel 200 further includes a first cross line L210, a second cross line L220, and a third cross line L230 located in the frame area NA200, where the first cross line L210 and the second cross line L220 extend in the first direction X, and a plurality of the third cross lines L230 extend in the second direction Y; the first crossover line L210 is adjacent to the display area AA200, the second crossover line L220 is located on a side of the first crossover line L210 away from the display area AA200, and the third crossover line L230 is located between the first crossover line L210 and the second crossover line L220; the display panel 200 further includes a first power line PVDD210 and a second power line PVDD220 located in the display area AA200, the first power line PVDD210 is electrically connected to the first cross line L210, the second power line PVDD220 is electrically connected to the first cross line L210, the first cross line L210 is electrically connected to the third cross line L230, and the third cross line L230 is electrically connected to the second cross line L220.

In the embodiment of the present invention, the first crossover line L210, the second crossover line L220, and the plurality of third crossover lines L230 are located on the second metal layer M220, and the first crossover line L210, the second crossover line L220, and the plurality of third crossover lines L230 are used for transmitting constant voltage signals to the first power line PVDD210 and the second power line PVDD 220. When more overlines transmit the constant voltage signal, the voltage drop of the constant voltage signal is smaller, so that the light emitting intensity of the display area AA200 is more uniform.

As shown in fig. 15, in the embodiment of the present invention, the plurality of third flying leads L230 includes a plurality of third flying leads L231, a plurality of third flying leads L232; an extension line of the third crossover line L231 intersects with the first pixel area AA201, and an extension line of the third crossover line L232 intersects with the second pixel area AA 202; the pitch of the two adjacent third overpasses L231 is smaller than the pitch of the two adjacent third overpasses L232.

In the embodiment of the invention, the distance between two adjacent first DATA lines DATA210 is smaller than the distance between two adjacent second DATA lines DATA 220; accordingly, the pitch between two first pixel circuits PX210 adjacent in the first direction X is smaller than the pitch between two second pixel circuits PX220 adjacent in the first direction X; accordingly, the interval between two adjacent first power lines PVDD210 is smaller than the interval between two adjacent second power lines PVDD 220; meanwhile, the distance between two adjacent third overpasses L231 is smaller than the distance between two adjacent third overpasses L232; the first power line PVDD210 is disposed opposite to the third crossover line L231, the first power line PVDD210 is dense, and meanwhile, the third crossover line L231 is dense; the second power line PVDD220 is disposed opposite to the third cross line L232, the second power line PVDD220 is relatively sparse, and meanwhile, the third cross line L232 is relatively sparse. Accordingly, the constant voltage signals transmitted to the first power line PVDD210 and the second power line PVDD220 by the third and third overpasses L231 and L232 are relatively uniform.

As shown in fig. 4 to 8, in the embodiment of the present invention, the first pixel circuit PX210 includes a first initialization transistor T215 of a single gate, a first second initialization transistor T217, a first SCAN line SCAN211 extending in the first direction X; the gate of the first initialization transistor T215 and the gate of the first second initialization transistor T217 are located on the first SCAN line SCAN 211.

In the embodiment of the present invention, the gate of the first initialization transistor T215 and the gate of the first second initialization transistor T217 are located on the first SCAN line SCAN211, the first initialization transistor T215 is a single gate, and no other gate is located between the gate of the first initialization transistor T215 and the gate of the first second initialization transistor T217; accordingly, the pitch between the gates of the first a initializing transistor T215 and the first b initializing transistor T217 is small, which can reduce the size of the single first pixel circuit PX210 in the first direction X.

As shown in fig. 9 to 13, in the embodiment of the present invention, the second pixel circuit PX220 includes a second initialization transistor T225, a second initialization transistor T227, a second SCAN line SCAN 221; the second SCAN line SCAN221 includes a straight portion DL200 extending in the first direction X, and a convex portion PR200 extending in the second direction Y, the straight portion DL200 being connected to the convex portion PR 200; a first gate electrode of the second initialization transistor T225 and a gate electrode of the second initialization transistor T227 are positioned at the straight line portion DL200, and a second gate electrode of the second initialization transistor T225 is positioned at the protruding portion PR 200; in the first direction X, the second gate of the second initialization transistor T225 is located between the first gate of the second initialization transistor T225 and the gate of the second initialization transistor T227.

In the embodiment of the present invention, the first gate of the second initialization transistor T225 and the gate of the second initialization transistor T227 are located at the straight line portion DL200 of the second scanning line SCAN221, the second initialization transistor T225 is dual-gate, and the second gate of the second initialization transistor T225 is located between the first gate of the second initialization transistor T225 and the gate of the second initialization transistor T227; accordingly, the spacing between the first gate of the second initializing transistor T225 and the gate of the second initializing transistor T227 is large, which can enlarge the size of the single second pixel circuit PX220 in the first direction X.

As shown in fig. 4 to 13, in the embodiment of the present invention, a distance between the gate of the first a initialization transistor T215 and the gate of the first b initialization transistor T217 is a first initialization transistor pitch, and a distance between the first gate of the second a initialization transistor T225 and the gate of the second b initialization transistor T227 is a second initialization transistor pitch; the first initialization transistor pitch is less than the second initialization transistor pitch.

In the embodiment of the present invention, the distance between the gate of the first initialization transistor T215 and the gate of the first second initialization transistor T217 is small, and the distance between the first gate of the second initialization transistor T225 and the gate of the second initialization transistor T227 is large; thus, the size of the single first pixel circuit PX210 in the first direction X is small, and the size of the single second pixel circuit PX220 in the first direction X is large; accordingly, the interval between the two first DATA lines DATA210 of the two first pixel circuits PX210 adjacent in the first direction X is small, and the interval between the two second DATA lines DATA220 of the two second pixel circuits PX220 adjacent in the first direction X is large.

As shown in fig. 4 to 8, in the embodiment of the present invention, the first pixel circuit PX210 includes a first power line PVDD210 extending in the second direction Y; the first SCAN line SCAN211 is located on the first metal layer M210, the first DATA line DATA210 and the first power line PVDD210 are located on the second metal layer M220, and the second metal layer M220 is located on the first metal layer M210; the first power supply line PVDD210 overlaps the gate of the first a-initialization transistor T215, and the first power supply line PVDD210 overlaps the gate of the first b-initialization transistor T217.

In the embodiment of the present invention, the first power supply line PVDD210 overlaps the gate of the first a initialization transistor T215, and the first power supply line PVDD210 overlaps the gate of the first b initialization transistor T217; the spacing between the first power supply line PVDD210 and the first second initialization transistor T217 in the first direction X is zero, which can reduce the size of the single first pixel circuit PX210 in the first direction X.

As shown in fig. 9 to 13, in the embodiment of the present invention, the second pixel circuit PX220 includes a second power line PVDD220 extending in the second direction Y; the second SCAN line SCAN221 is disposed on the first metal layer M210, and the second DATA line DATA220 and the second power line PVDD220 are disposed on the second metal layer M220; the second power supply line PVDD220 overlaps a first gate of the second initialization transistor T225, and the second power supply line PVDD220 does not overlap a gate of the second initialization transistor T227.

In the embodiment of the present invention, the second power supply line PVDD220 overlaps the first gate of the second initialization transistor T225, and the second power supply line PVDD220 does not overlap the gate of the second initialization transistor T227; the larger spacing between the second power supply line PVDD220 and the second reset transistor T227 in the first direction X may expand the size of the single second pixel circuit PX220 in the first direction X.

As shown in fig. 4 to 13, in the embodiment of the present invention, a distance between the first power line PVDD210 and the gate of the first second initialization transistor T217 is a first power line transistor pitch, and a distance between the second power line PVDD220 and the gate of the second initialization transistor T227 is a second power line transistor pitch; the first power line transistor pitch is smaller than the second power line transistor pitch.

In the embodiment of the present invention, the distance between the first power line PVDD210 and the gate of the first second initialization transistor T217 is smaller, and the distance between the second power line PVDD220 and the gate of the second initialization transistor T227 is larger; thus, the size of the single first pixel circuit PX210 in the first direction X is small, and the size of the single second pixel circuit PX220 in the first direction X is large; accordingly, the interval between the two first DATA lines DATA210 of the two first pixel circuits PX210 adjacent in the first direction X is small, and the interval between the two second DATA lines DATA220 of the two second pixel circuits PX220 adjacent in the first direction X is large.

As shown in fig. 4 to 13, in the embodiment of the invention, a distance between the first DATA line DATA210 and the first power line PVDD210 is a first DATA line power line pitch, and a distance between the second DATA line DATA220 and the second power line PVDD220 is a second DATA line power line pitch; the first data line power line pitch is substantially equal to the second data line power line pitch.

In an embodiment of the present invention, in one aspect, the first DATA line power line pitch is substantially equal to the second DATA line power line pitch, the first DATA line power line pitch and the second DATA line power line pitch are set moderately, the crosstalk between the first DATA line DATA210 and the first power line PVDD210 is small, and the crosstalk between the second DATA line DATA220 and the second power line PVDD220 is small; on the other hand, the first DATA line power line pitch is substantially equal to the second DATA line power line pitch, the distance between the first power line PVDD210 and the gate of the first second initialization transistor T217 is small, the distance between the second power line PVDD220 and the gate of the second initialization transistor T227 is large, the distance between the first DATA line DATA210 and the gate of the first second initialization transistor T217 is small, and the distance between the second DATA line DATA220 and the gate of the second initialization transistor T227 is large, which may reduce the size of a single first pixel circuit PX210 in the first direction X and expand the size of a single second pixel circuit PX220 in the first direction X.

As shown in fig. 4 to 8, in the embodiment of the present invention, the first pixel circuit PX210 includes a first driving transistor T213, a first a connection line N211, a first b connection line N212; the gate of the first driving transistor T213 is located at the first metal layer M210, the first a connection line N211 is located at the second metal layer M220, and the first b connection line N212 is located at the semiconductor layer POLY 200; the semiconductor layer POLY200 is located on a side of the first metal layer M210 away from the second metal layer M220; the gate of the first driving transistor T213 is electrically connected to the first a connection line N211, the first a connection line N211 is electrically connected to the first b connection line N212, and the first b connection line N212 is electrically connected to the source or drain of the first a initialization transistor T215; the first pixel circuit PX210 includes a first shielding electrode plate S210, and the first shielding electrode plate S210 is located at the third metal layer M230; the third metal layer M230 is located between the first metal layer M210 and the second metal layer M220; the first shielding electrode plate S210 interrupts the connection of the first DATA line DATA210 and the first b connection line N212.

In the embodiment of the invention, when the distance between the first DATA line DATA210 and the gate of the first second initialization transistor T217 is smaller, the distance between the first DATA line DATA210 and the first second connection line N212 becomes smaller, and the parasitic capacitance between the first DATA line DATA210 and the first second connection line N212 becomes larger, so that the driving current of the first driving transistor T213 is shifted. In this regard, the first shielding electrode plate S210 is provided, the first shielding electrode plate S210 interrupts the connection between the first DATA line DATA210 and the first second connection line N212, and the first shielding electrode plate S210 shields a portion of an electric field generated by the first DATA line DATA210 or the first second connection line N212, so as to suppress a parasitic capacitance between the first DATA line DATA210 and the first second connection line N212, thereby preventing a driving current of the first driving transistor T213 from being deviated.

As shown in fig. 9 to 13, in the embodiment of the present invention, the second pixel circuit PX220 includes a second driving transistor T223, a second connecting line N221, a second connecting line N222; the gate of the second driving transistor T223 is located in the first metal layer M210, the second connection line N221 is located in the second metal layer M220, and the second connection line N222 is located in the semiconductor layer POLY 200; the gate of the second driving transistor T223 is electrically connected to the second connecting line N221, the second connecting line N221 is electrically connected to the second connecting line N222, and the second connecting line N222 is electrically connected to the source or drain of the second initialization transistor T225; the second pixel circuit PX220 includes a second shielding electrode plate S220, and the second shielding electrode plate S220 is located at the third metal layer M230; the second shielding electrode plate S220 interrupts the connection between the second DATA line DATA220 and the second connecting line N222; the area of the first shielding electrode plate S210 is larger than that of the second shielding electrode plate S220.

In the embodiment of the invention, the second shielding electrode plate S220 interrupts the connection between the second DATA line DATA220 and the second connecting line N222, and the second shielding electrode plate S220 shields a part of an electric field generated by the second DATA line DATA220 or the second connecting line N222, so as to suppress a parasitic capacitance between the second DATA line DATA220 and the second connecting line N222, thereby preventing a driving current of the second driving transistor T223 from deviating. In addition, the distance between the first DATA line DATA210 and the gate of the first second initialization transistor T217 is small, the distance between the first DATA line DATA210 and the first second connection line N212 is small, and the parasitic capacitance between the first DATA line DATA210 and the first second connection line N212 is large; the distance between the second DATA line DATA220 and the gate of the second initializing transistor T227 is larger, the distance between the second DATA line DATA220 and the second connecting line N222 is larger, and the parasitic capacitance between the second DATA line DATA220 and the second connecting line N222 is smaller; in contrast, different first and second shielding electrode plates S210 and S220 are provided, the first shielding electrode plate S210 has a larger area so as to suppress a larger parasitic capacitance between the first DATA line DATA210 and the first second connection line N212, and the second shielding electrode plate S220 has a smaller area so as to suppress a smaller parasitic capacitance between the second DATA line DATA220 and the second connection line N222.

As shown in fig. 4 to 8, in the embodiment of the present invention, the first pixel circuit PX210 includes a first reference line VREF210 extending in the first direction X; the first reference line VREF210 is located in the third metal layer M230, and the first reference line VREF210 is electrically connected to the source or drain of the first second initialization transistor T217; the first reference line VREF210 is located at a side of the first SCAN line SCAN211 away from the first shielding electrode plate S210.

In the embodiment of the invention, the first reference line VREF210 and the first shielding electrode plate S210 are both located in the third metal layer M230, the area of the first shielding electrode plate S210 is larger, the first reference line VREF210 is not disposed on the side of the first SCAN line SCAN211 close to the first shielding electrode plate S210, but is disposed on the side of the first SCAN line SCAN211 away from the first shielding electrode plate S210, so as to transmit the initialization signal to the first initialization transistor T215 and the first second initialization transistor T217.

As shown in fig. 9 to 13, in the embodiment of the present invention, the second pixel circuit PX220 includes a second reference line VREF220 extending in the first direction X; the second reference line VREF220 is located in the third metal layer M230, and the second reference line VREF220 is electrically connected to the source or drain of the second initialization transistor T227; the second reference line VREF220 is located at a side of the second SCAN line SCAN221 near the second shielding electrode plate S220.

In the embodiment of the invention, the second reference line VREF220 and the second shielding electrode plate S220 are both located in the third metal layer M230, the area of the second shielding electrode plate S220 is smaller, and the second reference line VREF220 may be disposed on the second SCAN line SCAN221 near the second shielding electrode plate S220, so as to transmit the initialization signal to the second initialization transistor T225 and the second initialization transistor T227.

As shown in fig. 16, the present invention provides a display device 300, wherein the display device 300 includes a display panel 200. The display device 300 is an electronic device such as a smartphone or a flat panel television. The display panel 200 is described above and will not be described in detail.

In summary, the present invention provides a display panel and a display device, including: the display device comprises a display area, a first light source and a second light source, wherein the display area comprises a first pixel area and a second pixel area, the first pixel area and the second pixel area are arranged in a first direction, and the distance between the center of the display area and the first pixel area in the first direction is smaller than the distance between the center of the display area and the second pixel area in the first direction; the display panel comprises a plurality of first pixel circuits positioned in the first pixel area and a plurality of second pixel circuits positioned in the second pixel area; the first pixel circuit includes a first data line extending in a second direction, the second pixel circuit includes a second data line extending in the second direction, and the first direction is perpendicular to the second direction; the distance between two first data lines of two first pixel circuits adjacent in the first direction is a first data line distance; the distance between two second data lines of two second pixel circuits adjacent in the first direction is a second data line distance; the first data line pitch is smaller than the second data line pitch. In the present invention, the frame region of the display panel may be narrower.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A display panel, comprising: a display area including a first pixel area and a second pixel area, the first pixel area and the second pixel area being arranged in a first direction, a distance between a center of the display area and the first pixel area in the first direction being smaller than a distance between the center of the display area and the second pixel area in the first direction;

the first data line pitch is smaller than the second data line pitch.

2. The display panel according to claim 1, further comprising a bezel region surrounding the display region;

3. The display panel according to claim 1, further comprising a bezel region surrounding the display region;

4. The display panel according to claim 1, further comprising a bezel region surrounding the display region;

5. The display panel according to claim 4, wherein the third plurality of crossovers comprises a third plurality of crossovers, a third plurality of crossovers;

6. The display panel according to claim 1, wherein the first pixel circuit includes a first a-initialization transistor, a first b-initialization transistor of a single gate, a first a-scan line extending in the first direction;

7. The display panel according to claim 6, wherein the second pixel circuit includes a second initialization transistor, and a second scan line;

8. The display panel according to claim 7, wherein a distance between the gate of the first initialization transistor and the gate of the first second initialization transistor is a first initialization transistor pitch, and a distance between the first gate of the second initialization transistor and the gate of the second initialization transistor is a second initialization transistor pitch;

9. The display panel according to claim 7, wherein the first pixel circuit includes a first power supply line extending in the second direction;

10. The display panel according to claim 9, wherein the second pixel circuit includes a second power supply line extending in the second direction;

11. The display panel according to claim 10, wherein a distance between the first power line and the gate of the first second initialization transistor is a first power line transistor pitch, and a distance between the second power line and the gate of the second initialization transistor is a second power line transistor pitch;

12. The display panel according to claim 10, wherein a distance between the first data line and the first power line is a first data line power line pitch, and a distance between the second data line and the second power line is a second data line power line pitch;

the first data line power line pitch is equal to the second data line power line pitch.

13. The display panel according to claim 9, wherein the first pixel circuit includes a first driving transistor, a first a connection line, a first b connection line;

14. The display panel according to claim 13, wherein the second pixel circuit includes a second driving transistor, a second connecting line, and a second connecting line;

15. The display panel according to claim 14, wherein the first pixel circuit includes a first reference line extending in the first direction;

16. The display panel according to claim 15, wherein the second pixel circuit includes a second reference line extending in the first direction;

17. A display device characterized by comprising the display panel according to any one of claims 1 to 16.