CN116072023A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN116072023A CN116072023A CN202211517513.0A CN202211517513A CN116072023A CN 116072023 A CN116072023 A CN 116072023A CN 202211517513 A CN202211517513 A CN 202211517513A CN 116072023 A CN116072023 A CN 116072023A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
The invention discloses a display panel and a display device. The display panel includes: a display area and a non-display area; the non-display area comprises a detection area; the detection area is provided with a plurality of bonding pads; the plurality of pads includes a plurality of sense pads, a first dummy pad, and a second dummy pad; the display panel comprises a substrate base plate and a thin film transistor layer; the thin film transistor layer is provided with a groove in the detection area; the grooves expose a plurality of detection pads, a first virtual pad and a second virtual pad; the first virtual bonding pad and the second virtual bonding pad are electrically connected through a connecting wire; the connecting wire comprises a first part, a second part and a third part which are connected in sequence; the first part is electrically connected with the first virtual bonding pad; the third part is electrically connected with the second virtual bonding pad; the first portion and the third portion are both parallel to the first direction; the second portion is parallel to the second direction; at least the second portion is covered with an insulating layer. In the embodiment of the invention, the wear rate of the connecting wire is reduced by covering the insulating layer on at least the second part of the connecting wire.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
The display Test (VT) of the display panel is a very important link in the manufacturing process of the display panel, after the display panel is manufactured, the data lines, the grid lines and the common electrode lines are respectively connected to the corresponding Test pads between the binding driving chips, and the flexible circuit board for testing loads corresponding Test signals to enable the display panel to display pictures so as to detect whether each transistor in the display panel is normal or not and whether the wiring of each grid line and each data line is normal or not, thereby preventing bad products from flowing into a module section and causing cost waste.
In the prior art, two virtual bonding pads are arranged in a testing bonding pad for testing in a display panel, connecting wires are connected between the virtual bonding pads, and the virtual bonding pads are used for detecting whether golden fingers of a flexible circuit board for testing aligned with the virtual bonding pads are aligned with the testing bonding pads accurately or not. However, in the prior art, the connecting wire is generally directly exposed, so that when the flexible circuit board for testing is aligned and bound with the testing bonding pad, the exposed connecting wire is easy to break due to contact friction, and the accuracy of the detection result is further affected.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for avoiding the breakage of connecting wires and preventing the detection erroneous judgment of the display panel.
An embodiment of the present invention provides a display panel including: comprises a display area and a non-display area; the non-display area comprises a detection area; the detection area is provided with a plurality of bonding pads; the plurality of pads includes a plurality of sense pads, a first dummy pad, and a second dummy pad;
the display panel includes a substrate base plate and a thin film transistor layer; the thin film transistor layer is provided with a groove in the detection area; the grooves expose a plurality of the detection pads, the first virtual pads and the second virtual pads;
the bonding pads are arranged in parallel along the first direction and arranged along the second direction; the first direction and the second direction intersect; the first virtual bonding pad and the second virtual bonding pad are electrically connected through a connecting wire; the connecting wire comprises a first part, a second part and a third part which are sequentially connected; the first part is electrically connected with the first virtual bonding pad; the third part is electrically connected with the second virtual bonding pad; the first portion and the third portion are both parallel to a first direction; the second portion is parallel to the second direction; at least the second portion is covered with an insulating layer.
In the embodiment of the invention, the insulating layer is covered on at least the second part of the connecting wire of the first virtual bonding pad and the second virtual bonding pad, when the first virtual bonding pad and the second virtual bonding pad of the detection area are connected with the flexible circuit board for testing, the flexible circuit board for testing has friction in the aligning process of the first virtual bonding pad and the second virtual bonding pad, but the insulating layer is covered on at least the second part of the connecting wire of the first virtual bonding pad and the second virtual bonding pad, and the second part of the connecting wire which is most easy to generate the fracture phenomenon is protected by the insulating layer, so that the probability of fracture of the connecting wire can be reduced, and the misjudgment of the aligning result by the flexible circuit board for testing is prevented.
Drawings
FIG. 1 is a schematic diagram of a display panel in the prior art;
fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of the display panel provided in FIG. 2 along the section line A-B;
FIG. 4 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;
FIG. 5 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;
fig. 7 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;
fig. 9 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;
fig. 10 is a schematic top view of a detection area of a display panel according to an embodiment of the present invention;
FIG. 11 is a schematic top view of a detection area of a display panel according to another embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
The display panel provided by the embodiment of the invention comprises a display area and a non-display area; the non-display area comprises a detection area; the detection area is provided with a plurality of bonding pads; the plurality of pads includes a plurality of sense pads, a first dummy pad, and a second dummy pad; the display panel comprises a substrate base plate and a thin film transistor layer; the thin film transistor layer is provided with a groove in the detection area; the grooves expose a plurality of detection pads, a first virtual pad and a second virtual pad; the bonding pads are arranged in parallel along the first direction and in a second direction; the first direction and the second direction intersect; the first virtual bonding pad and the second virtual bonding pad are electrically connected through a connecting wire; the connecting wire comprises a first part, a second part and a third part which are connected in sequence; the first part is electrically connected with the first virtual bonding pad; the third part is electrically connected with the second virtual bonding pad; the first portion and the third portion are both parallel to the first direction; the second portion is parallel to the second direction; at least the second portion is covered with an insulating layer. According to the display panel provided by the embodiment of the invention, the grooves are formed in the detection area of the thin film transistor layer, the grooves expose the detection pads, the first virtual pads and the second virtual pads, and at least the second part of the connecting line of the first virtual pads and the second virtual pads is covered with the insulating layer. When the first virtual pad and the second virtual pad of the detection area are connected with the flexible circuit board of the display panel through the connecting wire, the second part can be protected from being scratched or worn by an external device by covering the insulating layer on at least the second part of the connecting wire.
The foregoing is the core idea of the present invention, and the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without making any inventive effort are intended to fall within the scope of the present invention.
Fig. 1 is a schematic structural diagram of a display panel in the prior art, as shown in fig. 1, the display panel includes a display area 100, the display area 100 is provided with a plurality of data signal lines 101, the non-display area 200 is provided with a plurality of display pads 400, and the display pads 400 are correspondingly connected with the plurality of data signal lines 101 (specific connection is not shown). The display panel further includes a VT detection circuit 102, and the VT detection circuit 102 includes a plurality of thin film transistors 301, DO signal lines, DE signal lines, and SW signal lines. The odd-numbered data signal lines 101 are connected to DO signal lines through the thin film transistor 301, the even-numbered data signal lines 101 are connected to DE signal lines through the thin film transistor 301, and the gate of the thin film transistor 301 is connected to SW signal lines. In VT detection of the display panel, a control signal is supplied to the SW signal line through the detection pad 302, and display signals are supplied to the DO signal line and the DE signal line. The SW signal line controls the thin film transistor 301 to be turned on, charges the odd-numbered data signal lines 101 through the DO signal line, and charges the even-numbered data lines 101 through the DE signal line, thereby performing VT detection. The display pads 400 are used for subsequent bonding with the driving chip, and each detection pad 302 is aligned and connected with each golden finger of the flexible circuit board for testing. However, since the size of each inspection pad 302 and the distance between the inspection pads 302 are relatively small, the inspection pads 302 are likely to be positioned inaccurately by each gold finger of the flexible circuit board for testing. If the golden finger of the flexible circuit board for testing is accurately connected with the position of the detection pad 302, whether each transistor, each grid line and each data line in the display panel are normal or not can be effectively detected through the loaded test signals; if the position connection is inaccurate, a short circuit is easily generated after the test signal is loaded, and the display panel is damaged. Therefore, two dummy pads 303 are further disposed in the non-display area 200, the two dummy pads 303 are connected through a connection line 304, and when the two dummy pads 303 are accurately aligned with corresponding golden fingers of the flexible circuit board for testing, a loop is formed between the two dummy pads 303 and the flexible circuit board for testing, and at this time, an external detection device can output a low level to indicate that the golden fingers of the flexible circuit board for testing are accurately aligned with the detection pads 302. If the two dummy pads 303 are not aligned with the corresponding golden fingers of the flexible circuit board for testing, the circuit between the two dummy pads 303 and the flexible circuit board for testing is broken, and at this time, the external detection device outputs a high level, which indicates that the golden fingers of the flexible circuit board for testing are not aligned with the detection pads 302. Since the connection lines 304 between the inspection pad 302 and the two dummy pads 303 are exposed outside, the connection lines are easily broken when subjected to external friction. If the connecting wire 304 is broken, even if the two dummy pads 303 are accurately aligned with the corresponding golden fingers of the flexible circuit board for testing, a loop cannot be formed between the two dummy pads 303 and the flexible circuit board for testing, and erroneous judgment is caused at this time.
Accordingly, the embodiment of the invention provides a display panel to solve the problem that the connecting wires between the virtual bonding pads are easy to break.
Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and fig. 3 is a schematic structural diagram of a cross section of the display panel provided in fig. 2 along a section line a-B, where, as shown in fig. 2 and fig. 3, the schematic structural diagram of the display panel provided in the embodiment of the present invention includes: comprising a display area 10 and a non-display area 20; the non-display area 20 includes a detection area 30; the detection region 30 is provided with a plurality of pads 300; the plurality of pads 300 includes a plurality of sense pads 310, a first dummy pad 320, and a second dummy pad 330. The plurality of pads 300 are arranged in parallel along the first direction Y and in an array along the second direction X; the first direction Y intersects the second direction X. The first dummy pad 320 and the second dummy pad 330 are electrically connected by the connection line 40; the connecting wire 40 includes a first portion 41, a second portion 42, and a third portion 43 connected in sequence; the first portion 41 is electrically connected to the first dummy pad 320; the third portion 43 is electrically connected to the second dummy pad 330; the first portion 41 and the third portion 43 are both parallel to the first direction Y; the second portion 42 is parallel to the second direction X. The plurality of test pads 310 are used to transmit test signals loaded on the flexible circuit board for testing to the display panel, and the first dummy pads 320 and the second dummy pads 330 are used to test whether to accurately align with the flexible circuit board for testing.
The display panel includes a substrate base 50 and a thin film transistor layer 60; the thin film transistor layer 60 is provided with a groove 70 in the detection region 30; the grooves 70 expose the plurality of sensing pads 310, the first dummy pads 320, and the second dummy pads 330. Since the plurality of pads 300 are required to be bonded to the flexible circuit board for testing during testing, the thin film transistor layer 60 needs to be grooved in the test area 30 to form the grooves 70, and the grooves 70 expose the plurality of test pads 310, the first dummy pads 320 and the second dummy pads 330. In order to meet the development trend of the narrow frame, the first portion 41 and the third portion 43 of the connecting wire 40 are set to be relatively short, and compared with the second portion 42, the second portion 42 is relatively long, so that the second portion 42 is more prone to wear and fracture, and therefore in order to avoid the situation that the connecting wire 40 breaks to cause detection misjudgment, at least the second portion 42 of the display panel provided by the embodiment of the invention is covered with the insulating layer 44. Fig. 2 and 3 illustrate that the first portion 41, the first portion 42, and the third portion 43 of the connecting wire 40 are each covered with an insulating layer 44. The connecting wire 40 is protected by the insulating layer 44, and breakage caused by external friction and scratch is avoided.
It should be noted that, in the embodiment of the present invention, the position of the detection area 30 in the non-display area 20 is not limited, and may be disposed on two sides of the bonding pad of the driving chip, or may be disposed on only one side. In fig. 2, one detection area 30 is exemplarily disposed in the non-display area 20, and one or more detection areas 30 may be disposed according to actual situations, and the number of detection areas 30 is not specifically limited in the embodiment of the present invention.
In addition, the arrangement order of each of the inspection pad 310, the first dummy pad 320, and the second dummy pad 330 is not limited in the embodiment of the present invention. In the exemplary arrangement of the first dummy pad 320 and the second dummy pad 330 of fig. 2, a test pad 310 is spaced between the first dummy pad 320 and the second dummy pad 330, and in other embodiments, the first dummy pad 320 and the second dummy pad 330 may be disposed adjacent to or interposed between the plurality of test pads 310, for example, the first dummy pad 320 and the second dummy pad 330 are arranged adjacent to each other, and no test pad 310 is disposed between the first dummy pad 320 and the second dummy pad 330; a plurality of sensing pads 310 are disposed between the first and second dummy pads 320 and 330; all of the sense pads 310 are disposed between the first and second dummy pads 320 and 330, and so on.
Optionally, fig. 4 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, and referring to fig. 4, the display panel includes a first metal layer 61 and a semiconductor layer 62. The semiconductor layer 62 is located between the first metal layer 61 and the substrate base plate 50. An insulating layer 44 is further provided between the semiconductor layer 62 and the first metal layer 61. The semiconductor layer 62 includes an active layer 621 of a thin film transistor layer and a connection line 40. The connection line 40 is a heavily doped semiconductor layer. The connection line 40 is formed using the same material at the same time as the active layer 621 of the thin film transistor layer 60 is prepared. Since the connection line 40 needs to be conductive, the connection line 40 may be a heavily doped semiconductor layer. For example, after the active layer 621 of the thin film transistor layer 60 and the connection line pattern are formed, the connection line 40 pattern is subjected to a heavily doping process. The first metal layer 61 includes a gate electrode 611 of the thin film transistor layer 60 and a plurality of pads 300. The active layer 621 of the thin film transistor layer 60 and the connection line 40 are arranged in the same layer, and the plurality of pads 300 and the gate 611 of the thin film transistor layer 60 are arranged in the same layer, namely, the active layer 621 of the thin film transistor layer and the connection line 40 are formed by the same material in the same process, and the plurality of pads 300 and the gate 611 of the thin film transistor layer 60 are formed by the same material in the same process, so that the overall thickness of the display device can be reduced, the connection line 40 and the active layer 621 of the thin film transistor layer 60 are arranged in the same layer, only one process is needed, and only one process is needed for arranging the plurality of pads 300 and the gate 611 of the thin film transistor layer 60 in the same layer, therefore, in the manufacturing process, the first metal layer 61 and the semiconductor layer 62 are manufactured by only one etching process, no separate masks are needed, the cost is saved, the manufacturing process is reduced, the production efficiency is improved, and the complexity of the process is reduced.
Note that the first metal layer 61 may include the gate electrode 611 of the thin film transistor layer 60 and the plurality of pads 300, and may also include the source and drain electrodes 612 of the thin film transistor layer 60 and the plurality of pads 300. The connection line 40 is connected to the first dummy pad 320 and the second dummy pad 330 by punching the insulating layer 44. The first metal layer 61 illustrated in fig. 4 may include a gate electrode 611 of a thin film transistor layer and a plurality of pads 300, and in other embodiments, as illustrated in fig. 5, the first metal layer 61 may further include a source drain electrode 612 of the thin film transistor layer 60 and a plurality of pads 300. As shown in fig. 4, the insulating layer 44 between the first metal layer 61 and the semiconductor layer 62 is a gate insulating layer; as shown in fig. 5, the insulating layer 44 between the first metal layer 61 and the semiconductor layer 62 includes a gate insulating layer between the gate electrode and the active layer of the thin film transistor layer and an interlayer insulating layer between the gate electrode and the source drain electrode of the thin film transistor layer.
Alternatively, semiconductor layer 62 comprises polysilicon. The semiconductor layer 62 may be formed, for example, by a low temperature polysilicon process.
Optionally, referring to fig. 6, fig. 6 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, and as shown in fig. 6, the display panel includes a first metal layer 63 and a second metal layer 64; the first metal layer 63 is located between the substrate base 50 and the second metal layer 64; the first metal layer 63 includes the connection line 40; the second metal layer 64 includes a plurality of pads 300; an insulating layer 44 is disposed between the first metal layer 63 and the second metal layer 64, and the first metal layer 63 further includes a light shielding layer 630 of the thin film transistor layer.
The second metal layer 64 further includes a gate 641 of the thin film transistor layer 60; or, the source and drain electrodes 642 of the thin film transistor layer 60 are included. Fig. 6 illustrates that the second metal layer 64 may include the gate electrode 641 of the thin film transistor layer 60 and the plurality of pads 300, and in other embodiments, as shown in fig. 7, the second metal layer 64 may further include the source and drain electrodes 642 of the thin film transistor layer 60 and the plurality of pads 300.
Since the thin film transistor layer 60 can generate a photo-degradation effect under strong illumination intensity, the light shielding layer 630 of the thin film transistor layer 60 is arranged on the first metal layer 63, so that the photo-degradation effect of the thin film transistor under illumination is avoided, the photoelectric conversion rate of the thin film transistor is improved, and the resolution of the display panel is further improved. The light shielding layer 630 and the connecting line 40 are formed by the same material in the same process, so that the number of masks can be reduced, the cost is saved, the production efficiency is improved, and the process complexity is reduced. The insulating layer 44 between the first metal layer 63 and the second metal layer 64 may include one or more insulating layers. As shown in fig. 6, the insulating layer 44 between the first metal layer 63 and the second metal layer 64 includes an insulating layer between the light shielding layer 630 of the thin film transistor layer and the active layer and a gate insulating layer between the active layer and the gate electrode of the thin film transistor layer. As shown in fig. 7, the insulating layer 44 between the first metal layer 63 and the second metal layer 64 includes an insulating layer between the light shielding layer 630 and the active layer of the thin film transistor layer, a gate insulating layer between the active layer and the gate electrode of the thin film transistor layer, and an interlayer insulating layer between the gate electrode of the thin film transistor layer and the drain electrode of the thin film transistor layer.
Optionally, referring to fig. 8, fig. 8 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, where, as shown in fig. 8, the display panel includes a first metal layer 63 and a second metal layer 64; the first metal layer 63 is located between the substrate base 50 and the second metal layer 64; an insulating layer 44 is provided between the first metal layer 63 and the second metal layer 64; the first metal layer 63 includes a gate electrode 631 of the thin film transistor layer and a connection line 40; the second metal layer 64 includes a source and drain electrode 642 of the thin film transistor layer and a plurality of pads 300.
The gate electrode 631 and the connection line 40 of the thin film transistor layer are provided in the first metal layer 63, and the source/drain electrode 642 and the plurality of pads 300 of the thin film transistor layer are provided in the second metal layer 64. The gate 631 and the connecting line 40 of the thin film transistor layer are formed by the same material in the same process, and the source drain 642 and the plurality of pads 300 of the thin film transistor layer are formed by the same material in the same process, so that the number of masks can be reduced, the cost can be saved, the production efficiency can be improved, and the process complexity can be reduced. As shown in fig. 8, the insulating layer 44 between the first metal layer 63 and the second metal layer 64 includes a gate insulating layer between the active layer of the thin film transistor layer and the gate electrode of the thin film transistor layer and an insulating layer between the gate electrode of the thin film transistor layer and the source and drain electrodes of the thin film transistor layer.
Optionally, the first portion 41, the second portion 43 and the third portion 42 are covered with an insulating layer 44.
In the embodiment of the invention, for example, the first portion 41, the second portion 42 and the third portion 43 of the connecting wire 40 are covered with the insulating layer 44, so that the phenomenon that the connecting wire 40 is broken due to alignment friction in the process of connecting and aligning the first virtual bonding pad 320 and the second virtual bonding pad 330 with the flexible circuit board is avoided, and the accuracy of the detection result is further improved.
Optionally, referring to fig. 9, fig. 9 is a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, as shown in fig. 9, the display panel includes a first metal layer 65; the first metal layer 65 includes the connection line 40 and the plurality of pads 300; the first metal layer 65 further includes a gate electrode, a source drain electrode, or a light shielding layer of the thin film transistor layer.
It should be noted that, the first metal layer 65 illustrated in fig. 9 includes the connection line 40, the plurality of pads 300, and the gate electrode 652 of the thin film transistor layer 60, that is, the connection line 40, the plurality of pads 300, and the gate electrode 652 of the thin film transistor layer are formed using the first metal layer 65. In other embodiments, the first metal layer 65 may further include the connection line 40, the plurality of pads 300, and the source/drain electrode of the thin film transistor layer 60, or the first metal layer 65 may include the connection line 40, the plurality of pads 300, and the light shielding layer, which are not described herein.
Optionally, fig. 10 is a schematic top view of a detection area of a display panel according to an embodiment of the present invention, in which a plurality of bonding pads 300 are aligned with corresponding golden fingers on a flexible circuit board for testing, and therefore, grooves 70 are required to be provided to expose the plurality of bonding pads 300, so that vertical projections of the plurality of bonding pads 300 on a substrate 50 are located in vertical projections of the grooves 70 on the substrate 50, so that the plurality of bonding pads 300 and the corresponding golden fingers on the flexible circuit board for testing can be fully aligned and contacted.
Alternatively, as shown in fig. 10, the boundary of the groove 70 may also coincide with a partial boundary of the plurality of pads 300. By providing the boundary of the groove 70 to coincide with the partial boundaries of the plurality of pads 300, the entire connecting line 40 is covered with an insulating layer, and the connecting line 40 is protected from external friction damage or scratches of the device.
Optionally, referring to fig. 11, fig. 11 is a schematic top view of a detection area of another display panel according to an embodiment of the present invention, as shown in fig. 11, a portion of the first portion 41 and a portion of the second portion 42 are exposed by the groove 70. In order to meet the development trend of the narrow frame, the first portion 41 and the third portion 43 of the connecting wire 40 are set to be relatively short, and compared with the second portion 42 being relatively long, the second portion 42 is more prone to wear and fracture, so that the second portion 42 is only required to be covered with an insulating layer, and the groove 70 can expose part of the first portion 41 and part of the second portion 42. In addition, since errors may occur in the manufacturing process of the groove 70, resulting in a deviation of the position of the groove 70, if the size of the groove 70 is too small, there may occur a case where the deviation of the position of the groove 70 in the process causes the groove 70 to fail to completely expose the plurality of pads 300, and thus the size of the groove 70 in the extending direction of the pads 300 may be set to be larger than the size of the pads 300, if the manufacturing process of the groove 70 is accurate, a part of the first portion 41 and a part of the second portion 42 may be exposed from the groove 70. In addition, in order to make the golden finger of the FPC for detection sufficiently contact with the plurality of pads 300, it is also necessary to appropriately enlarge the opening of the groove 70, and at this time, part of the first portion 41 and part of the second portion 42 are exposed by the groove 70.
On the basis of the above embodiments, fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 12, the display device may include the display panel 11 according to any embodiment of the present invention. It should be noted that, the display device provided in the embodiment of the present invention may be a display device of a computer, a television, an intelligent wearable device, or other display devices, which is not limited in particular.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (11)
1. A display panel, comprising a display area and a non-display area; the non-display area comprises a detection area; the detection area is provided with a plurality of bonding pads; the plurality of pads includes a plurality of sense pads, a first dummy pad, and a second dummy pad;
the display panel includes a substrate base plate and a thin film transistor layer; the thin film transistor layer is provided with a groove in the detection area; the grooves expose a plurality of the detection pads, the first virtual pads and the second virtual pads;
the bonding pads are arranged in parallel along the first direction and arranged along the second direction; the first direction and the second direction intersect; the first virtual bonding pad and the second virtual bonding pad are electrically connected through a connecting wire; the connecting wire comprises a first part, a second part and a third part which are sequentially connected; the first part is electrically connected with the first virtual bonding pad; the third part is electrically connected with the second virtual bonding pad; the first portion and the third portion are both parallel to a first direction; the second portion is parallel to the second direction;
at least the first portion and at least the second portion are covered with an insulating layer;
the perpendicular projection of a plurality of the bonding pads on the substrate is overlapped with the perpendicular projection of the grooves on the substrate.
2. The display panel of claim 1, wherein the display panel comprises a first metal layer and a semiconductor layer;
the semiconductor layer is positioned between the first metal layer and the substrate base plate;
an insulating layer is further arranged between the semiconductor layer and the first metal layer;
the semiconductor layer includes an active layer of the thin film transistor layer and the connection line; the connecting wire is heavily doped with the semiconductor layer;
the first metal layer comprises a grid electrode of the thin film transistor layer and a plurality of bonding pads; or the first metal layer comprises a source electrode and a drain electrode of the thin film transistor layer and a plurality of bonding pads.
3. The display panel of claim 2, wherein the semiconductor layer comprises polysilicon.
4. The display panel of claim 1, wherein the display panel comprises a first metal layer and a second metal layer;
the first metal layer is positioned between the substrate base plate and the second metal layer; the first metal layer comprises the connecting wire; the second metal layer comprises a plurality of bonding pads; an insulating layer is arranged between the first metal layer and the second metal layer; the first metal layer further comprises a light shielding layer of the thin film transistor layer;
the second metal layer further comprises a gate electrode of the thin film transistor layer; or the source electrode and the drain electrode of the thin film transistor layer are included.
5. The display panel of claim 1, wherein the display panel comprises a first metal layer and a second metal layer;
the first metal layer is positioned between the substrate base plate and the second metal layer; an insulating layer is arranged between the first metal layer and the second metal layer;
the first metal layer comprises a grid electrode of the thin film transistor layer and the connecting wire;
the second metal layer comprises a source electrode and a drain electrode of the thin film transistor layer and a plurality of bonding pads.
6. The display panel according to any one of claims 2 to 5, wherein the first portion, the second portion, and the third portion are each covered with an insulating layer.
7. The display panel of claim 1, wherein the display panel comprises a first metal layer;
the first metal layer comprises the connecting wire and a plurality of bonding pads;
the first metal layer further comprises a grid electrode, a source electrode and a drain electrode or a shading layer of the thin film transistor layer.
8. The display panel of claim 7, wherein the recess exposes a portion of the first portion and a portion of the second portion.
9. The display panel of claim 1, wherein a perpendicular projection of a plurality of the bonding pads onto the substrate is within a perpendicular projection of the groove onto the substrate. .
10. The display panel of claim 9, wherein a boundary of the recess coincides with a partial boundary of the plurality of pads.
11. A display device comprising the display panel of any one of claims 1-10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211517513.0A CN116072023A (en) | 2019-12-17 | 2019-12-17 | Display panel and display device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211517513.0A CN116072023A (en) | 2019-12-17 | 2019-12-17 | Display panel and display device |
| CN201911304999.8A CN110827732B (en) | 2019-12-17 | 2019-12-17 | Display panel and display device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911304999.8A Division CN110827732B (en) | 2019-12-17 | 2019-12-17 | Display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116072023A true CN116072023A (en) | 2023-05-05 |
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| CN111596476B (en) * | 2020-06-29 | 2022-08-19 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN113848664B (en) * | 2021-09-24 | 2023-10-20 | 京东方科技集团股份有限公司 | Driving backboard, manufacturing method thereof, light-emitting substrate and display device |
| CN114241914B (en) * | 2021-12-21 | 2024-02-20 | 上海中航光电子有限公司 | Display panel and display device |
| CN114706238B (en) * | 2022-03-03 | 2024-04-26 | 滁州惠科光电科技有限公司 | Array substrate mother board, preparation method thereof and display panel mother board |
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| KR100671640B1 (en) * | 2004-06-24 | 2007-01-18 | 삼성에스디아이 주식회사 | Thin film transistor array substrate and display using the same and fabrication method thereof |
| WO2014046099A1 (en) * | 2012-09-24 | 2014-03-27 | シャープ株式会社 | Image display apparatus and mounting inspection method for same |
| JP6665457B2 (en) * | 2015-09-16 | 2020-03-13 | 富士電機株式会社 | Semiconductor device |
| CN107329336B (en) * | 2017-07-11 | 2020-09-25 | 厦门天马微电子有限公司 | Display substrate, display panel and display device |
| KR102435975B1 (en) * | 2017-08-18 | 2022-08-24 | 삼성디스플레이 주식회사 | Display device |
| CN109659304A (en) * | 2017-10-12 | 2019-04-19 | 上海和辉光电有限公司 | A kind of array substrate, display panel and display device |
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