JP2856201B2 - Pachinko machine - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pachinko machine using a computer. 2. Description of the Related Art Some recent pachinko machines use a computer to electronically control the winning probability of a ball. In such a pachinko machine, in order to determine a hit mode, an event that depends on contingency is generated, a hit mode is determined from the event, and the development of a more complicated game is controlled in accordance with the hit mode. ing. However, the output devices such as the light emitting device and the sound emitting device perform only simple controls such as single sound and single light emission. There is a demand for control. [0003] However, in the conventional pachinko machine, the processing capacity is becoming saturated due to the control mainly of such complicated game development, and the program development is advanced by one person. I had to. For this reason, in controlling the output devices such as the sounding device and the light emitting device, more complicated control, for example, depending on the progress of the game, each sound is composed of more musical sounds, and continuous music having a melody is played. It is difficult to perform output or control to generate complicated illumination. In addition, since the control target of the computer becomes complicated and increasing in this way, the control program becomes long, and the capacity of a storage device for storing the control program also needs to be increased. However, in pachinko machines, the capacity of the storage device is limited due to the regulations of the organization that monitors fraud. For this reason, under the regulation of the limitation of the storage capacity, it is required to perform more complicated and more control. On the other hand, in pachinko machines, the number of CPUs used is not limited, but there is little necessity to process a large amount of work at high speed, and a plurality of CPUs are not used in pachinko machines. Furthermore, in order to increase the processing speed, a plurality of CPs are used in the field of computer equipment.
In the case of using U, it is common to operate each CPU independently and in parallel. While one is operating, the other stops operating, and while the other is operating, one of the operations stops. There is no proposal for use in which an alternate operation of stopping the operation is performed in a short cycle. Therefore, an object of the present invention is to enable more complicated and more processes without increasing the storage capacity due to the limitation of the storage capacity. Means for Solving the Problems The structure of the present invention for solving the above problems is as follows. That is, the present invention provides a winning detection device that detects a winning of a ball in a specific winning opening, determines a winning mode in accordance with the winning in the specific winning opening, and sets a ball to the winning opening in accordance with the mode. In a pachinko machine having a control device for controlling a winning probability of the game and a peripheral device such as a light emitting device and a sound generating device, the control device is a one-chip micro-computer in which a plurality of central processing units are formed on one chip. Made up of computers and before
The pachinko machine also has one clock generation circuit.
The clock generation circuit includes the plurality of central processing units.
It is characterized in that it is a configuration shared by .
The division of labor of the plurality of central processing units includes, for example, the following means. The first is a method in which one central processing unit controls the winning probability, mainly manages the progress of the game of the pachinko machine, and another central processing unit performs other work. Second,
This is a method in which one central processing unit controls at least one of a sound emitting device, a light emitting device, and another output device, and another central processing device performs another task. Third, one central processing unit generates an event that depends on contingency in response to a winning in a specific winning opening, performs a process of determining a hit mode from the event, and performs another job in another central processing unit. This is the method performed by the device. The first central processing unit of the one-chip microcomputer is used, for example, for main processing for controlling the progress of a game, and the other central processing units are a sound emitting device, a light emitting device, and other peripheral devices. Used for sub-processing to control the device. Each of the central processing units can use the storage device exclusively or in common, so that it can store its own program, manage common data in common, and simplify the processing of complicated games. . In addition, since real-time parallel processing becomes possible, for example, management of the progress of the game and management of the output device can be performed separately in parallel. Therefore, more detailed and complicated control can be performed. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on specific embodiments. In this embodiment, one of the dual CPUs is used for control for generating various melodies according to the state of the game, and the other CPU is used for managing the progress of the game. FIG. 2 is an external view showing the mechanism of the pachinko machine. Reference numeral 50 denotes a frame, and the game board 51 is supported by the frame 50. The game board 51 is provided with various winning ports, of which 52, 53, and 54 are specific winning ports, and when the specific winning port is won, a combination operation for determining a winning mode is started. . 56, 57,
58, 59, 60 are ordinary winning openings, 61, 62
Is a winning opening with a tulip-style character. Reference numeral 63 denotes a special winning opening which is opened and closed in accordance with the hit mode. The opening and closing door 64 is opened and closed by a solenoid 41 provided therein. Also, in the center of the big winning opening,
A V winning opening 63 is provided, and when a winning is made at the winning opening, the opening / closing door 64 generates a continuation right to open and close continuously. In the center of the game board 51, a numerical display 27 for displaying a combination state of coincidence when a ball is won in the specific winning openings 52, 53, 54, and a lamp display 2
9 are provided. Numerical display 27 is a 3-digit LED
The indicator 29 is a lamp in which red and blue LEDs are cyclically arranged. When a specific winning opening is won, in order to determine the winning mode, each digit of the three digits and the lighting LED of the lamp display 29 are displayed.
The winning modes are determined by a combination when they rotate at different periods and come to a standstill, and the opening time of the opening and closing door 64 of the special winning opening 63 is controlled according to the mode. In addition, the game board 51 is provided with various indicators and lamps for displaying an operation state. Reference numeral 30 in the center is a stored number display for displaying the number of balls that have won a specific winning opening and have been suspended. 4
Reference numerals 7a to 47j denote operation lamps that blink during the combination operation for determining the winning mode. 43a-43c
Is a panic lamp that flashes with the lamps 47a to 47j at the time of a big hit. Reference numerals 45a to 45c denote V lamps which blink when there is a winning in the V winning opening 63. FIG. 1 is a block diagram showing an electrical configuration of the apparatus according to the present embodiment. As the control device, a dual one-chip microcomputer 1 (hereinafter, referred to as "dual computer") is used. The dual computer 1 has two central processing units, a CPU 1 and a CPU 2, and can access an internal ROM and an internal RAM from both. Each CPU automatically and alternately executes one step at a time according to its own program (auto-swap mode), or controls the other CPUs under program control of the operating CPU.
(Program swap mode). An external ROM 3 and an external RAM 5 are connected to the dual computer 1 so as to be accessible from both CPUs. A winning detection switch 7 for detecting a winning ball in a special winning opening, a special winning opening winning switch 9 for detecting a winning ball in a special winning opening, and a V winning detection switch 11 for detecting a winning ball in a V winning opening prevent chattering. Connected to the dual computer 1 via a waveform shaping circuit 13 composed of flip-flops for performing the operation. The above-mentioned switch is constituted by a limit switch, and is arranged on a rail for guiding a winning ball from each winning opening. The clock generation circuit 17 is 4 MHz
Is output to the dual computer 1 and a signal is output to the frequency divider 15. Frequency divider 15
Divides the clock signal and outputs an external interrupt signal having a period of 4.096 msec to the dual computer 1. The main control of the dual computer 1 is started in synchronization with this interrupt signal. Reference numeral 21 denotes a power supply circuit. The signal of the start switch 23 is input to the reset signal generation circuit 19, and the reset signal, which is the output signal, is input to the reset terminal of the dual computer 1. The program is executed. Each output port of the dual computer 1 is connected to a display drive circuit 25, a display selection circuit 31, a software controlled sound generator (hereinafter simply referred to as "SSG") 33, and a driver 39. The numerical value display 27, the lamp display 29, and the stored number display 30 are connected to the display drive circuit 25 and the display selection circuit 31. These displays are dynamically driven by outputting selected data and display data from the dual computer 1 at regular intervals. That is, each display unit is selected by the display selection circuit 31 and is displayed according to the output signal of the display drive circuit 25 at that time. SSG
33 inputs control data for sound output from the dual computer 1 to each register, D / A converts a waveform created based on the control data, and outputs the converted waveform to the speaker 35. The driver 39 drives the solenoid 41 in response to a signal from the dual computer 1 and controls the lighting operation of the panic lamp 43, the V lamp 45, and the operation lamp 47. Next, the operation of the pachinko machine having such a configuration will be described with reference to a flowchart showing the processing procedure of the dual computer 1. (1) When the initial set start switch 23 at the time of power-on is turned on, power is supplied to the dual computer 1 and the reset signal generation circuit 19
Outputs a reset signal S4 to a reset terminal. Then, the CPU 1 executes the processing shown in FIG. That is, the numerical display registers X1, X2, and X3 storing the three-digit numerical values to be displayed on the numerical display 27 are set to the initial values, and the display lamp register L storing the lighting lamp of the lamp display 29 is set. Set to the initial value. Also, a winning prize ball counter C for counting the number of prize balls that have been won and held in the specific prize port is set to zero, and a special prize port winning counter G for counting the number of prize balls to the special winning port is set to zero. A V winning ball counter A for counting the number of winning balls to the winning port is initialized to zero. The state register F storing the control state is initialized to zero, the hit mode register R storing the hit mode is initialized to zero, and the timers T1, T2 and T3 are initialized to zero. Further, the swap flag S storing the swap state of the CPU 1 and the CPU 2 is reset. (2) Every time an external interrupt signal is input at regular time intervals (4.096 msec) after the background processing initial setting, the CPU 1
And the program of FIG. 5 is executed. In step 100,
The timer is updated, and the state signals S1, S2, and S3 of the switch group are read in step 102. These state signals are constituted by negative logic, and when the signal is at a low level, the switch is turned on. Indicates that a winning ball has been detected. Therefore, steps 104, 1
The falling of each state signal is detected at 10, 114, and only at that time, each counter C, G, A is updated by one. However, the number of winning balls held is determined in step 106 by
Only count up to four. Step 118
Steps 166 to 166 are processing steps corresponding to each state. Steps 170 to 192 are processing steps of the output device. When the hit mode register R is 0, the solenoid 41 is turned off, so that the special winning opening is closed or the closed state is maintained. When the register R is other than 0, the solenoid 41 is turned on, so that the special winning opening is opened or kept open (steps 170 to 174). That is, depending on the contents of the register R,
The opening and closing of the special winning opening is controlled. The numerical display 27 displays the values of the registers X1, X2, X3, and the lamp display 29.
Turns on the LED specified by the register L (step 176). When the register F is 1, that is, during the combination operation, the operation lamp 47 blinks, and when the register F is 2,
That is, when the special winning opening is open, the operation lamp 47 and the panic lamp 43 blink, and when the register F is 2 and the counter A is not 0, that is, when there is a V winning ball, the V lamp 45 is turned on. Is lit. Further, the value of the counter C is displayed on the stored number display 30 (step 178). Steps 180 to 192 are executed according to the presence or absence of sound control.
This is a step for driving and stopping U2 in the auto swap mode. At the time of sound control, that is, when the register F is other than 0, the swap flag S is set and auto-swap is started.
U2 will operate alternately one step at a time. When the register F becomes 0, the tone generation control is stopped, the swap flag S is reset, the auto swap is stopped, and thereafter, only the CPU 1 operates. (3) Processing when there is no winning ball When there is no winning ball, that is, when the counter C is 0, the processing of steps 100 to 124 and 170 to 192 is performed, whereby the numerical value is set. The display, the lamp display, and each lamp group perform a predetermined display. (4) When a winning ball exists (C ≠ 0) (a) The value of the counter C is determined in the combination operation processing step 124, and when a winning is detected, the value of the counter C is decremented by one. The register F is set to 1 to indicate the combination operation state, and the timer T1 is set to a predetermined value (steps 124 to 130). Then, in step 132, a random number generation process is performed, and the generated random numbers are stored in the registers X1, X2, X3, and L. Until the time is up in step 134, step 100
To 118, 132, 134, and 170 to 192 are repeated. The setting of the random numbers is performed every time the process passes through step 132. When the time is up, in step 136, the registers X1, X2, X3, L
Is set in the register R, and the mode is set in the register R. 0 is out, 1 is small hit, 2 is medium hit, and 3 is big hit. If it is off, the register F is set to 0, and the process proceeds to the cycle for determining the next winning ball. (B) Winning process When the result of the determination in step 136 is a hit, a time is set in the timer T2 according to the hit mode. Then, the background processing described above is performed until it is determined that the time is up. As a result, the special winning opening is opened for a predetermined time, the lamp group is displayed to indicate a panic state, and music in a panic state is played from the speaker 35. At this time, if the number of winning balls in the special winning opening reaches 10, the same processing as the time-up is performed even before the time-up. That is, the counter G is set to 0 and the register R is set to 0 (steps 150 and 152). (C) Processing when a V Win Ball Exists The V win ball exists when the large winning opening is open, that is,
If the counter A is not 0 (step 156), step 1
At 58, the value of the register F is set to 3 to indicate the generation of the continuation right. Then, the counter A is decremented by 1, and the timer T3
Is set to a predetermined time, and time up is determined (steps 158 to 164). This processing is for giving a certain delay until the special winning opening is subsequently opened. Thereafter, in step 166, the register R is set to 3 indicating a big hit, and the process proceeds to step 142 to perform the above-mentioned hit processing. However, the continuation right is adjusted in step 152 so as not to occur more than ten times. (5) Processing for sound generation control In the background processing of steps 180 to 192, it is determined that the state is sound generation control.
The PU 2 executes the processing of FIG. 6 in parallel with the processing of the CPU 1 macroscopically. In step 200, the sound generation mode is determined from the values of the status register F, the winning ball counter C, the winning mode register R, the special winning opening winning counter G, and the V winning ball counter A, and the value is set in the register W. The ROM 3 stores a control data group for outputting a different melody for each tone generation mode, as shown in FIG. The control data includes a set of sounding data such as a sound frequency, a sound volume, and an envelope, and time data indicating the sounding continuation time of the sound. In step 202, it is determined whether or not the tone generation mode has changed based on the change in the value of the register W. If there has been a change, the process proceeds to step 204, where the head address storing the control data group in that mode is set as the data pointer. Set to P. Next, step 206
To store the contents of the address indicated by data point P in ROM
3 and if it is not the end code of the data, at step 210, time data is set in the timer based on the control data. Next, in step 212, the pronunciation data is
By outputting to each register of G33, the speaker 3
From 5 onward, one sound is generated until it is determined in step 214 that the time is up. Next, when it is determined in step 214 that the time is up, the process proceeds to step 216, where the data pointer P is updated to the address of the next control data, and the process returns to step 200. If it is determined in step 202 that there is no change in the sounding mode, the initial setting of the address is jumped, so that sounding data of the next sound in the mode is input. As described above, in the present embodiment, one of the two CPUs of the dual computer is used for the main control of the pachinko machine, and the other CPUs are dedicated to the control of the sounding device, which has complicated control. Used in Therefore, it is only necessary to develop an independent program for each, so that the production is simple. Further, the CPU 2 can be used for controlling a lamp group. As shown in FIG. 8, the control data includes, as a set of light emission data designating which one of a plurality of lamps is to be turned on, and time data for maintaining the state, as a set of data. It is created for each light emission mode. The processing procedure of the CPU 2 is the same as that of FIG.
By replacing 04 with the setting of the initial address corresponding to the light emission mode, Step 210 with the setting of the time data, and Step 212 with the output of the light emission data, dynamic light emission control according to the control data is possible. Further, the CPU 2 can be used for addition of the number of times of driving the numerical value display, the number of times of opening the special winning opening in the big hit mode, and other statistical processing. According to the present invention, the game development of the pachinko machine,
First and second central processing units are formed on a single chip as a control device for controlling the input / output device, and the two central processing units alternately operate at minute intervals and operate in parallel in a macro manner. It is characterized by comprising a one-chip microcomputer and providing a common storage device accessible from the first central processing unit and the second central processing unit. Therefore, the two central processing units can execute in parallel while sharing necessary data according to their own processing programs, so that different jobs can be processed simultaneously. For this reason, it becomes possible to make the game development of the pachinko machine more complicated, to output a melody composed of complicated musical sounds in parallel with the progress of the game, and to realize lighting that fluctuates in a complicated manner, More entertaining can be improved. In addition, the development of the program can be performed independently of each other without being influenced by the programs of the other central processing units. Therefore, the development of the game program and the development of the program such as the sound control can be performed by the respective specialists, and the development of the device becomes easy. Further, if a single CPU executes a parallel operation of tasks, a stack area for saving a program and data of a register for a task switching process such as a save process of a register or the like is required. If the two CPUs are operated alternately at regular time intervals,
Since each CPU executes each task intermittently, there is no need to spare the CPU for execution of other tasks. As a result, the stack area for saving the program for the task switching process and the data of the register is not required, so that the capacity of the storage device can be saved. Also, two C
By alternately executing PUs, a single storage device can be used,
Since the data can be shared by the two CPUs and the data storage area can be shared, the capacity of the storage device can be saved. From these facts, even if the storage capacity is limited, more work can be performed and each C
You only have to develop a program specific to the PU,
System design becomes easier.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an electrical configuration of a pachinko machine according to a specific embodiment of the present invention. FIG. 2 is a plan view showing the appearance of the pachinko machine of the embodiment. FIG. 3 is a flowchart showing a processing procedure of a dual one-chip microcomputer used in the pachinko machine of the embodiment. FIG. 4 is a flowchart showing a processing procedure of a dual one-chip microcomputer used in the pachinko machine of the embodiment. FIG. 5 shows a processing procedure of a dual one-chip microcomputer used in the pachinko machine of the embodiment.
Flowchart that follows. FIG. 6 is a flowchart showing a processing procedure of a dual one-chip microcomputer used in the pachinko machine of the embodiment. FIG. 7 is a structural diagram showing a structure of control data for sound generation control. FIG. 8 is a structural diagram showing a structure of control data for controlling a light emitting device of a pachinko machine according to another embodiment. [Description of Signs] 27 Numerical Display 29 Lamp Display 30 Memory Number Display 43a to 43c Panic Lamp 45a to 45c V Lamp 47a to 47j Operation Lamp 50 Frame 51 Play Board 52, 53 , 54: specific winning opening 63: large winning opening 64: opening / closing door 65: V winning opening

Claims (1)

(57) [Claims] A winning detection device for detecting a winning of a ball in a specific winning opening is provided, a winning mode is determined according to a winning in the specific winning opening, and a winning probability of a ball to the winning opening is controlled in accordance with the mode. In addition, in a pachinko machine including a control device for controlling peripheral devices such as a light emitting device and a sound generating device, the control device is configured by a one-chip microcomputer in which a plurality of central processing units are formed on one chip.
The pachinko machine further includes one clock generation circuit.
The clock generation circuit is shared by the plurality of central processing units.
A pachinko machine characterized in that it is used.