JP2894349B2 - Pachinko machine - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pachinko machine using a computer. 2. Description of the Related Art Some recent pachinko machines use a computer to electronically control the winning probability of a ball. In such a pachinko machine, in order to determine a hit mode, an event that depends on contingency is generated, a hit mode is determined from the event, and the development of a more complicated game is controlled in accordance with the hit mode. ing.
However, the output devices such as the light emitting device and the sound emitting device perform only simple controls such as single sound and single light emission. There is a demand for control. [0003] However, in the conventional pachinko machine, the processing capacity is becoming saturated due to the control mainly of such complicated game development, and the program development must be advanced by one person. I had to. For this reason, in controlling the output devices such as the sounding device and the light emitting device, more complicated control, for example, depending on the progress of the game, each sound is composed of more musical sounds, and continuous music having a melody is played. It is difficult to perform output or control to generate complicated illumination. In addition, since the control target of the computer becomes complicated and increasing as described above, the control program becomes longer, and the capacity of a storage device for storing the control program also needs to be increased. However, in pachinko machines, the capacity of the storage device is limited due to the regulations of the organization that monitors fraud. For this reason, under the regulation of the limitation of the storage capacity, it is required to perform more complicated and more control. On the other hand, in a pachinko machine, the number of CPUs to be used is not limited, but there is little necessity that a large amount of work must be processed at high speed, and a plurality of CPUs are used in a pachinko machine. no. Therefore, an object of the present invention is to enable more complicated and more processes without increasing the storage capacity due to the limitation of the storage capacity. Means for Solving the Problems The constitution of the present invention for solving the above problems is as follows. That is, the present invention provides a winning detection device that detects a winning of a ball in a specific winning opening, determines a winning mode in accordance with the winning in the specific winning opening, and sets a ball to the winning opening in accordance with the mode. In a pachinko machine having a control device for controlling a winning probability of the game and a peripheral device such as a light emitting device and a sound generating device, the control device is a one-chip micro-computer in which a plurality of central processing units are formed on one chip. The pachinko machine further comprises one or a plurality of memories, and at least one of the memories is shared by the plurality of central processing units. It is. The division of labor of the plurality of central processing units includes, for example, the following means. The first is a method in which one central processing unit controls the winning probability, mainly manages the progress of the game of the pachinko machine, and another central processing unit performs other work. Second, one central processing unit is a sound emitting device, a light emitting device,
This is a method in which at least one of the other peripheral devices is controlled and another task is performed by another central processing unit. [0009] [act first central processing unit of word-chip microcomputer, for example, used in the main process of controlling the progress of the game, the other central processing unit, sound generating device, light emitting device, other Used for sub-processing for controlling peripheral devices. Each central processing unit, because it can use a memory in common manner, it is possible to manage common data in common, can be simplified processing of complex games. In addition, since the real-time parallel processing is possible, for example, management and progress of the game, can be carried out by division of labor in parallel with the management and of the peripheral device. Therefore, more detailed and complicated control can be performed . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on specific embodiments. In this embodiment, one of the dual CPUs is used for control for generating various melodies according to the state of the game, and the other CPU is used for managing the progress of the game. FIG. 2 is an external view showing the mechanism of the pachinko machine. Reference numeral 50 denotes a frame, and the game board 51 is supported by the frame 50. The game board 51 is provided with various winning ports, of which 52, 53, and 54 are specific winning ports, and when the specific winning port is won, a combination operation for determining a winning mode is started. . 56, 57,
58, 59, 60 are ordinary winning openings, 61, 62
Is a winning opening with a tulip-style character. Reference numeral 63 denotes a special winning opening which is opened and closed in accordance with the hit mode. The opening and closing door 64 is opened and closed by a solenoid 41 provided therein. Also, in the center of the big winning opening,
A V winning opening 63 is provided, and when a winning is made at the winning opening, the opening / closing door 64 generates a continuation right to open and close continuously. At the center of the play board 51, a specific winning opening 5 is provided.
When a ball is won at 2, 53, 54, a numerical display 27 for displaying a combination state of chance and a lamp display 29 are provided. The numerical display 27 is a three-digit LED display, and the lamp display 29 is a lamp in which red and blue LEDs are cyclically arranged. When a special winning opening is won, the three-digit numerical value and the lighting LED of the lamp display 29 are rotated at different periods to determine the winning mode, and they are stationary. The winning mode is determined by the combination at the time of, and the opening time of the opening and closing door 64 of the special winning opening 63 is controlled according to the mode. The game board 51 is provided with various indicators and lamps for displaying an operation state. Reference numeral 30 in the center is a stored number display for displaying the number of balls that have won a specific winning opening and have been suspended.
47a to 47j are operation lamps that blink during the combination operation for determining the winning mode. 43a-43
c is a panic lamp that blinks with the lamps 47a to 47j at the time of a big hit. 45a-45c is V
This is a V lamp that flashes when there is a winning in the winning opening 63. FIG. 1 is a block diagram showing an electrical configuration of the apparatus according to the present embodiment. As the control device, a dual one-chip microcomputer 1 (hereinafter, referred to as "dual computer") is used. The dual computer 1 has two central processing units, a CPU 1 and a CPU 2, and can access an internal ROM and an internal RAM from both. Each CPU automatically and alternately executes one step at a time according to its own program (auto-swap mode), or controls the other CPUs under program control of the operating CPU.
(Program swap mode). The dual computer 1 has an external R
The OM 3 and the external RAM 5 are connected so as to be accessible from both CPUs. A winning detection switch 7 for detecting a winning ball in a special winning opening, a special winning opening winning switch 9 for detecting a winning ball in a special winning opening, and a V winning detection switch 11 for detecting a winning ball in a V winning opening prevent chattering. Connected to the dual computer 1 via a waveform shaping circuit 13 composed of flip-flops for performing the operation. The above-mentioned switch is constituted by a limit switch, and is arranged on a rail for guiding a winning ball from each winning opening. The clock generation circuit 17 outputs a 4 MHz clock signal to the dual computer 1 and
The signal is output to the frequency divider 15. The frequency divider 15 divides the frequency of the clock signal and outputs an external interrupt signal having a period of 4.096 msec to the dual computer 1. The main control of the dual computer 1 is started in synchronization with this interrupt signal. Reference numeral 21 denotes a power supply circuit. The signal of the start switch 23 is input to the reset signal generation circuit 19, and the reset signal, which is the output signal, is input to the reset terminal of the dual computer 1. The program is executed. Each output port of the dual computer 1 is connected to a display drive circuit 25, a display selection circuit 31, a software controlled sound generator (hereinafter simply referred to as "SSG") 33, and a driver 39. I have. The numerical value display 27, the lamp display 29, and the stored number display 30 are connected to the display drive circuit 25 and the display selection circuit 31. These indicators are
The selection data and the display data are output from the dual computer 1 at a fixed period, and are dynamically driven. That is, each display unit is selected by the display selection circuit 31 and is displayed according to the output signal of the display drive circuit 25 at that time. SSG33 is a dual computer 1
, Control data for sound output is input to each register, and a waveform created based on the control data is stored in a D / A
It is converted and output to the speaker 35. Driver 39
Drives the solenoid 41 in response to a signal from the dual computer 1, and drives the panic lamp 43 and the V lamp 4
5. The lighting operation of the operation lamp 47 is controlled. Next, the operation of the pachinko machine having the above configuration will be described with reference to a flowchart showing the processing procedure of the dual computer 1. (1) When the initial set start switch 23 is turned on when the power is turned on, power is supplied to the dual computer 1 and the reset signal generation circuit 19
Outputs a reset signal S4 to a reset terminal. Then, the CPU 1 executes the processing shown in FIG. That is, the numerical display registers X1, X2, and X3 storing the three-digit numerical values to be displayed on the numerical display 27 are set to the initial values, and the display lamp register L storing the lighting lamp of the lamp display 29 is set. Set to the initial value. Also, a winning prize ball counter C for counting the number of prize balls that have been won and held in the specific prize port is set to zero, and a special prize port winning counter G for counting the number of prize balls to the special winning port is set to zero. A V winning ball counter A for counting the number of winning balls to the winning port is initialized to zero. The state register F storing the control state is initialized to zero, the hit mode register R storing the hit mode is initialized to zero, and the timers T1, T2 and T3 are initialized to zero. Further, the swap flag S storing the swap state of the CPU 1 and the CPU 2 is reset. (2) Every time an external interrupt signal is input at regular time intervals (4.096 msec) after the background processing initial setting, the CPU 1
And the program of FIG. 5 is executed. In step 100,
The timer is updated, and the state signals S1, S2, and S3 of the switch group are read in step 102. These state signals are constituted by negative logic, and when the signal is at a low level, the switch is turned on. Indicates that a winning ball has been detected. Therefore, steps 104, 1
The falling of each state signal is detected at 10, 114, and only at that time, each counter C, G, A is updated by one. However, the number of winning balls held is determined in step 106 by
Only count up to four. Steps 118 to 166 are processing steps corresponding to each state. Also, from step 170
Step 192 is a processing step of the output device. When the hit mode register R is 0, the solenoid 41 is turned off, so that the special winning opening is closed or the closed state is maintained. When the register R is other than 0, the solenoid 41 is turned on.
The open state is maintained (steps 170 to 174). That is,
Opening and closing of the special winning opening is controlled by the contents of the register R. The numerical display 27 displays the values of the registers X1, X2, X3, and the lamp display 29 turns on the LED specified by the register L (step 176). Register F is 1
In other words, when the combination operation is being performed, the operation lamp 47 blinks, and when the register F is 2, that is, when the special winning opening is in the open state, the operation lamp 47 and the panic lamp 43 blink, and the register F At 2, when the counter A is not 0, that is, when there is a V winning ball, the V lamp 45 is turned on.
Further, the value of the counter C is displayed on the stored number display 30 (step 178). Steps 180 to 192 are steps for driving or stopping the CPU 2 in the auto-swap mode depending on whether or not tone generation control is performed. At the time of tone control, that is, when the register F is other than 0, the swap flag S
Is set, auto swap is started, and after that,
CPU1 and CPU2 operate alternately one by one. When the register F becomes 0, the tone generation control is stopped, and the swap flag S is reset.
The auto swap is stopped, and thereafter, only the CPU 1 operates. (3) Processing when there is no winning ball When there is no winning ball, that is, when the counter C is 0, the processing of steps 100 to 124 and 170 to 192 is performed, whereby the numerical value is set. The display, the lamp display, and each lamp group perform a predetermined display. (4) When there is a winning ball (C ≠ 0) (a) The value of the counter C is determined in the combination operation processing step 124, and when a winning is detected, the value of the counter C is decremented by one. The register F is set to 1 to indicate the combination operation state, and the timer T1 is set to a predetermined value (steps 124 to 130). Then, in step 132, a random number generation process is performed, and the generated random numbers are stored in the registers X1, X2, X3, and L. Until the time is up in step 134, step 100
To 118, 132, 134, and 170 to 192 are repeated. The setting of the random numbers is performed every time the process passes through step 132. When the time is up, in step 136, the registers X1, X2, X3, L
Is set in the register R, and the mode is set in the register R. 0 is out, 1 is small hit, 2 is medium hit, and 3 is big hit. If it is off, the register F is set to 0, and the process proceeds to the cycle for determining the next winning ball. (B) Winning process When the result of the determination in step 136 is a hit, a time is set in the timer T2 according to the hit mode. Then, the background processing described above is performed until it is determined that the time is up. As a result, the special winning opening is opened for a predetermined time, the lamp group is displayed to indicate a panic state, and music in a panic state is played from the speaker 35. At this time, if the number of winning balls in the special winning opening reaches 10, the same processing as the time-up is performed even before the time-up. That is, the counter G is set to 0 and the register R is set to 0 (steps 150 and 152). (C) Processing when a V Win Ball Exists When a large win port is open, a V win ball exists, that is,
If the counter A is not 0 (step 156), step 1
At 58, the value of the register F is set to 3 to indicate the generation of the continuation right. Then, the counter A is decremented by 1, and the timer T3
Is set to a predetermined time, and time up is determined (steps 158 to 164). This processing is for giving a certain delay until the special winning opening is subsequently opened. Thereafter, in step 166, the register R is set to 3 indicating a big hit, and the process proceeds to step 142 to perform the above-mentioned hit processing. However, the continuation right is adjusted in step 152 so as not to occur more than ten times. (5) Processing for sound generation control In the background processing of steps 180 to 192, it is determined that the sound generation control state is established.
The PU 2 executes the processing of FIG. 6 in parallel with the processing of the CPU 1 macroscopically. In step 200, the sound generation mode is determined from the values of the status register F, the winning ball counter C, the winning mode register R, the special winning opening winning counter G, and the V winning ball counter A, and the value is set in the register W. The ROM 3 stores a control data group for outputting a different melody for each tone generation mode, as shown in FIG. The control data includes a set of sounding data such as a sound frequency, a sound volume, and an envelope, and time data indicating the sounding continuation time of the sound. In step 202, it is determined whether or not the tone generation mode has changed based on the change in the value of the register W. If there has been a change, the process proceeds to step 204, where the head address storing the control data group in that mode is set as the data pointer. Set to P. Next, step 206
To store the contents of the address indicated by data point P in ROM
3 and if it is not the end code of the data, at step 210, time data is set in the timer based on the control data. Next, in step 212, the pronunciation data is
By outputting to each register of G33, the speaker 3
From 5 onward, one sound is generated until it is determined in step 214 that the time is up. Next, when it is determined in step 214 that the time is up, the process proceeds to step 216, where the data pointer P is updated to the address of the next control data, and the process returns to step 200. If it is determined in step 202 that there is no change in the tone generation mode, the initial setting of the address is jumped, so that tone data of the next sound in that mode is input. As described above, in this embodiment, one of the two CPUs of the dual computer is used for the main control of the pachinko machine, and the other CPU is used for controlling the sounding device, which has complicated control. Used in Therefore, it is only necessary to develop an independent program for each, so that the production is simple. Further, the CPU 2 can be used for controlling a lamp group. As shown in FIG. 8, the control data includes light emission data designating which of the plurality of lamps is to be turned on, and time data for continuing the state.
As a set of data, such a data sequence is created for each light emission mode. The processing procedure of the CPU 2 is the same as that shown in FIG. 6, where step 200 is for determining the light emission mode, step 204 is for setting an initial address corresponding to the light emission mode, step 210 is for setting time data, and step 2 is for setting time data.
Numeral 12 enables dynamic light emission control in accordance with the control data if the light emission data is output. Further, the CPU 2 determines the number of times of driving the numerical value display,
It can also be used for addition and other statistical processing of the number of opening of the winning port in the jackpot mode. [0032] According to the present invention, a winning detecting system for detecting a winning ball that orchestra in particular winning hole is provided, a person or mode determined according to the winning to the particular winning hole, in that mode Control the winning probability of the ball to the winning opening according to the light emitting device,
In Pati <br/> Nko equipped with a control device for controlling the peripheral devices sound generating device such as the control device, a plurality on one chip
The central processing unit is formed of a one-chip microcomputer , and the pachinko machine further comprises one or more
Comprises a plurality of memories, at least one of said memories.
Memory is shared by the plurality of central processing units.
It is characterized by being. Therefore, since each central processing unit can execute necessary tasks in parallel while sharing necessary data in accordance with its own processing program, it is possible to simultaneously perform different tasks. For this reason, it becomes possible to make the game development of the pachinko machine more complicated, to output a melody composed of complicated musical sounds in parallel with the progress of the game, and to realize lighting that fluctuates in a complicated manner, More entertaining can be improved. In addition, the development of the program can be performed independently of each other without being influenced by the programs of the other central processing units. Therefore, the development of the game program and the development of the program such as the sound control can be performed by the respective specialists, and the development of the device becomes easy. If a single CPU executes parallel operation of tasks, a stack area for saving a program and register data for a task switching process such as a saving process for a register is required. as described above, the double
By using the number of CPU, intermittently perform each task
This eliminates the need to free up the CPU for execution of other tasks. As a result, a stack area for saving the program of the task switching process and the data of the register is not required, so that the memory capacity can be saved. Further , since the memory is shared by a plurality of CPUs , the capacity of the memory can be saved from this. From these facts, even if the storage capacity is limited, more work can be performed and a program unique to each CPU may be developed, thereby facilitating maintenance and system design.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an electrical configuration of a pachinko machine according to a specific embodiment of the present invention. FIG. 2 is a plan view showing the appearance of the pachinko machine of the embodiment. FIG. 3 is a flowchart showing a processing procedure of a dual one-chip microcomputer used in the pachinko machine of the embodiment. FIG. 4 is a flowchart showing a processing procedure of a dual one-chip microcomputer used in the pachinko machine of the embodiment. FIG. 5 shows a processing procedure of a dual one-chip microcomputer used in the pachinko machine of the embodiment.
Flowchart that follows. FIG. 6 is a flowchart showing a processing procedure of a dual one-chip microcomputer used in the pachinko machine of the embodiment. FIG. 7 is a structural diagram showing a structure of control data for sound generation control. FIG. 8 is a structural diagram showing a structure of control data for controlling a light emitting device of a pachinko machine according to another embodiment. [Description of Signs] 27 Numerical Display 29 Lamp Display 30 Memory Number Display 43a to 43c Panic Lamp 45a to 45c V Lamp 47a to 47j Operation Lamp 50 Frame 51 Play Board 52, 53 , 54: specific winning opening 63: large winning opening 64: opening / closing door 65: V winning opening

Claims (1)

(57) [Claims] Winning detector for detecting winning balls that orchestra in particular winning hole is provided, a person or mode determined according to the winning to the particular winning hole, the winning probabilities of the sphere to the in-prize opening in response to the mode controls, light emitting device, the pachinko machine having a control device for controlling the peripheral devices sound generating device such as the control device, a plurality of central processing units on one chip
It is composed of the formed one-chip microcomputer
The pachinko machine further includes one or more memories.
In addition, at least one of the memories includes the plurality of memories.
A pachinko machine characterized by a configuration shared by a central processing unit . 2. Before Among Kiwa-chip microcomputer, the first central processing unit, a pachinko machine according to claim 1, wherein controlling the prize probability, characterized by managing the progress of the game pachinko machine. 3. Before Among Kiwa-chip microcomputer, the first central processing unit, sound generating device, light emitting device, among other peripheral devices, pachinko machine according to claim 1, characterized by controlling at least.