JP2766985B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique particularly effective when applied to a logic integrated circuit technique and a microprocessor configuration method, and particularly to a program for executing a process according to a given program. The present invention relates to an LSI configuration method suitable for implementing a failure analysis and a self-diagnosis function in a control type data processing device.

[Related Art] Conventionally, failure analysis of hardware of a logic LSI such as a microprocessor has been performed using a diagnosis circuit provided inside the LSI. The diagnostic circuit in a conventional logic LSI is divided into a plurality of blocks inside the LSI, and by applying a signal to a specific terminal, the function shifts to a test mode that enables input and output of signals for each of the divided blocks. Was realized.

In addition, regarding LSI failure diagnosis technology, for example,
Published by Techno System Seminar Division, described in the lecture material "Logic Circuit Diagnosis Technology" on July 8, 1986.

[Problems to be Solved by the Invention] Since a logic LSI equipped with a conventional diagnostic circuit performs a diagnosis in a test mode that operates in a state different from an actual processing mode, it reproduces the same state as when the LSI failure occurred. However, analysis cannot be performed while monitoring this. For this reason, when a large-scale processor is performing processing according to a program under development, it is unknown whether the bug is in the hardware or the software, and the failure analysis requires a lot of time.
Further, there is a problem that it is difficult to perform a complete analysis.

An object of the present invention is to provide an LSI configuration method that enables a failure analysis and a self-diagnosis in a data processing device that operates according to a program such as a microprocessor to be performed in a short time and more accurately.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, when a mode switching signal is input from the outside into the microprocessor, a timing generation circuit for stopping generation of the next timing signal when all timing signals in one machine cycle have been generated, and an internal register Switching means for switching a supply path of an address signal to a decoder which generates a signal for selecting a data holding means which can be designated by an address signal such as a memory and a RAM, and a mode for switching an operation mode according to a control signal supplied from the outside When a specific mode (test mode) is designated, the timing generation circuit is stopped, and the address switching means switches the supply path of the address signal to the address decoder to the external input side. Internal register or RAM by the address signal of Constant to data read and write to the so performed.

[Operation] According to the above-described means, the internal operation of the microprocessor is stopped in machine cycle units, the data in the register and the RAM at that time are held, and an address is externally given to read out, Data can be stored in the desired register or RAM, and processing can be continued using the data. This allows failure analysis and self-diagnosis in a data processing device that operates according to a program such as a microprocessor to be performed in a short time. In addition, it is possible to achieve the above-mentioned object of more accurately performing.

FIG. 1 shows an embodiment in which the present invention is applied to a microprocessor.

The microprocessor according to this embodiment includes a control unit 1 of a microprogram control system, an execution unit 2 including a special register such as an ALU (arithmetic logic unit), an accumulator, and an index register; a general-purpose register group 3 for temporarily storing data; A RAM 4 serving as an area, an I / O control circuit 5 for controlling input / output, and a timing generator 6 as a timing generation circuit for generating a timing signal inside the processor are provided.

The control unit 1 is a ROM 1 storing a microprogram.
2. A sequencer 11 for holding a macro instruction read from an external program memory via the I / O control circuit 5, reading a series of micro instructions corresponding to the macro instruction from the ROM 12, and controlling the flow of processing. And above
An instruction register 13 for holding a microinstruction read from the ROM 12; a decoding unit for decoding the microinstruction held in the instruction register 13;
And an instruction decoder 14 for forming control signals C ₁ , C ₂ ,... Ci for the RAM 4 and the like.

The execution unit 2, the general-purpose register group 3, and the RAM 4
Is an internal data bus via gates G ₁ , G ₂ ,.
The gates G ₁ , G ₂ ,... Gj are controlled based on an address decode signal Sk and a read / write control signal R / W so that writing and reading are performed. I have.

In this embodiment, an address selector 21 is provided at the preceding stage of the address decoder 8 which decodes an address designating the register and the like to form the selection signals S ₁ , S ₂ ,... Sk. / O control circuit 5
A register or the like can be designated by any of the addresses supplied from the outside via the.

In addition, the address selector 21 of this embodiment is configured to create an address non-designated state in which none of the addresses are supplied to the decoder 8. When the address non-designated state is reached, a selection signal output from the address decoder 8 is generated.
S _1, S _2, all ...... Sk becomes low level, disconnect the internal register 3 and RAM4 internal bus 7a, from 7b, so that the data captured immediately before can be held.

Further, in this embodiment, a mode switching circuit 22 for generating a control signal for switching between the test mode and the normal processing mode, a test mode control circuit 23 for determining the type of the test mode and controlling the start / stop thereof, An address switching control circuit 24 for forming an address switching control signal in the address selector 21 is provided.

FIG. 2 shows a configuration example of the timing generator 6 used in the present embodiment.

The timing generator 6 9 flip-flops FF ₁ to ff ₉ are connected in cascade form, the output signal of the one flip-flop FF ₂ and FF ₄ and FF ₆ is N
The input signal is input to the OR gate Gn, and the output signal is fed back to the input terminal of the _first flip-flop FF1 via the AND gate Ga. Along with this, flip-flops
FF ₁ to ff ₉ is triggered by the common clock CK is supplied from outside. Moreover, the odd-numbered flip-flops are triggered by the rising edge of the clock CK, and the even-numbered flip-flops are triggered by the falling edge of the clock CK (or vice versa). This output state of the flip-flop FF ₁ (low level) the clock CK
It is transmitted to the next stage flip-flop for each half cycle of the output of each flip-flop FF ₁ to ff ₉ is sequentially changed.
In this case, when the first input of the FF ₁ in a state in which the AND gate Ga is opened to assume a low level, 3 clock cycles in the sixth input of FF ₁ when the output is changed to the low level of the flip-flop FF ₆ is high captured in that state changes in level, the output of the flip-flop FF ₂ in one clock later changes to the high level, the input of the FF ₁ output of NOR gate Gn is changed to the low level becomes the low level.
Therefore, the output of each flip-flop FF ₁ to ff ₉ is a signal having a 1/4 duty at four times the period of the clock CK (see FIG. 3). In this embodiment, the flip-flop FF
_{1 ~FF} FF _{1 ~FF} internal timing signal phi ₁ output is ₈ out of ₉
As to [phi] _8, it is supplied to each circuit in the processor such the execution unit 2 is configured to operate four times the period of the clock CK as one machine cycle.

The timing generator 6 according to this embodiment includes the AND
When a high-level control signal TEST is applied to the external terminal 31 connected to the other input terminal of the gate Ga, the device operates normally, and when the control signal TEST is changed to a low level, the input signal of the flip-flop FF ₁ is input. Is fixed to a low level, and thereafter, as shown in FIG.
_A new output pulse (φ ₁ ) is no longer formed. However, even if the control signal TEST is changed to a low level once the pulse φ ₁ is formed, the subsequent timing signal φ
Pulse ₂ to [phi] ₈ is subsequently formed. Therefore, the inside of the processor stops when the operation of one machine cycle is completed.

Further, in this embodiment, the output of the flip-flop FF ₁ to ff ₉ constituting the clock generator 6 wired OR
Is supplied to the address switching control circuit 24 as a control signal HALT. In addition, when the control signal HALT changes to a low level, the address switching control circuit 24 generates a signal that causes the address selector 21 to shift to an address non-designated state. As a result, the register 3 and RAM4 in the processor input and output gates G _1, G _2, ...
... Since Gi is closed, the data contained at the end of the machine cycle is kept as it is. Moreover, at this time, the gate on the write side is also closed, so that unwanted data is not erroneously taken into the register or the RAM due to noise generated when a test type selection signal described later changes.

On the other hand, the control signal TEST input to the external terminal 31 is
The mode is also input to the mode switching circuit 22, and when the control signal TEST is changed to the low level, the mode switching circuit 22 instructs the test mode control circuit 23 to switch the operation mode from the normal mode to the test mode. A switching signal MC is supplied. Upon receiving this signal, the test mode control circuit 23 takes in a test type selection signal TTYP ₁ ~TTYP ₃ which is input to the external terminals 32, 33, 34, determines a test mode in accordance with the combination, the external A control signal for activating the test mode determined when the signal TEN applied to the terminal 35 is asserted is generated and supplied to the address switching control circuit 24 and the I / O control circuit 5.

In the microprocessor of this embodiment, six types of tests as shown in Table 1 below can be performed according to the combination of the _three test type selection signals TTYP _{1 to} TTYP ₃ .

When the test type TT0 in Table 1 above is selected,
The microprocessor operates in the same manner as in the normal operation mode, but the execution timing of the microcode and the start / stop (HALT signal) of the time generator can be monitored from the function multiplexing terminal.

When the test type TT1 is selected, all registers accessible by the microprocessor can be read and written from outside.

When the test type TT2 is selected, registers that cannot be accessed by the microprocessor, particularly registers that directly control the sequence, can be read / written. Specifically, microcode is set in the instruction register 13 to force a specific instruction to be executed, or the sequencer 11
, A microcode address is set in a program counter in the program, and a sequence can be monitored by forcibly jumping or reading the microprogram.

When the test type TT3 is selected, the RAM is read / written, and the entire space in the RAM can be accessed with a 12-bit address.

 Test type TT4 is unused.

When the test type TT5 is selected, the scan path can be read / written.

When the test type TT6 is selected, the execution of the microprogram can be stopped at the address specified in the breakpoint register (set by TT2).

When the test type TT7 is selected, the microprocessor performs a single step operation. That is, the processor can be stopped and started every machine cycle. Therefore, in combination with the test types TT1, TT2, and TT3, the internal LSI can be monitored every time the microprogram is executed for one step.

Next, the operation of the microprocessor configured as described above will be described.

In the normal operation mode in which the test mode switching control signal TEST is at a high level, the microprocessor of this embodiment reads the microinstruction at the address specified by the sequencer 11 from the ROM 12 and temporarily stores it in the instruction register 13. . At this time, the path is selected so that the address selector 21 supplies the address in the instruction register 13 to the address decoder 8.

Microinstruction held in the instruction register 13 is decoded control signals C ₁ ~Ci is generated by the instruction decoder 14, this data from the register group 3 and RAM4 by is being processed is supplied to the execution unit 2 read , And output to the outside via the I / O control circuit 5 or stored in the register group 3 and the RAM 4. These series of processes are executed by sequentially operating each circuit element by the periodic timing signals φ _{1 to} φ ₈ generated by the timing generator 6.

It is assumed that the test mode switching control signal TEST is set to the low level in a state where the microprocessor is executing the process according to the program as described above (normal operation mode). Then, this signal is supplied to the timing generator 6 shown in FIG. 2, and the timing signals φ _{1 to} φ ₈ are stopped in units of machine cycles of the processor.

When the timing generator 6 is stopped and the timing signals φ _{1 to} φ ₈ are no longer output, the processing of the processor is stopped, and the HALT signal is supplied from the timing generator 6 to the address switching control circuit 24. As a result, the address selector 21 is switched to the address non-designated state, and the write path to the register group 3 and the RAM 4 is temporarily cut off. As a result, the data in the process of being written to the register group 3 or the RAM 4 at that time is saved.

Next, when a test type is selected by inputting test type selection signals TTYP _{1 to} TTYP ₃ and a control signal TEN is asserted, a corresponding test mode is activated.

For example, when the test type TT1 is selected, the assertion of the control signal TEN causes the address selector 21 to be selected.
The address path is switched to the I / O control circuit 5 to supply an external address to the address decoder 8. Therefore, if an address signal AD for specifying the register group 3 is input from the address input terminal 36, the data in the register group 3 is output to the internal data bus 7a, and the data input / output terminal via the I / O control circuit 5. 37 can be output. Therefore, it is possible to externally monitor the data being processed in the internal register and the RAM every machine cycle.

After that, when the control signal TEN is released, the address selector 2
1 returns to the state of the address unspecified, further releases the test mode switching control signal TEST, the timing generator 6 starts operation, begins to generate timing signals from phi _1. Therefore, the processor restarts the operation from the beginning of the machine cycle, and continues the process immediately after the stop, continuing the processing. Therefore, the state of each machine cycle can be monitored.

On the other hand, when the test type TT0 is specified, if the write of the register is instructed by the read / write control signal R / W, the desired data can be externally input into the register, so that the microprocessor writes the written data. Use to continue processing.

Also, if the type TT2 is designated instead of the register read / write (TT1) as the test type, the program counter and the instruction register can be read / written, so that the sequence control can be performed independently of the installed program. . As a result, failure analysis of hardware and software of the processor can be performed easily and in a short time.

Note that the test types in the test mode are not limited to those shown in Table 1. For example, when the microprogram ROM built in the processor is configured by a rewritable memory such as an EPROM, the EPROM is read from the outside. A test type that enables writing can be provided.

Further, the terminals 32, 33, 34 for applying a test type selection signal TTYP ₁ ~TTYP _3, is shared with the terminal to be used in the normal operation mode, the terminal 32, 33, 34 when asserted test mode switching signal TEST By configuring so that the input signal is supplied to the test mode control circuit 23, the external terminals can be multiplexed and the increase in the number of pins can be suppressed.

As described above, in the above embodiment, when a mode switching signal is input from the outside into the microprocessor, the generation of the next timing signal is stopped when all the timing signals in one machine cycle have been generated. A timing generation circuit, an address switching means for switching a supply path of an address signal to a decoder for generating a signal for selecting a data holding means which can be designated by an address such as an internal register or a RAM, and a control signal supplied from the outside. A mode control means for switching an operation mode in accordance with the operation mode; when a specific mode (test mode) is designated, the timing generation circuit is stopped; and the address switching means externally supplies an address signal supply path to the address decoder. Switch to input side, internal by external address signal Data can be read and written by specifying a register or RAM, so the internal operation of the microprocessor is stopped in machine cycle units, the data in the registers and RAM at that time is retained, and the address is externally addressed. To analyze the failures and self-diagnosis of the microprocessor in a short time. In addition, there is an effect that it can be performed more accurately.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor.

For example, immediately after power-on of the processor, the timing generator 6 does not operate, and the address switching control circuit 24
The address selector 21 is configured so that any address supply path is not connected to the address decoder 8 in an address non-designated state, thereby preventing a malfunction occurring before a power-on reset is applied to the processor. You may.

In the above description, the invention made by the present inventor is mainly applied to a microprocessor which is a field of application as a background, but the present invention is not limited to this, and a controller LSI operated by a program And a digital signal processor and other data processing devices in general.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, failure analysis and self-diagnosis in a logic LSI operating according to a program such as a microprocessor can be performed in a short time and more accurately.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a microprocessor to which the present invention is applied. FIG. 2 is a circuit diagram showing an example of a clock generator in the microprocessor. FIG. 3 is an input / output signal of the clock generator. 6 is a time chart showing the timing of FIG. 1 ... Control unit, 6 ... Timing generation circuit, 7a, 7b ...
Internal data bus, 13 ...... instruction register, FF ₁ to ff ₉ ...... flip-flop.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 11/22-11/26 G01R 31/28-31/30 G06F 15/78 510

Claims (1)

(57) [Claims] An internal memory or an internal register corresponding to an address, wherein each circuit portion is operated in time series by a plurality of signals having different timings in accordance with a program instruction to process one data. In the data processing device configured to execute the operation of, in order to execute a series of operations based on a basic clock supplied from the outside, sequentially generate a timing signal,
A timing generation circuit configured to stop when a control signal indicating a predetermined mode is input, when the generation of the last one of the series of timing signals is completed, and a signal for selecting the internal memory or the internal register Address switching means capable of switching a supply path of an address signal to an address decoder that generates an address signal. The address switching means supplies an internally generated address signal to the address decoder in a normal operation mode, and In this mode, an externally input address signal is supplied to the address decoder, and when the timing generation circuit is stopped, any of the address supply paths is cut off to set an address non-designated state, and other predetermined control is performed. Signal is configured to enable the external address supply path. The timing generation circuit outputs a signal indicating that the operation has been stopped when the operation is stopped, and the address switching means shifts to the address non-designated state based on the operation stop signal. A data processing device characterized by the above-mentioned.