TWI306194B - - Google Patents

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TWI306194B
TWI306194B TW95106524A TW95106524A TWI306194B TW I306194 B TWI306194 B TW I306194B TW 95106524 A TW95106524 A TW 95106524A TW 95106524 A TW95106524 A TW 95106524A TW I306194 B TWI306194 B TW I306194B
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central processing
unit
processing unit
abnormal
signal
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TW95106524A
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TW200732909A (en
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wen-zhong Dai
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Description

1306194 九、發明說明: 【發明所屬之技術領域】 本發明係有關一種可記錄當機次數之中央處理器,尤 士曰種可§己錄该中央處理器從開機後所產生過之—不正 系指令訊號之次數,即當機次數,並將該當機次數儲至— f存器/或記憶單元中,以在該中央處理器被重新啟動 時,供一軟體程式讀取,並予顯示者。 【先前技術】 按,中央處理器(Central Processing Unit,簡稱 ⑽)在電齡統巾,是主要核^的元件,又稱電腦的心臟。 该中央處理社要用來做算術、邏輯運算,解釋每個指令 :意義’ _經過蘭和計算後,再下齡將·送到正 的裝置上執行。—套電腦系統通常使用-個該中央處理 是,器電腦或是較大型的電腦,則可能由多個該 奸同時工作。目前市面上常會聽到的該中央處理 ‘二英特爾(Intel)所生產的奔騰(pentium)及賽 柄CCeleron)系列等。 料+央處理11的設計職+,對於不正常指令訊 理°器外部的處理方式,大都係需等待該中央處 _辑電腦重::重電路(如:一^ 源斷電後,再重新將” it過人工方式將該電腦的電 m ^雜令職產生衫動預警。 * #1圖所不’習知該中央處理器1〇的結構中, 1306194 係至少包括一續取單元101、一解碼器1〇2、一模擬或執行 單元103及-算術邏輯運算單元1〇4(arithmeticandi〇g^ unit,簡稱ALU) ’其中該讀取單元1〇1係用以從外部之一輸 入輸出界面讀取一指令式機械碼;該解碼器1〇2係用以接收 由該讀取單元101所送出之該指令式機械碼,以成為一個機 械週期之開始,並將該指令式機械碼翻譯成每一個獨立的 指^,其中也包括-不正常指令訊號(意即所謂不正確的 運算指令)’該模擬或執行單元⑽制以將該指令式機械 碼所翻譯成的該每一個獨立的指令作轉碼的動作,其中該 不正&才曰令Λ號在其處理當中將導致該中央處理器的當 機;該算術邏輯運算單元綱係肋接收由該模擬或執行單 ,103所送出轉碼的該每一個獨立的指令,以執行算術運 算’邏輯運算和有關的操作後,再將結果送到正確的裝置 上執行。 然而’在一般正常的情形下,該指令式機械碼是不會 產生該不正常指令訊號。該不正常指令減的發生有些是 因為軟體設計錯誤所造成,但Α多數是因為電腦硬體發生 故障或是零件老化所導致,如:動態隨機存取記憶體 (Dynamic Random Access Memory,簡稱DRAM)老化,以 致儲存在該祕隨機存取記憶體巾的f料因其漏電而產生 資料不正確,或因其他邏輯晶片故障導致傳輸資料發生錯 誤。 ^從習知該中央處理器的設計結構中,若產生該不正常 扣令汛唬,結果都是該中央處理器當機,然後等待該中央 1306194 處理益外部的該定時器重置(Reset)電路,自動將該電腦 重新啟動,或是透過人工方式將該電腦的電源斷電後,再 重新將该電腦重新啟動,由於需等待該定時器重置電路, 自動將該電腦重新啟動,故在反應速度上較慢,因此,該 電腦當機不僅會造成使用者在工作上的不便,同時亦往往 造成時間及金錢上的損失。 基於此,發明人在嗅覺到此一現象,即構想設計出一1306194 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a central processing unit capable of recording the number of crashes, which can be recorded by the central processor after being turned on. The number of command signals, that is, the number of crashes, and the number of crashes is stored in the memory or memory unit to be read by a software program and displayed to the display when the central processor is restarted. [Prior Art] According to the Central Processing Unit (C10), it is the main core component of the computer, which is also called the heart of the computer. The central processing agency is used to perform arithmetic and logic operations, interpreting each instruction: meaning ' _ after Lan and calculation, then the next age will be sent to the positive device for execution. - A computer system usually uses - the central processing is a computer or a larger computer, and it is possible that multiple traitors work at the same time. The central government often hears about the ‘Pentium and Celebrity CCeleron series produced by Intel. Material + central processing 11 design job +, for the abnormal processing of the external processing of the device, most of them need to wait for the central office _ series computer heavy:: heavy circuit (such as: a ^ source power off, then re- "It has artificially made the computer's electric m ^ miscellaneous job to produce a shirt warning. * #1图不不" The central processor 1〇 structure, 1306194 is at least including a renewing unit 101, a decoder 1〇2, an analog or execution unit 103, and an arithmetic logic unit 1〇4 (arithmeticandi〇g^ unit, ALU for short), wherein the reading unit 1〇1 is used to input and output from one of the external ones. The interface reads an instructional mechanical code; the decoder 1〇2 is configured to receive the instructional mechanical code sent by the reading unit 101 to become a beginning of a mechanical cycle, and translate the instructional mechanical code Each of the independent fingers, which also includes - an abnormal command signal (meaning a so-called incorrect operation command) 'the simulation or execution unit (10) is configured to translate the instructional mechanical code into each of the independent The instruction is a transcoding action, where the error is & The nickname in its processing will cause the central processor to crash; the arithmetic logic unit rib receives each of the independent instructions sent by the analog or executable, 103, to perform arithmetic After the operation of the logical operation and related operations, the result is sent to the correct device for execution. However, in the normal case, the instructional mechanical code will not generate the abnormal command signal. Some of them happen because of software design errors, but most of them are caused by computer hardware failure or parts aging, such as: Dynamic Random Access Memory (DRAM) aging, so that it is stored in The material of the secret random access memory towel is incorrect due to leakage, or the transmission data is incorrect due to other logic chip failures. ^ From the conventional design structure of the central processing unit, if the abnormality occurs After the deduction, the result is that the central processor is down, and then wait for the central 1306194 to handle the external reset of the timer. , automatically restart the computer, or manually power off the computer power, and then restart the computer again, because the timer is reset, the computer is automatically restarted, so the reaction The speed is slower. Therefore, the computer crashes not only causes inconvenience to the user, but also causes time and money loss. Based on this, the inventor is smelling this phenomenon, that is, conceiving a design.

種中央處理如部預警當機之硬體裝置,透職中央處理 器的出現,可產生出新的電腦’且該電腦可達成預警當機 或永=當機之功效,藉贿低習知因機所產生:損 失這也就疋本案發明人認為有必要將其提出專利 構想起源。 【發明内容】 雜歡迷介紹,習知該中央處理器 人乃依其從事該中央處理器之製造經驗和= 柄明之-種「可記錄當機 十出 該中央處理諸開顺所纽過之中—^記錄 機次數,並將該當機次數健至-暫 本發明之一目的,Λ %斗 _ρ二Α 理器’該中域ίΐϋ包括1_^機中央處 元係用以接收由該中央處理器内部之二 7 1306194 至料in號’並對其進行重整後,將重整訊號輸出 中^、=理$外部之—邏輯電路,該邏輯電路可為另一 編、’ Μ在接收龍錄峨後,接管所有之控 . Μ達到永不當機之目的,及/或觸啟動該中央 處理為,一言*Μ哭·苗- j ,^ °。早兀,係與該解碼器連接,以記錄該中 機後所產生過之該不正常指令訊號之次 次數’並將該即當機次數儲存至一暫存器/或 ^早7L巾’以在該中央處理器被重新啟動時,供—儲存 早兀内之一軟體程式讀取。 夕士本發明之另-目的,係當該不正常指令訊號的次數過 夕日r可透過該軟體程式於—顯示幕中顯示出,以供一使 用者判斷該中央處理器之當機次數是否已超過正常標 ㈣亚據輯其進行制、維修或更換,以確保 後續作業得以正常進行。 本發明之又—目的,係當該不正常指令訊號之次數超 t預定次數時,可透職軟齡式,向其他周邊輪出裝 置(如:喇叭)發出警告訊號。 為便於f審查委員能對本發明之技術手段及運作過 私有更進-步之認識鱗解,_實關配合圖式細 說明如下: 【實施方式】 本發明係-種「可記錄當機:欠數之巾央處理器」,請參 ,第2圖解i其絲發明之—最佳實關,該中央處理 态20 (CPU)係至少包括—訊號重整單元211、—計數器 1306194 單元批及-暫存器/或記憶單元那,其中 p :211係與該中央處理器2〇内部之一解碼;〇2連;早 ====送出之-不正常指令訊號(意即 :==),並對其進行重整後,將重整訊 =至=處,2〇外部之一邏輯電路3〇,該邏輯 :路30可為另一中央處理器,用以在 重 管所有之控制程序,以達到永不當機之目的,J 或重新啟動該中央處理器2〇。 魅t於該不正常指令訊號的工作頻率太高(如:600百 一 2ΐΓ番:1)以上)’故將其卫作頻率透過該訊號重整單 tr短Ϊ 神(如:33百萬赫兹(ΜΗζ))的波型供 |亥邏輯電路30使用。 此外’由於該不正常指令訊號的工作頻率太高,以致 ,出電磁波’讓電磁波許擾且影響到其他電子零件之正 承運作,且該不正常指令訊號的工作頻率太高,亦將使 麟輯電路3G不容易接收,及—設計人 路 30在設計上之不容易。 珥电峪 再者,前述該計數器單元212係與該解碼器2〇2連接, 用匕以記錄該中央處理器20從開機後所產生過之該不正常 心令《之次數,即當機次數;該暫存器/或記憶單元如 係=以暫時將該計數器單元212所記錄該不正常指令訊號 之次數儲存至其中,並供-儲存單元31内之-軟體程^ 311 口於重新啟動該中央處理器2〇時讀取,則共一使用者判 斷是否為該不正常指令訊賴造錢重置,且當該不正常 1306194 定次數時,則係可透過該敕體程 20之#機次缺否已超J 確保編業得以^^其進行檢測、維修或更換,以A kind of central processing such as the hardware device of the early warning, the emergence of a central processor, can produce a new computer' and the computer can achieve the effect of early warning or permanent, the use of bribes The machine produces: the loss is also the origin of the patent idea that the inventor of the case thinks is necessary. [Invention] The introduction of the fans, it is known that the central processor is engaged in the manufacturing experience of the central processor and the type of "the recordable machine is out of the central processing." -^ Record the number of times, and the number of times of the crash is up to - one of the purposes of the present invention, Λ%斗_ρ二理器' the middle domain ίΐϋ includes the 1_^ machine central unit for receiving by the central processor After the internal 2 7 1306194 to the in number ' and after it is re-formed, the signal will be output in the ^, = = external - logic circuit, the logic circuit can be another series, 'Μ Receive Dragon Record After that, take over all the controls. Μ achieve the purpose of never crashing, and / or touch the start of the central processing, a word * cry cry Miao - j, ^ °. Early, connected to the decoder, to Recording the number of times the abnormal command signal is generated after the middle machine is 'storing the number of crashes to a register/or early 7L towel' to be used when the central processor is restarted - Store one of the software programs in the early reading. The other purpose of the invention is to The number of frequent command signals may be displayed on the display screen by the software program for a user to determine whether the number of crashes of the central processor has exceeded the normal standard (4). Replacement to ensure that the subsequent operation can be carried out normally. The purpose of the present invention is that when the number of abnormal command signals exceeds a predetermined number of times, the soft-aged type can be used to rotate the device to other peripherals (such as a speaker). A warning signal is issued. In order to facilitate the review of the technical means of the present invention and the operation of the private and further step-by-step understanding, the actual description is as follows: [Embodiment] The present invention is "recordable" When the machine is: the number of the towel processor, please refer to the second diagram, the invention is the best implementation, the central processing state 20 (CPU) system at least includes - signal reforming unit 211, - counter 1306194 Unit batch and - scratchpad / or memory unit, where p: 211 is decoded with one of the internal processing unit 2; 〇 2 connected; early ==== sent - abnormal command signal (meaning: ==) and after reforming it The re-synchronization = to =, 2 〇 one of the external logic circuits 3 〇, the logic: the way 30 can be another central processing unit, in order to re-control all the control procedures, in order to achieve the purpose of never crashing, J or restart the central processor 2〇. Charm t is too high in the operation frequency of the abnormal command signal (such as: 600 one hundred and one hundred and two: 1) or more) 'So the frequency of its guard is re-scheduled through the signal, and the tr (short Ϊ god) (eg: 33 megahertz) The waveform of (ΜΗζ)) is used by the Hi-Logic circuit 30. In addition, because the operating frequency of the abnormal command signal is too high, the electromagnetic wave will cause the electromagnetic wave to interfere and affect the operation of other electronic components, and the operating frequency of the abnormal command signal is too high. Circuit 3G is not easy to receive, and design channel 30 is not easy to design. Further, the counter unit 212 is connected to the decoder 2〇2 for recording the number of times the central processor 20 has generated the abnormal heartbeat after the power-on, that is, the number of times of the crash. The temporary memory device or the memory unit is configured to temporarily store the number of times the abnormal command signal is recorded by the counter unit 212, and the software module 311 in the storage unit 31 restarts the When the CPU is read, the user can determine whether the money is reset for the abnormal command, and when the number of the abnormal 1306194 is fixed, the machine can pass through the machine. The second deficiency has exceeded J to ensure that the editing industry can be tested, repaired or replaced.

f卢取ft上述各構件’可清楚得知,當有該不正常指令m 二t何將該不正常指令訊號經由該訊號重整單 2 、、仃重整’並將重整訊號輸出至該中央處理器 y之該邏輯電路30,其中該邏輯電路可為另 ^ β ’以在接收到該重整訊號後,接管所有之控制程 器林當機之目的,及/或重新啟動該中央處理 ,夕’該計數器單元212 ’尚可記錄該中央處理器 錢後所產生過之該不正常指令訊號之次數,即當機f ft ft the above components ' can clearly know that when there is the abnormal command m 2 t, the abnormal command signal is reformed through the signal 2, 仃 re-formed and the reformed signal is output to the The logic circuit 30 of the central processing unit y, wherein the logic circuit can be further configured to take over the control of all the controllers and/or restart the central processing after receiving the reforming signal , the 'the counter unit 212' can still record the number of abnormal command signals generated by the central processor after the money, that is, the crash

^,、’並_當淑數财至該暫存IV或記鮮元213 以在s亥中央處理器20被重新啟動時,供該軟體程式 311讀取,並予顯示。 二上所述’透過本發縣巾央處理器20在發生有該不 令峨產㈣,其反親度即可變快,同時可降低 當機所造成使用者紅作上的錢、_及金錢上的損 進而達到永不當機或據以決定是否對其進行檢測、維 L或更換’以確保後續作業得以正常進行之目的。 按,以上所述,僅為本發明最佳之一具體實施例,惟 本發明之技巧特徵財侷限於此,絲何麟該項技藝者 10 1306194 在本發明領域内,可輕易思及之變化或修飾,應均被涵蓋 在以下本案之申請專利範圍内。 【圖式簡單說明】 第1圖係習知中央處理器之部分方塊示意圖;及 ^圖係本㈣中央處理器之部分方塊示意圖。 【主要元件符號說明】 20 解碼器 … 202 211 計數器單元… 212 213 邏輯電路 … 30 31 軟體程式 … 311 32 輪出裝置 … 33 中央處理器 ... 訊號重整單元 ... 暫存器/或記憶單元... 儲存單元 ... 顯示幕 ...^,, ‘And _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Secondly, 'through the Benfa County towel processor 20, the occurrence of the non-production (4), the reverse degree can be faster, and at the same time reduce the money on the user's red work caused by the machine, _ and The damage to the money can be achieved by never crashing or deciding whether to detect it, maintain it or replace it to ensure that the subsequent operations are carried out normally. According to the above, it is only one of the best embodiments of the present invention, but the skill of the present invention is limited to this, and the artist of the present invention 10 1306194 can be easily changed in the field of the invention. Or the modifications should be covered in the scope of the patent application in the following case. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial block diagram of a conventional central processing unit; and FIG. 4 is a partial block diagram of the central processing unit. [Description of main component symbols] 20 Decoder... 202 211 Counter unit... 212 213 Logic circuit... 30 31 Software program... 311 32 Wheeling device... 33 CPU... Signal reforming unit... Register/or Memory unit... Storage unit... Display screen...

Claims (1)

1306194 V 广^--〜〜〜 、 十、申請專利範圍:樹 k 1、一種可記錄當機次數之中央處理器,至包括: 一解碼器; 一訊號重整單元,係與該解碼器連接,用以接收該解 碼器所產生之一不正常指令訊號,並將該不正常指令訊號 進行重整後’將該重整訊號輸出至該中央處理器外部之一 邏輯電路; I 一計數器單元,係與該解碼器連接,以記錄該中央處 理器從開機後所產生過之該不正常指令訊號之次數;及 一暫存器/或記憶單元,係用以暫時將該計數器單元所 記錄之該不正常指令訊號之次數儲存於其中。 2如明求項1所述之可記錄當機次數之中央處理器, 其中該邏輯電路可為另一中央處理器,用以在接收^重 整訊,後,接管所有之控制程序,及/或重新啟動該中央 處理器。 私 ▲如明求項2所述之可記錄當機次數之中央處理器, /中央處理科部财—儲存單元該儲存單元内安 軟體耘式,當該中央處理器被重新啟動,且該軟體 ^被^行時,將讀取該暫存器/或記鮮元中所儲存之 〜不^!1 令訊號之次數,並透過—顯示幕顯示出來。 盆中㈣明求項3所述之可記錄當機次數之中央處理器, 二II不正常指令訊號之次數超過一預定次數時,可透 姑簡雜錄錄岭告緘。 、、項4所述之可記錄當機次數之中央處理器,其中 12 130.6194. 該周邊輸出裝置可為一喇a。1306194 V 广^--~~~, ten, application patent scope: tree k 1, a central processor capable of recording the number of crashes, to include: a decoder; a signal reforming unit, connected to the decoder Receiving an abnormal command signal generated by the decoder, and reforming the abnormal command signal, and then outputting the reformed signal to a logic circuit outside the central processing unit; Connected to the decoder to record the number of times the abnormal signal is generated by the central processing unit after being turned on; and a register or a memory unit for temporarily recording the counter unit The number of abnormal command signals is stored in it. 2 The central processing unit of claim 1, wherein the logic circuit is another central processing unit, after receiving the re-synthesis, and taking over all control programs, and/or Or restart the central processor. Private ▲ as described in Item 2, which can record the number of times of the central processing unit, / central processing department, the storage unit, the storage unit, the software unit, when the central processor is restarted, and the software When ^ is lined, the number of times that the ~#^^1 command signal stored in the register/or the fresh element is read is displayed and displayed through the display screen. In the basin (4), the central processor capable of recording the number of times of the operation described in Item 3, when the number of abnormal II command signals exceeds a predetermined number of times, can be circulated. The central processing unit capable of recording the number of times of the operation described in item 4, wherein 12 130.6194. The peripheral output device may be a la a. 1313
TW095106524A 2006-02-27 2006-02-27 Central processing unit capable of recording number of breakdown TW200732909A (en)

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