JP2008111682A - Method and apparatus for testing semiconductor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus capable of running even at a high test cycle and being compatible with conventional systems. <P>SOLUTION: In a semiconductor testing method comprising the steps of executing a pattern program stored in instruction memory 101, controlling a multiplexer 108, changing the program execution address to the next execution address, and creating a test pattern to be given to a tested device 500 according to a pattern generation instruction at the same address as the execution address, the instruction memory 101 stores SELECT signals which are related to addresses of pattern programs and a SELECT signal is output by executing a pattern program. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus for testing an IC circuit such as a semiconductor memory, and particularly has a feature in a sequence control circuit that outputs an address signal.

  Conventionally, in a semiconductor test apparatus for testing an IC circuit such as a semiconductor memory, the pattern signal given to the device under test (DUT) stores the pattern generation instruction in the pattern memory and designates the address of the pattern generation instruction by the pattern program The structure to take is taken. In such a semiconductor test apparatus, a sequence control circuit is provided to control the operation of the pattern program.

  FIG. 5 is a diagram showing the configuration of a conventional semiconductor test apparatus. The semiconductor test apparatus includes a sequence control circuit 100 that executes a pattern program and outputs an address signal, a pattern memory 200 that outputs a pattern generation command associated with an address, and a device under test (DUT) according to the pattern generation command. A pattern generation circuit 300 for supplying a test pattern to the device and a comparator 400 for determining whether the device under test 500 is good or bad.

  The pattern generation circuit 300 supplies a test pattern to the device under test 500 and supplies an expected pattern to the comparator 400. On the other hand, the device under test 500 operates in accordance with the test pattern and outputs an output signal to the comparator 400 (return value). The comparator 400 compares the expected pattern supplied from the pattern generation circuit 300 with the output signal output from the device under test 500, and determines whether the device under test 500 is good or bad.

The address signal is a signal for specifying the address of the pattern program in the sequence control circuit 100 and the address of the pattern generation instruction in the pattern memory 200, and is sometimes called a program counter.
JP 2001-282324 A

  FIG. 6 is a diagram illustrating a configuration example of the sequence control circuit. The sequence control circuit 100 shown in FIG. 6 includes an instruction memory 103, a decode circuit 104, a control circuit 106, a multiplexer 108, and a register 110.

  The instruction memory 103 stores a pattern program. FIG. 7 is a diagram for explaining a pattern program stored in the instruction memory. As shown in FIG. 7, the pattern program includes an instruction code (sequence instruction code related to address control) associated with an address and an operand (instruction parameter). The instruction code is obtained by coding an instruction (instruction) as shown in FIG. The instruction is a sequence instruction that describes the movement of the address. Then, the instruction memory 103 outputs a corresponding instruction code and operand based on the current address.

  The decode circuit 104 decodes (decodes) the instruction code and converts it into a select signal that can be interpreted by the multiplexer 108. For example, if the instruction is NOP and it corresponds to the first function of the multiplexer 108, the select signal is 0x001.

  The control circuit 106 performs an execution process for controlling the multiplexer according to the decoded select signal. The control circuit 106 not only selects the function of the multiplexer 108 but also inputs an address to the memory data of the multiplexer 108 when the instruction is jump (JMP) or controls the timer when it is a wait process (PAUSE). The function of measuring time and controlling the counter to measure the number of times in the case of repetitive processing (RPT) is provided.

  The multiplexer 108 performs processing of updating to the next address based on or not based on the current address by selecting a function from the control circuit 106. The next address updated in the multiplexer 108 is held in the register 110. The address signal output from the register 110 is output to the pattern memory 200 and also fed back to the instruction memory 103, and the next series of operations is repeated. As a result, the sequence control circuit 100 outputs address signals one after another.

  That is, the address signal output from the register 110 is used to specify the next address of the pattern program in the instruction memory 103, but is also used as an address to specify a pattern generation instruction in the pattern memory 200. Note that the sequence instruction of the pattern program at the same address and the pattern generation instruction of the pattern memory are not related and are defined separately.

  Since the sequence control circuit 100 described above accesses the instruction memory 103 during one cycle to control the address, the maximum operation speed is the access time of the instruction memory 103, the operation speed of the decode circuit 104, and the control circuit 106. And the total. Therefore, in order to operate at higher speed, there is a problem that it is necessary to use the instruction memory 103 having a fast access time and to configure the decode circuit 104 and the control circuit 106 with high-speed elements.

  Therefore, in the past, the present applicant has proposed a sequence control circuit capable of high-speed operation without using a memory or a high-speed element having a fast access time in Patent Document 1 (Japanese Patent Laid-Open No. 2001-282324). According to Patent Document 1, a storage area for a sequence control instruction for the next row and a storage area for a sequence control instruction for a jump destination row are provided in the instruction memory, and these are read out simultaneously. In response, the sequence control instruction for the next line or the sequence control instruction for the jump destination line is selected, and a program counter signal indicating the next address is created based on the selection output. It is said that a sequence control circuit capable of operating at high speed can be realized without using it.

  A series of operations from the above address control to pass / fail judgment by the comparator 400 is performed at every test cycle of the device under test. Here, in recent devices under test, the operating frequency has increased remarkably, and the test cycle has become faster accordingly. In particular, memories, CPUs (Central Processing Units), MPUs (Micro Processing Units), and the like have clock frequencies as high as several hundred MHz, and testing must be performed at their operating speeds. High speed operation is required.

  Accordingly, an object of the present invention is to provide a semiconductor test apparatus that can operate even when the test cycle becomes high and can maintain compatibility with a conventional system.

  As a result of diligent examination of the above problem, the inventors of the present invention have found that there is a problem in the time required to determine the next address after reading an instruction. That is, a device under test such as an IC must have a delay time from when a test pattern is given until a stable output signal is obtained. Therefore, conversely, it is necessary to give a test pattern to the device under test at the earliest possible timing within the test cycle. On the other hand, the number of pins is increasing as the functionality of ICs increases. When the number of pins increases, the time required for the decoding process for reading the instruction and determining the next address increases, so that the timing for providing the test pattern is inevitably delayed. For this reason, there is a problem of a delay from reading an instruction to determining a next address.

  From the above, it has been found that by omitting the time required for the decoding process, it is possible to operate even in a high-speed test cycle, and the present invention has been completed.

  That is, in order to solve the above-mentioned problem, a typical configuration of the semiconductor test method according to the present invention is to execute a pattern program stored in an instruction memory to control a multiplexer and set the execution address of the program to the next execution address. In a semiconductor test method for generating a test pattern to be updated and applied to a device under test based on a pattern generation instruction specified by the same address as the execution address, the multiplexer interprets the instruction memory corresponding to the sequence instruction of the pattern program. A possible select signal is stored in association with an address of the pattern program, and the multiplexer is controlled by using the select signal associated with the execution address by executing the pattern program.

  According to the above configuration, since the select signal that can be interpreted by the multiplexer is stored in the instruction memory in association with the address of the pattern program, the decoding process for converting the sequence instruction into the select signal during the test cycle is not required, and the processing speed is high. Therefore, even when the test cycle becomes high speed, the operation becomes possible.

  A decoding circuit that converts a sequence command for updating the execution address of the pattern program into a select signal is provided between the central control unit of the test apparatus and the instruction memory, and when the central control unit writes the pattern program to the instruction memory. It is preferable that the decode circuit converts the sequence command into a select signal and stores the select signal and the address of the pattern program in association with each other. With the above configuration, it is only necessary to perform writing from the central control unit to the instruction memory in the same manner as in the past, and compatibility with the conventional system can be maintained.

  Preferably, a sequence command for updating the execution address of the pattern program is stored in the instruction memory in association with the address together with the select signal, and the sequence control unit reads the sequence command. Thereby, the compatibility with the conventional system can be further maintained.

  An encoder circuit that converts a select signal into a sequence command for updating the execution address of the pattern program is provided between the central control unit of the test apparatus and the instruction memory, and the central control unit of the test apparatus is stored in the instruction memory. When reading the signal, it is preferable that the encode circuit converts the select signal into a sequence command. As a result, it is possible to further reduce the required memory amount of the instruction memory while maintaining compatibility with the conventional system.

  A typical configuration of the semiconductor test apparatus according to the present invention includes an instruction memory for storing a pattern program for controlling a multiplexer to update an execution address to the next execution address, and a pattern for storing a pattern generation instruction in association with the address. In a semiconductor test apparatus comprising a memory and a pattern generation circuit for generating a test pattern to be applied to a device under test based on a pattern generation instruction specified by the same address as the execution address of the pattern program, the instruction memory includes a pattern A select signal that can be interpreted by the multiplexer is stored in association with the address of the program. According to the above configuration, the decoding process for converting the sequence command into the select signal during the test period is not necessary, and the operation is possible even when the test period becomes high speed.

  A decoding circuit that converts a sequence command for updating the execution address of the pattern program into a select signal is provided between the central control unit of the test apparatus and the instruction memory, and when the central control unit writes the pattern program to the instruction memory. The decode circuit converts the sequence command into a select signal. With the above configuration, compatibility with a conventional system can be maintained.

  According to the present invention, the present invention can provide a semiconductor test apparatus that can operate even when the test cycle becomes high and can maintain compatibility with a conventional system.

  Embodiments of a semiconductor test method and a semiconductor test apparatus according to the present invention will be described. FIG. 1 is a diagram illustrating the configuration of a sequence control circuit according to the present embodiment, FIG. 2 is a diagram illustrating a pattern program stored in the instruction memory, and FIG. 3 is another configuration of the pattern program stored in the instruction memory. FIG. 4 is a diagram for explaining another configuration of the sequence control circuit. The same parts as those in the conventional example are denoted by the same reference numerals and the description thereof is omitted. Note that dimensions, materials, and other specific numerical values shown in the following examples are merely examples for facilitating the understanding of the invention, and do not limit the present invention unless otherwise specified.

  The semiconductor test apparatus according to the present embodiment controls the multiplexer by executing the pattern program stored in the instruction memory, updates the execution address of the program to the next execution address, and is specified by the same address as the execution address. A test pattern to be given to the device under test is generated based on the pattern generation command. The overall configuration of the semiconductor test apparatus is the same as the conventional configuration described with reference to FIG. In the semiconductor test apparatus according to the present embodiment, the configuration of the sequence control circuit 100 is different from the configuration shown in FIG.

  The sequence control circuit 100 shown in FIG. 1 includes an instruction memory 101, a decode circuit 104, a control circuit 106, a multiplexer 108, and a register 110. A characteristic difference from the sequence control circuit shown in FIG. 6 is that the CPU bus 114 between the central control unit 112 and the instruction memory of the test apparatus includes a decode circuit 104, and the instruction memory 101 and the control circuit 106. The decoding circuit 104 is not disposed between the two.

  The central control unit 112 controls the overall operation of the semiconductor test apparatus. The central control unit 112 writes the pattern program into the instruction memory 101 via the CPU bus 114. Here, the pattern program sent from the central control unit 112 is composed of an instruction code associated with an address (see FIG. 7), but a select that can be interpreted by the multiplexer by the decode circuit 104 at the time of writing. Convert to signal.

  Therefore, as shown in FIG. 2, the instruction memory 101 stores a select signal associated with the address of the pattern program. By executing the pattern program, the instruction memory 101 outputs a select signal, and the control circuit 106 performs an execution process for controlling the multiplexer 108 in accordance with the select signal. As a result, the execution address is updated, and address signals are successively output from the sequence control circuit 100.

  As described above, since a select signal that can be interpreted by the multiplexer is stored in advance in the instruction memory in association with the address of the pattern program, the decoding process for converting the sequence command into the select signal during the test period is not necessary. Therefore, since the processing can be speeded up, it is possible to operate even when the test cycle becomes high.

  Further, although the pattern program is rewritten by the decode circuit 104 inside the sequence control circuit 100, the central control unit 112, the CPU bus 114, and the supplied pattern program are not changed. For this reason, the central control unit 112 may perform processing for writing into the instruction memory 101 in the same manner as in the past, and compatibility with the conventional system can be maintained.

[Other Embodiments]
In the above embodiment, the instruction memory 101 has been described so as to store only the select signal associated with the address. However, the central control unit 112 may read the pattern program from the instruction memory 101 for operation verification (debugging). At this time, if only the select signal can be read from the instruction memory 101, it may be inconvenient.

  Therefore, the instruction memory 102 shown in FIG. 3 may store an instruction code (sequence instruction) for updating the execution address of the pattern program together with the select signal. With this configuration, the central control unit 112 can read the instruction code from the instruction memory 101 in association with the address. Therefore, the compatibility with the conventional system can be maintained. At this time as well, during the device test operation, only the bit in which the select signal is stored needs to be output from the instruction memory 101, so that the high speed operation is not lost.

  As shown in FIG. 4, the CPU bus 114 between the central control unit 112 and the instruction memory 101 may include an encoding circuit 116 that converts a select signal into an instruction code. As a result, even when only the select signal is stored in the instruction memory 101 (the state shown in FIG. 2), the central control unit 112 can acquire the sequence command from the instruction memory 101. With this configuration, it is possible to further reduce the amount of memory required for the instruction memory while maintaining compatibility with the conventional system.

  Although the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such examples. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention can be used as a semiconductor test apparatus for testing an IC circuit such as a semiconductor memory.

It is a figure explaining the structure of the sequence control circuit concerning embodiment. It is a figure explaining the pattern program stored in instruction memory. It is a figure explaining the other structure of the pattern program stored in instruction memory. It is a figure explaining the other structure of a sequence control circuit. It is a figure which shows the structure of the conventional semiconductor test apparatus. It is a figure which shows the structural example of a sequence control circuit. It is a figure explaining the pattern program stored in instruction memory. It is a figure explaining an instruction code.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Sequence control circuit 101 ... Instruction memory 102 ... Instruction memory 103 ... Instruction memory 104 ... Decoding circuit 106 ... Control circuit 108 ... Multiplexer 110 ... Register 112 ... Central control part 114 ... CPU bus 116 ... Encoding circuit 200 ... Pattern memory 300 ... Pattern generation circuit 400 ... Comparator 500 ... Device under test

Claims (6)

By executing the pattern program stored in the instruction memory, the multiplexer is controlled to update the execution address of the program to the next execution address, and based on the pattern generation instruction specified by the same address as the execution address In a semiconductor test method for generating a test pattern to be applied to a device,
In the instruction memory, a select signal corresponding to the sequence instruction of the pattern program and interpretable by the multiplexer is stored in association with the address of the pattern program,
A semiconductor test method, wherein the multiplexer is controlled using the select signal associated with an execution address by executing the pattern program. A decoding circuit that converts a sequence command for updating an execution address of the pattern program into the select signal is provided between a central control unit of a test apparatus and the instruction memory,
When the central control unit writes the pattern program into the instruction memory, the decode circuit converts the sequence command into the select signal, and stores the select signal and the address of the pattern program in association with each other. The semiconductor test method according to claim 1. A sequence command for updating the execution address of the pattern program is stored in the instruction memory in association with the address together with the select signal,
The semiconductor test method according to claim 1, wherein a central control unit of a test apparatus reads the sequence command. An encoding circuit for converting the select signal into a sequence command for updating an execution address of the pattern program between a central control unit of a test apparatus and the instruction memory;
2. The semiconductor test method according to claim 1, wherein the encode circuit converts the select signal into the sequence command when the central control unit of the test apparatus reads the select signal stored in the instruction memory. An instruction memory for storing a pattern program for controlling the multiplexer and updating the execution address to the next execution address;
A pattern memory storing pattern generation instructions in association with addresses;
In a semiconductor test apparatus comprising: a pattern generation circuit that generates a test pattern to be applied to a device under test based on a pattern generation instruction specified by the same address as the execution address of the pattern program;
A semiconductor test apparatus, wherein the instruction memory stores a select signal that can be interpreted by the multiplexer in association with an address of the pattern program. A decoding circuit that converts a sequence instruction for updating an execution address of the pattern program into the select signal is provided between the central control unit of the test apparatus and the instruction memory,
6. The semiconductor test apparatus according to claim 5, wherein when the central control unit writes the pattern program into the instruction memory, the decode circuit converts the sequence command into the select signal.

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