TWI413778B - Adjustable test pattern results latency - Google Patents

Abstract

A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.

Description

Adjustable test pattern result latency

The present invention relates to digital test instruments and methods, and more particularly to digital test instruments and methods for dynamically changing the sequence of patterns performed in a test using the result of the pattern.

The digital test instrument applies test excitation to the units under test (UUT) on several channels simultaneously during the performance of the functional digital test and collects test responses from the unit under test. A typical digital function test consists of a series of patterns. Each pattern includes the specifications of the test stimulus to be applied and/or the test response to be collected and the timing of such actions.

Digital test instruments typically provide a means to compare the collected test responses to expected responses and produce pass or fail test results for each channel in the instrument that indicates whether the actual response is for that channel on a particular model. Matches the expected response. A type of individual channel result is logically combined to produce a total test result for the pattern. The pattern results are then logically combined to produce a total test result for the complete test.

The digital test instrument can include a hardware component called a pattern controller that determines the particular sequence of patterns that are executed during the digital test. In such instruments, instructions for generating test stimuli and/or collecting test responses are stored in a pattern memory, and instructions for a particular pattern are at a particular address within the memory. The pattern controller generates a test pattern sequence for testing by controlling the sequence of addresses applied to the pattern memory. In a simple test The pattern controller can generate a linear pattern sequence by incrementing the pattern memory address. In more complex tests, the pattern controller can generate a sequence of pattern memory addresses that skip certain patterns, or can cause the entire pattern to be executed several times during test execution.

Typically, model results are only stored in the digital test instrument hardware during the execution of the test and are captured after the test is completed to provide diagnostic information to help isolate and diagnose defects on the UUT. However, digital test instruments can also use pattern results to dynamically change the pattern sequence executed during the test. To accomplish this, the test instrument is typically designed such that the pattern controller is on a particular model and one of two actions can be performed based on the settings of the total test results for that pattern.

The delay between the time the test pattern is applied to the unit under test and the time at which the test pattern result is applied to the pattern controller is referred to as the pass/fail result latency, or simply the resulting latency. In high-speed test instruments that rely on pipelining techniques to achieve their high-speed performance, this latency is usually expressed in several forms. The user of the digital test instrument must calculate this latency when writing a test program that is executed on the instrument and uses its conditional execution capabilities.

As an example, consider the test application shown in Figures 1A and 1B in which a digital test instrument having a four-type resulting latency is used to detect when the output of the synchronous counter 10 reaches a zero state. Patterns 1-5 form a conditional loop that counts the counter once for each repeated loop and exits when the counter output is all low.

The digital function test program is expensive to develop and once verified and deployed, In case of reluctance to modify these programs. These test programs can be used for many years and the service life can be easily longer than the test equipment originally designed to execute the test program. When migrating such test programs to a new test system with different digital test instruments, the new digital test instrument should provide the same latency as the initial digital test instrument.

However, as a general trend, the maximum speed of digital test instruments has increased over time. The higher the computing speed, the more pipeline stages, and the higher the latency. This increased latency can "break" the test program for the job.

2 is an example of an execution trace illustrating the operation of the test program of FIG. 1B on a first digit test instrument having a latency of four pattern cycles. As shown in Figure 2, the test program is properly executed on the first digital test instrument.

3 is an example of an execution trace illustrating the operation of the test program of FIG. 1B on a second digit test instrument having a latency of nine pattern cycles. As shown in Figure 3, the test program is not properly executed on the second digit test instrument.

Therefore, there is a need for digital test instruments and test methods that overcome the problems of executing an existing test program on a digital test instrument having different latency times.

The present invention provides an aspect of the problem of performing an existing test program on a newer digital test instrument, which is an alternative method of collecting and distributing via pass/fail test results. Not based on fixed The pipeline method to process the test results, the present invention provides an architecture to configure the test result latency to match the requirements of the test program, allowing the test program to execute in its initial verification state.

According to a first aspect of the invention, a digital test instrument is provided. The digital test apparatus includes: a type controller configured to generate a test pattern sequence at least partially in response to a pass/fail result; a type memory configured to provide the generated test pattern sequence to a type of result collecting unit configured to receive at least one result value from the unit under test and to determine pass/fail results for at least one of the provided test patterns; and a synchronization unit configured to be tested After the start, a no-result indication is provided to the pattern controller during a preset number of pattern cycles. The preset number of pattern cycles is based on the result latency of the test instrument and provides pass/fail after a preset number of pattern cycles Pass the result to the pattern controller.

According to a second aspect of the invention, a method for digital testing is provided. The method includes: generating a test pattern sequence at least partially in response to a pass/fail result in a type controller; providing the generated test pattern sequence to the unit under test; in response to receiving the result from the unit under test a value, a pass/fail result is determined for at least one of the provided test patterns, wherein the pass/fail result is available after the result latency; a no result indication is provided during a preset number of pattern cycles after the test begins The sample controller, the preset number of pattern cycles is based on the resulting latency; and provides pass/fail results to the pattern controller after a predetermined number of pattern cycles.

According to a third aspect of the invention, a method for digital testing is provided. The method includes: at least partially responding to a pass in a type controller Passing/failing to produce a test pattern sequence; providing the generated test pattern sequence to the unit under test; in response to the result value received from the unit under test, determining pass/fail for at least one of the provided test patterns Result; selecting a result condition including no result indication during a preset number of pattern cycles after the start of the test, and selecting a result condition including one of the pass/fail results after the preset number of pattern cycles; Select the result condition to the pattern controller.

For a better understanding of the invention, reference is made to the drawings, which are incorporated by reference.

A simplified block diagram of a digital test apparatus in accordance with a first embodiment of the present invention is shown in FIG. Channel logic block 20 represents the logic responsible for controlling the application of the test pattern to the UUT on each channel of the digital test instrument and the digital test instrument from which the test response was collected. The settings of the test pattern and the expected responses are stored in the pattern memory 22. The pattern controller 24 controls the address lines of the pattern memory 22 to generate a test pattern sequence and respond to the collection of collections. The pattern controller 24 is a processor that executes a test program by accessing a sequence of instructions in the pattern memory 22 and generating a test pattern applied to the unit under test. Pattern result collection unit 30 includes logic that combines various test result values from various channels for each pattern to produce a total pass/fail test result for that pattern.

The digital test instrument further includes a synchronization unit 32 that receives the pass/fail results from the pattern result collection unit 30 and provides The result condition is supplied to the pattern controller 24. Synchronization unit 32 provides a no-result indication to pattern controller 24 during a predetermined number of pattern cycles after the test begins or resumes. The preset number of pattern cycles corresponds to the resulting latency of the test instrument. After a predetermined number of pattern cycles, the synchronization unit 32 provides pass/fail results to the pattern controller 24.

In the embodiment of FIG. 4, the synchronization unit 32 includes a FIFO 40, a multiplexer 42, a FIFO 44, and a counter 46. The FIFO 40 receives and stores the pass/fail results generated by the pattern result collecting unit 30. The multiplexer 42 can be a 2:1 multiplexer having a first input that receives a no-indication indication, a second input that receives a pass/fail result from the FIFO 40, and a control input coupled to the counter 46. . The output of multiplexer 42 is coupled to the input of FIFO 44. The FIFO 44 provides the resulting conditions to the pattern controller 24. The resulting conditions can affect the test pattern sequence generated by the pattern controller 24. Counter 46 controls multiplexer 42 and thus controls the source of the resulting conditions provided to FIFO 44.

Initially, the multiplexer 42 is set such that the value indicating "no result" is passed to the FIFO 44 and then passed to the pattern controller 24. Counter 46 is set to count down from zero to zero on each pattern. When counter 46 reaches zero, it switches the source of the input to FIFO 44 from the "no result" indication to the output of FIFO 40.

The FIFO 44 produces new values for the resulting conditions for each test pattern generated by the pattern controller 24. The first N values of the resulting condition are no result indication, where N is determined by the preset value of counter 46. The first N+1 value is the first pass/fail result provided to the FIFO 40, which is the first test type for the test. Sample test results. The first pass/fail result provided to the pattern controller 24 is the result of the first test pattern performed by the pattern controller. Pass/fail results are not skipped or ignored; only delayed until the model controller is available. The N value is preset based on the resulting latency and the N value can be programmed to enable the digital test instrument to simulate a variety of digital test instruments.

By way of example, the pattern controller 24 can receive the two-dimensional result condition from the FIFO 44, including the pass bit and the fail bit. The pass is indicated by the setting state of the bit, and the setting state of the unpassed bit indicates that the pass has not passed. In this example, each input of multiplexer 42 has a width of two bits, and FIFO 44 has a width of two bits. The pattern controller 24 is programmed by the test program to perform a specified action in response to one of the set two bits, that is, to change its operation. When the pattern controller 24 receives the no-response indication, the two-digits are reset and the specified action is not performed. Examples of actions performed by pattern controller 24 in response to pass/fail results include, but are not limited to, jumping to another location in the test program; repeating or exiting the loop in the test program; pausing the test program; and continuing The next instruction in the sequence of instructions.

Pattern controller 24 is typically set to change its operation based on whether a single condition (pass or fail) is true. The no-result indication forces both the pass and fail conditions to be false, and the pattern controller 24 does not change its operation. When the pattern controller is set to change its operation in response to the true state of the condition, the true state of the unconditional condition or the no-result indication does not change the operation. Similarly, when the pattern controller is set to change its operation in response to the true state of the unpassed condition, the operation is not changed by the true state of the condition or the no result indication.

In the embodiment of FIG. 4, counter 46 can be preset to have a value based on the resulting latency of the digital test instrument. By way of example only, in the case where the digital test instrument has a latency of N+1 pattern cycles, the counter 46 can be preset to cause the multiplexer control line to change state after N cycles of the pattern. Preset values corresponding to different result latency times can be utilized. Counter 46 is enabled by the start counter signal and is clocked by the pattern clock. Each type of clock cycle corresponds to a new test pattern produced by the pattern controller 24. The start counter signal can initially be provided at the beginning of the test or when the test is restarted after resetting the pattern controller 24. The start counter signal and the pattern clock can be provided by the pattern controller 24.

In one embodiment, counter 46 is clocked by the pattern clock to count down to zero from a preset value. The output provided to multiplexer 42 remains in the first state in which the no result indication is selected until counter 46 counts down to zero. Thereafter, the output of counter 46 is switched to a second state that selects the pass/fail result provided by FIFO 40 to multiplexer 42. It will be appreciated that different configurations can be utilized to control the multiplexer 42 within the scope of the present invention.

For the resulting latency of the N+1 pattern cycle, the counter or other multiplexer control logic is set to select a no-result indication from the beginning of the test until the pattern cycle N ends, and thereafter the pass/fail results are selected. Therefore, no result indication is selected until the pattern controller 24 can utilize the pattern cycle of pass/fail results. It will be appreciated that different multiplexer control techniques may be utilized, including incrementing or decrementing to a specified number, such as zero, and other multiplexer control logic configurations within the scope of the present invention may be utilized. In any multiplexer control technique, the number of pattern cycles can be stylized to accommodate different results. The latency value, the number of pattern cycles during the no-result indication is provided to the pattern controller.

In the embodiment of FIG. 4, the FIFO 40 serves as a buffer between the pattern result collecting unit 30 and the multiplexer 42. Similarly, FIFO 44 acts as a buffer between multiplexer 42 and pattern controller 24. In some embodiments, one or both of FIFOs 40 and 44 may be omitted.

Figure 5 is a simplified block diagram of a digital test instrument showing a first example of the implementation of a synchronization circuit. The same elements in Figures 4 and 5 have the same element symbols. In the execution of Fig. 5, the pattern result collecting unit 30 produces a pass/fail result of a single bit. The FIFO 40 receives the pass/fail results from the pattern result collection unit 30 and provides a pass/fail result to the B input of the multiplexer 42b and the inverter 60. The output of inverter 60 provides an inverted pass/fail result to the B input of multiplexer 42a. A "0" logic level is provided to the A inputs of multiplexers 42a and 42b. The outputs of multiplexers 42a and 42b are provided to FIFOs 44a and 44b. Multiplexers 42a and 42b receive multiplexer control signals from counter 46 as described above. The FIFO 44a provides a pass condition to the pattern controller 24, and the FIFO 44b provides a fail condition to the pattern controller 24. When the multiplexers 42a and 42b select the "0" logic level, both the pass condition and the fail condition are false. Providing a "0" logic level to both multiplexers 42a and 42b ensures that the pattern controller 24 will not branch based on any pass/fail conditions until the resulting latency period expires.

In the implementation of Figure 5, the pass/fail results are encoded such that the pass = "1" logic level and pass = "0" logic level. If the position of the inverter 60 is shifted from the B input of the multiplexer 42a to the B input of the multiplexer 42b, then The opposite encoding can be used.

In the execution of FIG. 5, the pattern result collecting unit 30 provides a pass/fail result of a single bit. In other implementations, the pattern result collection unit 30 can provide a two-pass pass/fail result. An example is described below in conjunction with Figures 8A and 8B.

A timing diagram illustrating the operation of the synchronization unit is shown in FIG. As shown in FIG. 6, the multiplexer control signal selects a no-response indication on input A during the start of the test and during a predetermined number of pattern cycles based on the resulting latency. Next, the multiplexer control signal switches states and selects the pass/fail results on input B until the test is complete or until the pattern controller 24 resets or restarts. For the resulting latency of the N+1 pattern cycle, the multiplexer control signal switches states at the end of the pattern loop N.

A table illustrating an example of the resulting conditional state is shown in FIG. In the example of Figure 7, the resulting condition has two bits, one of which indicates passage and one of which indicates failure. The no-result condition corresponds to both the pass and fail bits being reset. Depending on the particularity of the test, the pattern controller 24 as described above may cause an alternate action by the setting condition of the bit or the setting condition of the non-passing bit. The no-response indication does not cause an alternate action, and the pattern controller 24 continues its normal sequence of operations. After providing a no-result indication to the preset number of pattern cycles of the pattern controller 24, a pass/fail result for each pattern cycle is provided to the pattern controller 24. In some embodiments, the pass/fail results may include an identifier of the test pattern. It should be understood that the resulting condition can have any desired format and number of bits.

8A is a digital test instrument showing a second example of the implementation of a synchronous circuit. A simplified block diagram. The same elements in Figures 4, 5 and 8A have the same element symbols. In the execution of FIG. 8A, the pattern result collecting unit 30 generates a two-element pass/fail result. The FIFO 40 receives the pass/fail results from the pattern result collection unit 30 and provides a two-element pass/fail result to the conditional logic finite state machine 70. The output of conditional logic finite state machine 70 is provided to FIFOs 44a and 44b. The FIFO 44a provides a pass condition to the pattern controller 24, and the FIFO 44b provides a fail condition to the pattern controller 24.

The truth table for the conditional logic finite state machine 70 is shown in Figure 8B. The incoming pattern result from FIFO 40 is shown in the first row, the state of counter 46 is shown in the second row, and the pass and fail conditions of the previous pattern loop are shown in the third and fourth rows, and Pass/fail conditions provided to FIFOs 44a and 44b, respectively, are shown in the fifth and sixth rows. When the counter 46 is not at zero, the false state is output on the pass condition and the fail condition line, corresponding to the no result indication. The remaining states indicate that the counter 46 is at zero and the output is passed when the pass/fail result is selected. When the unsuccessful result from the FIFO 40 is received, the true state is output on the failed condition line. When the result of the pass from the FIFO 40 is received, the true state is output on the pass condition line. Previous pass/fail conditions are not related to these states. The remaining three states illustrate the operation during the pattern cycle when the pattern result is not received from the FIFO 40. In these states, the previous pass/fail condition is maintained for the current pattern cycle. Therefore, in the case where the previous pass/fail conditions are both false, the new pass/fail conditions are also false. When the previous fail condition is true, the true state is output on the failed condition line. Similarly, when the previous pass condition is true, the true state is output on the pass condition line. Figures 8A and 8B The examples accommodate conditions that produce results on some, but not all, of the pattern loops.

The present invention provides a general solution for simulating how a variety of older digital test instruments handle type test results. Currently, digital test instruments have a fixed latency that does not necessarily match the requirements of older test programs, but is adjusted to generally higher instrument operating speeds than older generation instruments.

In addition, the present invention allows the user to perform tests that require latency in the zero pattern cycle between the time the test is performed and the time the action is taken. This is done without compromising the timing flexibility and programmability of high-speed, high-performance digital test instruments.

As noted above, the resulting latency is typically defined as the delay between the time the test pattern is applied to the unit under test and the time the test pattern result is applied to the pattern controller. However, the present invention is not limited to this definition and can be utilized in any situation where it is required to control the application of pass/fail results to the pattern controller.

Having thus described several aspects of at least one embodiment of the present invention, it will be appreciated that those skilled in the art will readily recognize various changes, modifications and improvements. Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to be within the spirit and scope of the invention. Accordingly, the above description and illustration are by way of example only.

10‧‧‧Synchronous counter

20‧‧‧ channel logic block

22‧‧‧ Type memory

24‧‧‧Model Controller

30‧‧‧ Type result collection unit

32‧‧‧Synchronization unit

40‧‧‧FIFO

42‧‧‧Multiplexer

42a‧‧‧Multiplexer

42b‧‧‧Multiplexer

44‧‧‧FIFO

44a‧‧‧FIFO

44b‧‧‧FIFO

46‧‧‧ counter

60‧‧‧Inverter

70‧‧‧ Conditional Logic Finite State Machine

A‧‧‧ input

B‧‧‧ input

1A illustrates an example of a circuit to be tested; FIG. 1B illustrates a simplified example of the circuit test program for FIG. 1A; FIG. 2 is an example of an execution trace illustrating four pattern loops The result of the test procedure of Figure 1 of the prior art on the first digit test instrument of the latency time; Figure 3 is an example of an execution trace illustrating the second digit test instrument with the latency of the results of the nine pattern cycles Figure 4 is a simplified block diagram of a digital test instrument in accordance with an embodiment of the present invention; and Figure 5 is a simplified block diagram of a digital test instrument showing a first example of the implementation of a synchronization unit. Figure 6 is a timing diagram illustrating the operation of the synchronization unit; Figure 7 is an example table illustrating the different result conditions provided to the execution of the mode controller of Figure 5; Figure 8A is a digital test instrument showing a second example of the implementation of the synchronization unit A simplified block diagram; and FIG. 8B is a truth table of the conditional logic finite state machine of FIG. 8A.

20‧‧‧ channel logic block

22‧‧‧ Type memory

24‧‧‧Model Controller

30‧‧‧ Type result collection unit

32‧‧‧Synchronization unit

40‧‧‧FIFO

42‧‧‧Multiplexer

44‧‧‧FIFO

46‧‧‧ counter

A‧‧‧ input

B‧‧‧ input

Claims (20)

A digital test apparatus comprising: a type controller configured to generate a test pattern sequence at least in part in response to a pass/fail result; a type of memory configured to provide the generated test pattern Sequence to a unit under test; a type result collection unit configured to receive at least one result value from the unit under test and determine a pass/fail result for at least one of the provided test patterns; and a synchronization unit, setting Providing a no-result indication to the pattern controller during a predetermined number of pattern cycles after the start of the test, the preset number of pattern cycles being based on a result latency of the test instrument, and A predetermined number of patterns are cycled to provide pass/fail results to the pattern controller. The digital test instrument of claim 1, further comprising two or more channel logic units coupled between the pattern memory and the unit under test to provide pattern information to the unit under test Individual channels and receive result values from the individual channels of the unit under test. The digital test apparatus of claim 2, wherein the type result collection unit is configured to determine a pass/fail result of the at least one provided test pattern as a logical combination of one of the individual channel result values. The digital test apparatus of claim 1, wherein the synchronization unit comprises a multiplexer having a first input for receiving the no-indication indication and a first for receiving a pass/fail result Two input and And a control input for switching from the no-result indication to the pass/fail result after the preset number of patterns is cycled. The digital test apparatus of claim 4, wherein the synchronization unit further comprises a first FIFO buffer coupled between the output of one of the multiplexers and the pattern controller. The digital test apparatus of claim 5, wherein the synchronization unit further comprises a second FIFO buffer coupled between the pattern result collection unit and the second input of the multiplexer. The digital test apparatus of claim 6, wherein the synchronization unit further comprises a counter having an output coupled to the control input of the multiplexer, and the counter is set to count the preset number Sample cycle. A digital test instrument as claimed in claim 1, wherein the pattern controller is configured to change the test pattern sequence in response to the pass/fail results. The digital test apparatus of claim 1, wherein the synchronization unit is configured such that the number of pattern cycles can be programmed, and the no-result indication is provided to the pattern controller during the number of pattern cycles. The digital test apparatus of claim 1, wherein the synchronization unit is configured to provide a test during the preset number of pattern cycles based on the result latency when the test is restarted after the pattern controller is reset This no result is indicated to the pattern controller. The digital test instrument of claim 1, wherein the synchronization unit comprises a conditional logic finite state machine, the conditional logic finite state The machine has a result input for receiving a pass/fail result, a control input for switching from the no-result indication to the pass/fail result after the preset number of patterns is cycled, and a Pass and fail condition output. A method for digital testing, comprising: generating a test pattern sequence at least partially in response to a pass/fail result in a type controller; providing the generated test pattern sequence to a test Unit; determining, for at least one of the provided test patterns, a pass/fail result in response to a result value received from the unit under test, wherein the pass/fail result is available after a result latency; in a test Providing a no-result indication to the pattern controller during a predetermined number of pattern cycles after starting, the preset number of pattern loops is based on the result latency; and after the preset number of pattern cycles , pass/fail results are provided to the model controller. The method of claim 12, wherein providing the generated test pattern sequence comprises providing pattern information to individual channels of the unit under test. The method of claim 13, wherein determining a pass/fail result comprises determining a logical combination of one of the individual channel result values. The method of claim 12, wherein generating a test pattern sequence comprises changing the test pattern sequence in response to the pass/fail result. The method of claim 12, further comprising setting a number of the pattern based on one of the result latency times, the no-state indication being provided to the pattern controller during the number of pattern cycles . The method of claim 12, further comprising, when the test is restarted after the pattern controller is reset, providing the non-result indication to the preset number of pattern cycles based on the result latency Model controller. A method for digital testing, comprising: generating a test pattern sequence at least partially in response to a pass/fail result in a type controller; providing the generated test pattern sequence to a test a unit; for at least one of the provided test patterns, in response to a result value received from the unit under test, determining a pass/fail result; selecting to include a period during a predetermined number of pattern cycles after the start of the test No result indicates a result condition, and a result condition including a pass/fail result after the preset number of pattern cycles is selected; and the selected result condition is provided to the pattern controller. The method of claim 18, wherein generating a test pattern sequence comprises changing the test pattern sequence in response to the pass/fail result. The method of claim 18, wherein the pass/fail result is available after a result latency, further comprising setting the number of cycles of the pattern based on the latency of the result, during the cycle of the number Select this no result indication.