JP2713994B2 - Package structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a high-density pitching of a pin array (PGA) package pin in a V-LSI mounting of an ultra-large computer which requires high-speed and high-density mounting. The present invention relates to a package structure having high reliability.

[Conventional technology]

FIG. 2 shows a known example of a pin structure to which solder 44 is attached. The pin 1 is fixed by a through hole 3 of a pin mounting board 2 and a land 4 provided on the board 2.

The pinned structure can be expected to have higher reliability than the planar mounting method in terms of the mechanical strength of the connection portion and the temperature cycle resistance. However, as the demand for high-speed, high-density mounting has increased,
There is no room to provide land portions for reinforcing pins.
Furthermore, as thin-film wiring of polyimide or the like comes to be used as modules become more sophisticated, forming a thin film on a module substrate structure pinned with silver brazing or the like from the beginning is a problem in the process. There is. Therefore, there is a demand for pinning by soldering so as not to affect the polyimide, the thin film and the like in a later step. In the structure of the known example, since the pin fixing portion of the through hole 3 and the soldered portion are simultaneously melted, there is a problem in terms of process and reliability.

On the other hand, with the demand for high-speed computers, it has become essential to use glass ceramic multilayer boards and mullite multilayer boards having a low dielectric constant.

These ceramics have a smaller coefficient of thermal expansion (3 to 4 × 10 ⁻⁶ / ° C.) and are brittle materials as compared with the Al ₂ O ₃ substrate that has been used. For this reason, the pins brazed on the module substrate made of ceramics form a multilayer printed circuit board having a high coefficient of thermal expansion (plane direction α = 15 × 10 ⁻⁶ / ° C.) and a low dielectric constant.
In the structure soldered to the through hole, the outermost pins of the large module board undergo large deformation, and a large force acts on the pinned portion. For this reason, as shown in FIG. 2 (b), the area of the pinned portion is enlarged, and the head portion 42 of the pin and the brazed terminal portion 11 are reduced so as to reduce the stress of the pinned portion.
In order to ensure a sufficient area (or a soldered portion) or to prevent the ceramic 43 from being broken at the interface between the metallization and the ceramic, a joint with a highly reliable pin such as a cover coat has been devised. However, in the prior art, a nail head portion, a metallized portion, or a metallized protection portion having a large pin has become an obstacle to the high-density pitch in the high-density other pin structure.

In order to connect a pin having a pin diameter of 150 μm at a 300 μm pitch level with high reliability and high accuracy, it has become impossible to provide a nail head space in terms of space. For this reason,
For pin bending, it has become important to ensure high reliability of the pinned portion.

4 [Problems to be Solved by the Invention] The above prior art does not have a pin structure corresponding to ultra-high-density mounting in response to a demand for a high-density and multi-pin large-scale high-speed calculation module board, and In the case where the conventional technology is compatible with ultra-high-density mounting, there has been a problem that high reliability cannot be ensured in the pinned portion.

An object of the present invention is to provide a pin after the formation of the polyimide thin film, from the compatibility with the thin film formed on the substrate, after the flip-chip connection, or after the solder sealing after the flip-chip connection, An object of the present invention is to provide a structure and a method for enabling an ultra-high-density multi-pin structure by a low-temperature process.

That is, an object is to realize a high-density multi-pin structure with high reliability.

[Means for solving the problem]

In order to connect with a high-density pin pitch, do not provide a land area that takes up space on the module board to fix the pins, uniformly reinforced with resin, or use a new pin carrier and connect with a bumping method, The structure is such that the resin is filled and reinforced.

Specifically, a first substrate in which the front terminal and the back terminal are electrically connected, a chip connected to the front terminal of the first substrate, and a plurality of pins connected to the back terminal of the first substrate. And a second substrate having a plurality of through holes, filling the through holes with resin, and holding the corresponding pins.

In order to realize a high-density pin pitch, we devised the pin diameter to be the terminal diameter immediately. Therefore, by adopting a structure in which the pin end face is soldered to the terminal of the module substrate as it is, it is possible to realize the same level of density as the planar mounting with the pin structure. For the reinforcement of the connection portion, a resin having a thermal expansion coefficient substantially equal to that of the solder and having rubber fine particles dispersed for heat shock resistance was used. Curing condition of resin is 150 ℃ (max)
Since the soldering temperature is 260 ° C (max) in × 10 hours,
Enables high-density pin pitch without affecting the package.

[Action]

Conventionally, a high-density pin pitch of 1/4 to 1/5 level can be realized with respect to a conventionally used minimum pin pitch of 1.27 mm.
In addition, by filling with a specific resin and reinforcing it, it has an excellent effect on the reliability of the pinned part, ie, temperature cycle resistance, impact resistance, mechanical strength, moisture resistance, dirt prevention, etc. Can be expected.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIG. 1, FIG. 3, FIG. 5 to FIG.

FIG. 3 shows a sectional view of the assembling process. (A) shows Si on which solder 8 (Pb-5% Sn, melting point 305 ° C.) bump is formed.
Chip 9. (B) is a carrier substrate 10 made of low dielectric constant glass ceramics. On the surface of the carrier substrate 10, a terminating resistor for impedance matching required for high speed operation and a thin film wiring layer are formed. A polyimide film 21 was used as an insulating layer. The thin film resistor is a Cr-Si-O type, and a resistance change occurs at 350 ° C or higher, so that a post-process at 350 ° C or lower is required. Similarly, a capacitor may be built in the carrier substrate for speeding up. (C) shows a method of embedding a pin having Ni-Au attached to Kovar having a diameter of 130 μm with a pitch of about 300 μm in a resin 15, flattening one side with the resin, and flattening the surface.
Pin-mounted carrier board that has been plated 14 and dipped (immersion soldered) with Sn-3.5% Ag (melting point 221 ° C) solder 7 or Sn-5% Sb (melting point 240 ° C) solder and pre-soldered It is 15. (D) shows a structure in which the chip (a) and the carrier substrate (b) are connected and then the resin 16 is filled.
(E) is obtained by pre-soldering the back surface of the chip carrier of (d) using solder having the same composition as that of (c), and then positioning and soldering (c). FIG. 4 shows the structure shown in FIG. 4 in which resin is filled between the carrier substrate and the pin mounting substrate.

The resin of the pin mounting carrier substrate is a reinforcement for bending deformation of the pins. Further, by filling the resin, the service life of the soldered portion is improved and the reinforcement is ensured. However, the thermal expansion coefficient of the resin is almost equal to that of the solder. The thermal expansion coefficient of the pin mounting carrier substrate is desirably 7 to 10 × 10 ⁻⁶ / ° C. or less.

FIG. 1 is an enlarged view of a thin film resistor formed on a carrier substrate 10. Al conductor 18 on Si chip 9 and SiO ₂
19 A connection terminal 20 (Cr-Cu-Au) is formed on the insulating film. The carrier substrate material was glass ceramics, and copper paste conductor 19 was used. After the carrier substrate surface is flattened, polyimide 21 is used except for the copper paste terminals exposed on the surface.
And then form a Cr-Si-O22 resistive thin film on it,
Further, Cr-Cu-Au20 was formed as an electrode terminal.

 FIG. 5 shows a method of manufacturing a pin mounting plate.

A metal mask 23 having pin holes and a metal mask 24 for spacers are overlapped with the terminal pitch of the carrier substrate in advance, and long pins 25 are inserted into each hole. The metal mask and the metal mask for the spacer are pre-released
(Silicone-based resin) is applied, and a surface treatment is applied so that the resin can be easily separated. The thickness of the spacer metal mask corresponds to the pin protrusion length. The spacer metal mask gap corresponds to the thickness of the pin mounting substrate. When the resin is filled and the cross section AA '27 near the spacer metal mask is cured and cut with a dicer or the like, two pin mounting substrates can be formed (a large number can be formed by stacking in multiple stages). Then, the metal mask for the space and the substrate for pin mounting are separated, and cut to the size of the carrier substrate. FIG. 5 (b) shows a cross section in which the end surface of the pin mounting substrate is flattened, Ni-Au plating is applied, and then Sn-5% Sb solder 7 is pre-soldered. In this case, the resin and the pin need to be a combination excellent in adhesion and moisture resistance (PCT resistance). The pin surface may be provided with a Ni plating that is not easily damaged by solder, and a thin Au plating may be applied to ensure storage and solderability.

As another method of manufacturing the pin mounting substrate, there is a method of forming the pins by etching a foil, passing the pins through holes while aligning the pins, and positioning each row.

 FIG. 6 shows various package structures.

(A) is a case where a resin is used as the pin mounting carrier substrate 15; (b) is a case where a heat diffusion plate 28 (for example, high thermal conductive SiC, AlN, CuC, etc.) is mounted on the back surface of the chip, and as a pin mounting substrate, In the case where resin 16 is filled in the gap between the pins using polyimide, glass epoxy, kepra, etc., (c) is the case where the carrier substrate and the substrate for pin mounting are used (in the resin, artificial diamond, SiC, etc. (D), when the gap between the carrier substrate and the pin mounting substrate is narrow, the hole 30 is provided in the center of the pin mounting substrate, so that the resin can flow well. , And it becomes easy to make a void dress.

(E) shows a structure in which the pins are soldered with Sn-5% Sb7 and then the resin 16 is used to reinforce the pinned portions.

(F) shows a hermetically sealed carrier having a pin carrier structure.

FIG. 7 shows a low-expansion, low-dielectric-constant organic substrate 32 for pin mounting.
(Epoxy or polyimide material containing low expansion glass fiber or Kepler fiber, the thermal expansion coefficient of the substrate is 7-9
(× 10 ⁻⁶ / ° C) with a laser, electron beam or drill to make a hole larger than the pin diameter. It is a pin mounting carrier substrate adhered. The through-holes were barely accessible for pins, and had no lands that hinder high density. When the end face of the substrate is immersed in the resin, the resin penetrates the narrow through hole by the action of surface tension. After the resin is cured, the terminal side of the carrier substrate is subjected to surface grinding 33 and the pin end surface is subjected to Ni-Au plating 14 to form connection terminals. Since this pin carrier has a low expansion, even if it is directly connected to the Si chip by the flip chip method, if the space between the chip and the carrier is filled with a resin, a highly reliable pin carrier structure is obtained. In addition, since the pin carrier for connecting the glass carrier substrate has almost the same heat application coefficient, high reliability can be expected.

FIG. 8 shows an embodiment in which a high-output pin grid array package is mounted on a multilayer printed board 49 having a low dielectric constant. Since it is a multi-pin, high-density thin wire pin, it is configured to be used in a state inserted into the non-through through hole 34. If the tip of the pin is partially inserted, there is no need to worry about creep resistance of the solder against the horizontal and vertical forces 38 pushing the chip back surface. Also, the pin structure deforms the pin even if the thermal expansion difference between the carrier substrate and the multilayer printed board is large, so there is no concern about the reliability of the temperature cycle. The bending stiffness of the pin is controllable.

The solder joint of the flip chip between the chip and the carrier substrate has the same thermal expansion coefficient as solder, and
The use of resin to which rubber particles for thermal shock are added significantly improves the temperature cycle life.
No. 58-17192.

According to the present embodiment, the same resin is filled in the gap between the chip carrier and the resin for pin fixing, so that problems such as temperature cycling resistance, mechanical strength, moisture resistance, and protection from dust adhesion and the like can be solved. Will be resolved.

The presence or absence of resin between the carrier substrate and the pin mounting substrate has a significant effect on reliability. It has the same coefficient of thermal expansion as solder (25 × 10 ^-6 / ° C) and is made of polybutadiene or
Disperse silicone rubber, low Young's modulus (400-700kg
f / mm ² ), the stress and strain applied to the solder were significantly reduced as compared to the resin-less structure, and the temperature cycle resistance could be improved ten to twenty times. The cause of the improvement of the life is as follows. As a result of the thermal elasto-plastic analysis by the finite element method, (1) the resin alleviates the stress concentration concentrated on a part of the solder bump.

(2) The coefficient of thermal expansion of the resin is matched with that of the solder.

(3) The fine spherical polybutadiene (or silicone) dispersed in the resin reduces the thermal shock.

(4) It is considered that the stress applied to the stress concentration portion is small due to low Young's modulus.

The mixing ratio of quartz powder is limited to 60 to 65% by volume based on the whole resin. The mixing ratio of polybutadiene is limited to 20 parts by weight. 30-60% by volume of quartz powder, 5-15 of polybutadiene
Parts by weight are desirable.

 The used resin composition is as follows.

This resin has low expansion comparable to that of solder, but has good fluidity, and penetrates and fills the gap between the carrier substrate and the pin mounting substrate by the action of surface tension.

Table 1 shows the relationship between the resin composition and the mixing ratio of the quartz powder as the low expansion material and the polybutadiene as the buffer material, and the thermal fatigue life judgment (寿命: good, Δ: almost good, ×: bad).

About 1-2% of a carbon black was added to the resin, and the resin was colored black.

The low expansion material other than quartz can be any material made of at least one of alumina, silicon carbide, silicon nitride, aluminum nitride, calcium carbonate, and silicon carbide mixed with beryllium oxide.

As an elastic material other than polybutadiene, one made of at least one of polyisoprene and silicone is also possible.

In particular, when high temperature resistance and moisture resistance are required, acid anhydride and silicone as a rubber are preferable instead of dicyanamide as a curing agent.

As the input / output pin structure for high-speed computer calculation,
This is an example applied to a highly-reliable pin structure of a high-density, multi-terminal multilayer flexible tape in order to run a number of wirings such as a power supply, a signal, and a ground in parallel.

FIG. 9 shows an application to connector connection. Copper terminals 41 are exposed on the lowermost surface of the multilayer flexible tape 39, and the periphery is covered with polyimide 16 or epoxy resin.

Pin pitch is 250 μm, pin diameter is 150 μm, and pin end face is Ni
-Au plating is applied.

Solder is Sn-5% Sb7 (melting point, liquid phase 240 ℃, solid phase 232)
° C), the eutectic solder Pb-60
% Sn (melting point: 183 ℃, soldering temperature: 220 ℃)
Alternatively, the Sn-5% Sb solder is not melted during repair.

As the tape, a Teflon-based or polyimide-based tape having a low dielectric constant, which is advantageous for speeding up signals, was used. By this method, many pins,
It is possible to realize a high density pitch soldered connector.

The protection effect of the resin is effective not only in temperature cycle resistance, humidity resistance, and vibration resistance (there is no resonance due to integration with the resin), mechanical resistance, but also protection against dust adhesion.

With respect to a high output V · LSI chip, it is possible to eliminate anxiety about creep deformation of a soldered joint due to a lateral force applied to the joint when water cooling the rear surface of the chip.

Furthermore, since the difference in thermal expansion between the chip and the multilayer printed board can be reduced by the deformation of the pin, a highly convenient package structure having not only high reliability but also repairability can be obtained.

〔The invention's effect〕

ADVANTAGE OF THE INVENTION According to this invention, although it is a highly reliable structure pair which is the characteristic of a PGA package, high-density mounting like a surface mounting structure is attained.

[Brief description of the drawings]

FIG. 1 is a sectional view of an embodiment of the present invention in which a thin film resistive layer is provided on a carrier substrate, FIG. 2 is a sectional view under a conventional carrier substrate, FIG. 3 (a) is a chip, and FIG. substrate,
(C) Pin mounting board, (d) integrated structure of chip and carrier board, (e) cross-sectional view of pin mounted structure in (d), FIG. 4 is a PGA package cross-sectional view of the present invention, FIG. 5
The figure shows a cross section model (a) showing the method of manufacturing the pin mounting board, and the cross section (b) of the pin mounting board, FIG. 6 shows the PGA cross section of various structures applied, and FIG. 7 shows a printed board with through holes. Sectional view of pin mounting structure when used, Fig. 8 shows high output PGA
FIG. 9 is a cross-sectional view (a) and a plan view when the package is applied to a flexible tape when the package is mounted on a multilayer substrate. DESCRIPTION OF SYMBOLS 1 ... Pin, 2 ... Pin mounting board, 3 ... Through hole, 4 ... Land, 5 ... Package board, 6 ... Conductor, 7 ... Solder, 8 ... Pb-5% Sn solder, 9 ... Si
Chip, 10 Carrier substrate, 11 Thin film, 12 Internal connection terminal, 13 External connection terminal, 14 Ni-Au plating,
15 ... Resin board, 16 ... Resin, 17 ... Copper paste, 18 ...
... Al conductor, 19 ...... SiO ₂ insulating film, 20 ...... Cr-Cu-Au connection terminal, 21 ...... polyimide, 22 ...... resistive film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masahiro Goda 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratory (72) Inventor Tadao Kushima 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi Research, Ltd. In-house (72) Inventor Ichiji Yamada 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratory Co., Ltd. (72) Inventor Tadahiko Miyoshi 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd.Hitachi Laboratory Co., Ltd. Tohru Koyama 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture, Hitachi, Ltd.Hitachi Laboratory, Hitachi, Ltd. (72) Inventor Minoru Yamada 1-280, Higashi Koikekubo, Kokubunji, Tokyo, Japan Inside Hitachi, Ltd. 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. Kanagawa Plant (56) Bibliography JP Akira 63-110758 (JP, A) JP Akira 62-174955 (JP, A) JP Akira 60-138948 (JP, A)

Claims (7)

(57) [Claims] A first substrate having a front terminal and a back terminal electrically connected to each other; a chip connected to the front terminal of the first substrate; and a plurality of pins connected to the back terminal of the first substrate. A package structure comprising: a second substrate having a plurality of through holes, filled with resin in the through holes, and holding the corresponding pins. 2. The package structure according to claim 1, wherein the coefficient of thermal expansion of the resin is substantially equal to the coefficient of thermal expansion of a solder connecting the back terminal and the pin. 3. The package structure according to claim 1, wherein the resin is an epoxy resin or a polyimide resin mixed with 10 to 60% by volume of quartz powder. . 4. A package structure according to claim 1, wherein said resin is an epoxy resin or a polyimide resin containing 5 to 20 parts by weight of rubber particles. . 5. The package according to claim 1, wherein the pins are made of beryllium copper, copper or kovar, and plated with Ni or Ni-Au. Structure. 6. The package structure according to claim 1, wherein one end of the pin, which is not connected to a back terminal, is connected to a non-through through hole of a multilayer substrate. . 7. The package structure according to claim 1, wherein the pins and the back terminals are connected by using solder having a melting point of 220 to 250 ° C.