JPH08316367A - Pin grid array - Google Patents

Abstract

PURPOSE: To obtain a pin grid array for fixing a large number of I/O pins to a printed wiring board(PWB) while increasing the wiring density of PWB. CONSTITUTION: I/O pins 15 are fixed to I/O pads 13 on the lower surface of a PWB 11 and secured by means of a thermosetting resin 17. Since the I/O pin 15 can be fixed firmly to the PWB 11 without penetrating the PWB 11, wiring density of the PWB 11 can be increased and the number of I/O pins 15 can be increased regardless of the wiring density of PWB 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pin grid array, and more particularly to a pin grid array used in electronic information processing equipment.

[0002]

2. Description of the Related Art Conventionally, a pin grid array, especially a plastic pin grid array (hereinafter also referred to as P-PGA) using resin as a material for an insulating substrate is cheaper than a pin grid array using a ceramic substrate or the like. It has been widely used for some reason.

FIG. 6 is a vertical sectional view of an example of a conventional plastic pin grid array. This P-PGA is a printed wiring board (hereinafter referred to as PWB) 41 made of resin.
And the LSI 42 provided by wire bonding W in the cavity C at the center of the upper surface of the PWB 41, and the PWB.
An input / output pin 45 inserted and fixed in the through hole 50 of 41;
The input / output pin 45 is electrically connected to the LSI 42 via a wiring (not shown) on the PWB 41.

The reason why the input / output pin 45 is penetrated through the PWB 41 is that the input / output pin 45 is firmly fixed because the strength of the PWB 41 is lower than that of a ceramic substrate or the like.

As a method of fixing the input / output pin 45 to the PWB 41, the input / output pin 45 is press-fitted and fixed in the through hole 50, or the input / output pin 45 is inserted and then soldered and fixed.

Further, as a pin grid array in which a substrate is reinforced with ceramics, (1) Japanese Unexamined Patent Publication (Kokai) No. 4-142766 discloses a chip carrier having an input / output terminal which does not penetrate the substrate, and (2) Japanese Unexamined Patent Publication (Kokai) No. 62-111456. Japanese Patent Publication discloses a multi-chip package in which input / output terminals are brazed to a substrate.

[0007]

However, the conventional PWB
Since the pin grid array using is provided with through holes corresponding to the number of input / output pins, when wiring is performed on the surface layer and the inner layer of the PWB, the through holes limit the wiring area. Therefore, in order to increase the wiring density, the number of input / output pins must be reduced, and on the other hand, if the number of input / output pins cannot be reduced, the number of PWB layers must be increased. However, there is a drawback that an increase in the number of layers of PWB causes an increase in cost.

Further, the prior art (1) relates to a pin grid array using a ceramic substrate having high strength, and this input / output pin mounting method cannot be directly applied to a pin grid array using PWB having low strength. Can not. Further, in the prior art (2), the effect of brazing the input / output terminals is not specifically described, and the effect is not clear. As described above, the prior arts (1) and (2) do not disclose a technique of attaching a large number of input / output pins to a pin grid array using a PWB having low strength and increasing the wiring density of the PWB.

Therefore, an object of the present invention is to provide a pin grid array in which a large number of input / output pins can be attached to the PWB and the wiring density of the PWB can be increased.

[0010]

In order to solve the above-mentioned problems, the present invention provides an insulating substrate, an LSI provided on the insulating substrate, and a tip portion thereof electrically connected to the LSI on one side surface of the insulating substrate. It is characterized in that it includes an input / output pin that is electrically connected and a thermosetting resin that covers an electrical connection portion of the input / output pin.

[0011]

Since the input / output pins are attached to the surface of the insulating substrate, the wiring density of the insulating substrate can be increased, and the number of input / output pins can be increased regardless of the wiring density of the insulating substrate. Further, since the electric connection portion of the input / output pin is covered with the thermosetting resin, the input / output pin can be firmly fixed to the insulating substrate.

[0012]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the following drawings, the same components as those in the conventional example are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 is a vertical sectional view of a first embodiment of a pin grid array according to the present invention. In the first embodiment, a printed wiring board (hereinafter referred to as PWB) 11 made of resin,
The LSI 42 provided by the wire bonding W in the cavity D at the center of the lower surface of the PWB 11 and the LSI 42.
42 is electrically connected to an electrical terminal (not shown) of PWB 11 via a wiring E provided on the surface layer or the inner layer of PWB 11,
An input / output pad 13 provided on the lower surface of B11, an input / output pin 15 whose tip is soldered by the input / output pad 13 and the solder 14, and P for sealing the LSI 42
It comprises a cap 16 fixed to the WB 11 with an adhesive or the like, and a thermosetting resin 17 for firmly fixing the input / output pin 15 to the PWB 11.

The surface of the input / output pad 13 and the soldering portion of the input / output pin 15 are plated with a material having a good solder wetting property, such as Au or Cu. When Sn / Pb (63/37 wt%) eutectic solder or the like is used as the solder 14, the soldering of the input / output pad 13 and the input / output pin 15 can be performed by 210 ° C. heating reflow or the like.

A thermosetting epoxy resin is preferable as the thermosetting resin 17. After the soldering of the input / output pad 13 and the input / output pin 15 is completed, the thermosetting resin 17 is applied to the soldering portion. Heat to cure. By setting the heating temperature at this time to a temperature lower than the melting temperature of the solder 14, it is possible to prevent the solder 14 from being melted and the input / output pin 15 from being displaced or falling.

The plastic pin grid array (hereinafter referred to as P-PGA) completed in this way is used as another PWB.
When the solder 14 is mounted on a mother board, the solder 14 is covered with the thermosetting resin 17 and is fixed, so that there is no problem even if the solder 14 is melted, and the same solder material can be used for mounting.

If it is not necessary to seal the LSI 42, the cap 16 need not be attached.

Next, the P-PGA of the second embodiment will be described. FIG. 2 shows a second pin grid array according to the present invention.
FIG. 3 is a vertical cross-sectional view of the embodiment, and FIG. 3 is a vertical cross-sectional view of the pinned substrate of the second embodiment. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The P-PGA of the second embodiment differs from that of the first embodiment in that a reinforcing substrate 28 is attached to the input / output pin 15.

As shown in FIG. 3, the substrate 29 with pins is
The PWB 11 includes a reinforcing substrate 28 having a through hole 30 at a position corresponding to the input / output pad 13, and an input / output pin 15 press-fitted and fixed in the through hole 30.

Then, the upper ends of the input / output pins 15 of the board 29 with pins are aligned so as to overlap the input / output pads 13 of the PWB 11 as shown in FIG.
To connect electrically. As a method of soldering, cream solder is placed on the input / output pad 13 in advance, the input / output pins 15 are superposed on the cream solder, and heat reflow is performed in this state, for example, Sn / Pb (63/3 as the solder 14).
(7 wt%) When eutectic solder or the like is used, the I / O pad 13 and the I / O pin 15 are electrically connected by performing 210 ° C. heating reflow or the like. Further, the soldering portion of the input / output pin 15 is also plated with a material having a good solder wetting property like the surface of the input / output pad 13, for example, Au, Cu or the like.

After the soldering is completed, the thermosetting resin 17 is poured into the soldering portion in the gap between the PWB 11 and the reinforcing substrate 28 and is cured by heating or the like. Thermosetting resin 1
As in the first embodiment, 7 is preferably a thermosetting epoxy resin, and by setting the heating temperature at this time to a temperature lower than the melting temperature of the solder 14, the solder 14 does not melt and input / output It is possible to prevent the pin 15 from being displaced.

The P-PGA thus completed is replaced with another PW.
When mounted on a mother board such as B, since the solder 14 is covered and fixed by the thermosetting resin 17, there is no problem even if it melts, and mounting using the same kind of solder material is possible.

By attaching the reinforcing substrate 28 to the PWB 11 as described above, the PWB 11 and the input / output pin 1
5 can be reinforced.

Next, the P-PGA of the third embodiment will be described. FIG. 4 shows a third pin grid array according to the present invention.
It is a longitudinal cross-sectional view of an example. The same components as those in the first and second embodiments are designated by the same reference numerals and the description thereof will be omitted.

The P-PGA of the third embodiment is different from that of the first embodiment in that a heat sink is attached to the LSI 42.

As shown in FIG. 4, the P-PG according to the third embodiment.
A is a PWB 35 in which a through hole 36 having a smaller diameter than the LSI 42 is provided in the LSI 42 mounting portion of the PWB 11 of the first embodiment.
And a heat sink 37 provided in contact with the LSI 42 in the through hole 36. As the material of this heat sink 37, A
It is preferable to use a 1, Fe / Ni (42/58) alloy or the like. By providing this heat dissipation plate 37, the LSI 42
The heat dissipation ability of can be improved.

Next, the P-PGA of the fourth embodiment will be described. FIG. 5 shows a fourth pin grid array according to the present invention.
It is a longitudinal cross-sectional view of an example. The same components as those in the first to third embodiments are designated by the same reference numerals and the description thereof will be omitted.

The P-PGA of the fourth embodiment differs from that of the first embodiment in that the LSI 42 is sealed with a resin 38 instead of the cap 16. Further, it is preferable to use the same resin as the thermosetting resin 17 as the resin 38.

The reinforcing substrate 28 of the second embodiment can be used for the P-PGA of the third or fourth embodiment. Further, although the resin substrate is used as the insulating substrate in the P-PGAs of the first to fourth embodiments, the present invention is not limited to this, and it is also possible to use, for example, a ceramic substrate or the like.

[0031]

According to the present invention, since the input / output pins electrically connected to the LSI are provided on one surface of the insulating substrate and the input / output pins are fixed by the thermosetting resin, the wiring density of the insulating substrate is reduced. The number of input / output pins can be increased regardless of the wiring density of the insulating substrate, and the input / output pins can be firmly fixed to the insulating substrate.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of a first embodiment of a pin grid array according to the present invention.

FIG. 2 is a vertical sectional view of a second embodiment of the pin grid array.

FIG. 3 is a vertical sectional view of a pinned substrate of the second embodiment of the pin grid array.

FIG. 4 is a vertical sectional view of a third embodiment of the pin grid array.

FIG. 5 is a vertical sectional view of a fourth embodiment of the pin grid array.

FIG. 6 is a vertical cross-sectional view of an example of a conventional plastic pin grid array.

[Explanation of symbols]

 11 Printed Wiring Board 14 Solder 15 Input / Output Pin 16 Cap 17 Thermosetting Resin 17 28 Reinforcing Board 30, 36 Through Hole 37 Heat Sink 38 Sealing Resin 42 LSI

Claims (6)

[Claims] 1. An insulating substrate, an LSI provided on the insulating substrate, an input / output pin whose tip portion is electrically connected to the LSI on one surface of the insulating substrate, and an electrical circuit for the input / output pin. Pin grid array including a thermosetting resin that covers the static connection portion. 2. The pin grid array according to claim 1, wherein a temperature at which the thermosetting resin is hardened is lower than a melting temperature of solder which electrically connects the LSI and the input / output pins. 3. A reinforcing board having a through hole at a position corresponding to the input / output pin, wherein the input / output pin is inserted into the through hole of the reinforcing board to fix the reinforcing board to the insulating board side. The pin grid array according to claim 1 or 2, wherein 4. The heat dissipation plate, wherein the LSI is provided on a side of the insulating substrate where the input / output pins are attached, a through hole having a diameter smaller than that of the LSI is provided at the LSI attaching portion of the insulating substrate, and the through hole is in contact with the LSI. The pin grid array according to claim 1, wherein the pin grid array is provided. 5. The pin grid array according to claim 1, wherein the LSI is sealed with resin. 6. The pin grid array according to claim 1, wherein the LSI is sealed with a lid material.