KR100339491B1 - Method for fabricating chip size package - Google Patents

Method for fabricating chip size package Download PDF

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Publication number
KR100339491B1
KR100339491B1 KR1019950069095A KR19950069095A KR100339491B1 KR 100339491 B1 KR100339491 B1 KR 100339491B1 KR 1019950069095 A KR1019950069095 A KR 1019950069095A KR 19950069095 A KR19950069095 A KR 19950069095A KR 100339491 B1 KR100339491 B1 KR 100339491B1
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South Korea
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pcb
hole
chip
semiconductor chip
semiconductor
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KR1019950069095A
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Korean (ko)
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KR970053780A (en
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하선호
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1019950069095A priority Critical patent/KR100339491B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A method for fabricating a chip size package(CSP) is provided to improve capability and miniaturize a semiconductor package by molding the semiconductor package in such a way to directly attach a signal withdrawal terminal to a chip pad formed on a semiconductor chip. CONSTITUTION: A printed circuit board(PCB) is penetrated to form a through hole(7) and an air vent(8). The through hole is plated and a plurality of interconnection patterns(5) are formed on and under the PCB. The gap between the interconnection patterns on the PCB where the through hole and the air vent are not formed is covered with solder resist or polyimide(9). An aluminum pad(2) on the semiconductor chip(1) and the interconnection pattern on the PCB are attached to each other by using a gold bump(4). The gap between the PCB and the semiconductor chip is filled with a coating material(4), resin. Solder balls(10) are formed in the interconnection patterns formed under the PCB.

Description

칩 사이즈 패키지의 제조 방법Manufacturing method of chip size package

본 발명은 칩 사이즈 패키지의 제조 방법에 관한 것으로, 더욱 상세하게는 반도체 패키지의 크기를 반도체칩의 크기와 비슷한 크기로 형성하여 경박단소화한 반도체 패키지를 제조함으로써, 작은 반도체패키지의 크기로 고집적화 및 고성능화 할 수 있도록 하는 반도체패키지의 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a chip size package, and more particularly, to manufacture a semiconductor package in which the size of the semiconductor package is formed to a size similar to that of the semiconductor chip, thereby manufacturing a thin and small sized semiconductor package. The present invention relates to a method for manufacturing a semiconductor package that enables high performance.

최근에 전자제품, 통신기기, 컴퓨터 등 모든 반도체 관련 제품들은 소형화되어 가고 있는 바, 이와 같이 전자제품들이 소형화되기 위해서는 먼저 반도체 패키지의 크기를 작게 형성하면서 그 성능은 고기능화되어야 한다.Recently, all semiconductor-related products such as electronic products, communication devices, computers, etc. have been miniaturized. Thus, in order to miniaturize electronic products, first, the size of the semiconductor package must be made small, and the performance thereof must be highly functionalized.

그러나, 이와 같이 반도체 패키지의 크기를 작게 형성하기에는 종래의 반도체 패키지 제조 방법과 구조로는 한계가 있기에 새로운 형태의 반도체 패키지 제조방법과 장치를 요구하게 되었다.However, in order to form a small semiconductor package as described above, a conventional semiconductor package manufacturing method and structure have limitations, and thus a new type of semiconductor package manufacturing method and apparatus are required.

이렇게 되어 출현한 새로운 형태의 반도체 패키지를 칩 사이즈 패키지(CSP; Chip Size Package)라 하는데, 이는 반도체 패키지의 크기를 반도체칩의 크기와 비슷한 크기로 반도체 패키지를 형성함은 물론, 그 기능을 다기능화함으로써, 전자제품에 탑재시 그 탑재되는 면적을 최소화하여 제품의 소형화를 이룰 수 있도록 한 것이다.This new type of semiconductor package is called a chip size package (CSP), which not only forms a semiconductor package with a size similar to that of a semiconductor chip, but also multiplies its functions. By doing so, the mounting area of the electronic product is minimized so that the product can be miniaturized.

따라서, 본 발명의 목적은 반도체 패키지를 칩 사이즈 패키지의 구조를 갖는 것으로, 반도체칩에 형성된 칩패드에 직접 신호인출단자를 부착시킬 수 있는 구조로 반도체 패키지를 성형하므로서 그 성능을 향상시키고, 반도체 패키지를 경박단소화함은 물론 고기능을 갖는 반도체 패키지 구조와 그 제조 방법을 제공함에 있다.Therefore, an object of the present invention is to have a structure of a semiconductor package chip size package, to improve the performance of the semiconductor package by molding the semiconductor package in a structure capable of attaching the signal extraction terminal directly to the chip pad formed on the semiconductor chip, To provide a semiconductor package structure and a method of manufacturing the same, as well as reducing the size and light weight.

본 발명의 칩 사이즈 패키지는 반도체칩상의 알루미늄 패드와 배선페턴 사이에는 골드 범프로서 접합되며, 상기 배선패턴이 부착된 PCB와 상기 반도체칩 사이에는 코팅물질인 수지가 충진되고, 상기 PCB에 간격을 두고 세로 방향으로 구멍을 뚫어 스루홀과 에어 벤트를 형성하고 PCB 하단부 배선 패턴위에 솔더볼이 얹히며, 상기 에어벤트 부분이 아닌 PCB 위의 배선패턴 사이에는 솔더레지스트 또는 폴리이미드로 덮히는 구조를 특징으로 한다.The chip size package of the present invention is bonded as a gold bump between the aluminum pad and the wiring pattern on the semiconductor chip, and the resin, which is a coating material, is filled between the PCB with the wiring pattern and the semiconductor chip, and is spaced apart from the PCB. It forms a through hole and an air vent by drilling a hole in a vertical direction, and a solder ball is placed on a wiring pattern at the bottom of the PCB, and the structure is covered with solder resist or polyimide between the wiring patterns on the PCB instead of the air vent. .

또한, 본 발명에 의한 칩 사이즈 패키지 제조 방법은 PCB에 상하부가 관통되는 구멍을 형성하여 스루홀과 에어벤트를 형성하고 도금하는 단계와, 상기 스루홀과 에어벤트 부분이 아닌 PCB 위의 배선패턴 사이에는 솔더레지스트 또는 폴리이미드를 덮는 단계와, 준비된 반도체칩 상의 알루미늄 패드와 PCB 위의 배선패턴 사이를 골드 범프로서 접합시키는 단계와, 상기 PCB와 상기 반도제칩 사이를 코팅물질인 수지로 충진시키는 단계와, 상기 PCB의 하면에 형성된 배선패턴에 솔더볼을 형성하는 단계로 이루어진 것을 특징으로 한다.In addition, the method for manufacturing a chip size package according to the present invention comprises the steps of forming a through-hole and a through-hole through the PCB to form and plate the through-hole and the air vent, and between the wiring pattern on the PCB rather than the through-hole and the air vent portion Covering the solder resist or polyimide, bonding the aluminum pad on the prepared semiconductor chip and the wiring pattern on the PCB as a gold bump, and filling the resin between the PCB and the semiconductor chip with a resin as a coating material; And forming a solder ball on the wiring pattern formed on the bottom surface of the PCB.

본 발명의 칩 사이즈 패키지를 도면 제1도를 참조하여 상세히 설명하면 다음과 같다. 알루미늄 패드(2)가 부착된 반도체칩(1)이 PCB(6) 위의 배선패턴(5)과 골드 범프(3)로 접합되며, 상기 반도체칩(1)과 PCB(6) 사이의 공간은 코팅 물질인 수지(4)로 채워지고, 상기 PCB(6)에는 다수의 스루홀과 에어벤트가 형성되고, 상기 배선패턴(5)의 상면이 폴리이미드로 덮혀지며, 배선패턴이 형성된 상기 PCB(6)의 하면부는 솔더레지스트가 덮히고 그위에 솔더볼이 안착된다.The chip size package of the present invention will be described in detail with reference to FIG. 1 as follows. The semiconductor chip 1 having the aluminum pad 2 attached thereto is bonded to the wiring pattern 5 and the gold bump 3 on the PCB 6, and the space between the semiconductor chip 1 and the PCB 6 is The PCB 6 is filled with a resin 4, which is a coating material, and a plurality of through holes and air vents are formed in the PCB 6, and an upper surface of the wiring pattern 5 is covered with polyimide, and the wiring pattern is formed on the PCB ( The lower part of 6) is covered with solder resist and solder balls are seated on it.

본 발명의 칩 사이즈 패키지의 제조 단계를 제2도를 참고하여 설명하면 다음과 같다.The manufacturing steps of the chip size package of the present invention will be described with reference to FIG.

제2(A)도는 반도체칩(1) 상의 알루미늄 패드(2)위에 와이어 본딩 방식을 이용하여 골드 또는 솔더 범프(3)를 형성한다.FIG. 2 (A) shows gold or solder bumps 3 on the aluminum pads 2 on the semiconductor chip 1 using a wire bonding method.

이와 같이 제조된 반도체칩(1)과 연결되는 PCB(6) 제조 공정은 다음과 같다.The manufacturing process of the PCB 6 connected to the semiconductor chip 1 manufactured as described above is as follows.

제2(B)도는 PCB 골격으로 사용되는 PCB(6) 구조를 나타낸다. 즉, 상기PCB(6)는 양면이 동박으로 입혀있다.2 (B) shows the structure of the PCB 6 used as the PCB skeleton. That is, both sides of the PCB 6 are coated with copper foil.

제2(C)도에 도시된 바와 같이, 동박이 입혀진 상기 PCB(5)에 스루홀(7)과 에어벤트(8)를 뚫는다.As shown in FIG. 2 (C), through-holes 7 and air vents 8 are drilled through the PCB 5 coated with copper foil.

이후, 제2(D)도에서 도금공정을 거친 후, 포토 에칭 공정을 사용하여 다수의 배선패턴(5)을 형성한다.Subsequently, after the plating process is performed in FIG. 2D, a plurality of wiring patterns 5 are formed by using a photo etching process.

이어서, 제2(E)도에 도시된 바와 같이 폴리이미드 공정을 거쳐 PCB(6) 상부에 폴리이미드(9)를 쒸우고, 상기 PCB(6) 하부는 솔더래지스트 공정을 통해 솔더레지스트를 씌우는 데, 이때 솔더볼(10)이 안착되는 배선패턴 영역만을 개방시켜 니켈, 금 도금 또는 솔더링을 한다. 이와 같이 완성된 PCB를 제2(A)도의 반도체칩(1)과 본딩을 한 후 수지(4)로 코팅을 한다.Subsequently, as shown in FIG. 2E, the polyimide 9 is deposited on the upper part of the PCB 6 through the polyimide process, and the lower part of the PCB 6 is covered with solder resist through the solder resist process. In this case, only the wiring pattern area on which the solder ball 10 is seated is opened to perform nickel, gold plating or soldering. The PCB thus completed is bonded with the semiconductor chip 1 of FIG. 2A and then coated with the resin 4.

제1도는 솔더볼(10)을 부착하여 완료된 칩 사이즈 패키지의 구조를 나타낸 것으로, 이러한 본 발명의 칩 사이즈 패키지는 골드범프(3)를 이용하여 본딩을 하였기에 내구성과 안전성이 높아졌으며, 특히 PCB에 에어벤트를 뚫어 놓음으로서 코팅시 불완전한 채움을 방지할 수 있으며, PCB를 사용함으로써 솔더볼(10) 위치를 자유로이 디자인하여 종래 칩 사이즈 패키지가 갖는 단점을 보완하는 효과가 있다.1 shows the structure of the chip size package completed by attaching the solder ball 10. The chip size package of the present invention is bonded by using the gold bumps 3 to increase durability and safety. By penetrating the vent, it is possible to prevent incomplete filling during coating. By using the PCB, the solder ball 10 can be freely designed to compensate for the disadvantages of the conventional chip size package.

제1도는 본 발명에 따른 칩 사이즈 패키지의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a chip size package according to the present invention.

제2도는 본 발명에 따른 칩 사이즈 패키지의 제조 단계를 도시한 도면2 shows manufacturing steps of a chip size package according to the present invention.

* 도면의 주요부분에 대한 부호의 설명** Explanation of symbols for the main parts of the drawings *

1; 반도체칩 2; 알루미늄 패드One; Semiconductor chip 2; Aluminum pad

3; 범프 4; 코팅물질3; Bump 4; Coating material

5; 배선패턴 7; 스루 홀5; Wiring pattern 7; Through hole

8; 에어벤트(air Vent) 9; 폴리이미드8; Air vent 9; Polyimide

10; 솔더 볼10; Solder ball

Claims (1)

PCB에 상하부가 관통되는 구멍을 형성하여 스루홀과 에어벤트를 형성하고, 상기 스루홀은 도금하며, 상기 PCB의 상,하면에 다수의 배선패턴을 형성하는 단계와;Forming a through hole and an air vent through the upper and lower portions of the PCB, plating the through hole, and forming a plurality of wiring patterns on the upper and lower surfaces of the PCB; 상기 스루홀과 에어벤트 부분이 아닌 PCB 위의 배선패턴 사이에는 솔더레지스트 또는 폴리이미드를 덮는 단계와;Covering a solder resist or polyimide between the through hole and the wiring pattern on the PCB other than the air vent; 반도체칩 상의 알루미늄 패드와 PCB 위의 배선패턴 사이를 골드 범프로 접합시키는 단계와;Bonding a gold bump between the aluminum pad on the semiconductor chip and the wiring pattern on the PCB; 상기 PCB와 상기 반도체칩 사이를 코팅물질인 수지로 충진시키는 단계와;Filling the PCB and the semiconductor chip with a resin that is a coating material; 상기 PCB의 하면에 형성된 배선패턴에 솔더볼을 형성하는 단계로 이루어진 것을 특징으로 하는 칩 사이즈 패키지 제조 방법.Chip size package manufacturing method comprising the step of forming a solder ball on the wiring pattern formed on the lower surface of the PCB.
KR1019950069095A 1995-12-30 1995-12-30 Method for fabricating chip size package KR100339491B1 (en)

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* Cited by examiner, † Cited by third party
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KR100447226B1 (en) * 2001-10-24 2004-09-04 앰코 테크놀로지 코리아 주식회사 Semiconductor Package contained chip

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022151A (en) * 1988-06-15 1990-01-08 Hitachi Ltd Package structure
JPH0269945A (en) * 1988-09-05 1990-03-08 Hitachi Ltd Semiconductor device and manufacture thereof
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
KR940012550A (en) * 1992-11-03 1994-06-23 빈센트 비. 인그라시아 Thermally Reinforced Semiconductor Devices Having Exposed Backsides and Methods of Manufacturing the Same
JPH06326211A (en) * 1993-05-17 1994-11-25 Hitachi Ltd Semiconductor package and circuit board and electronic equipment using-same
JPH07245360A (en) * 1994-03-02 1995-09-19 Toshiba Corp Semiconductor package and its manufacture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH022151A (en) * 1988-06-15 1990-01-08 Hitachi Ltd Package structure
JPH0269945A (en) * 1988-09-05 1990-03-08 Hitachi Ltd Semiconductor device and manufacture thereof
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
KR940012550A (en) * 1992-11-03 1994-06-23 빈센트 비. 인그라시아 Thermally Reinforced Semiconductor Devices Having Exposed Backsides and Methods of Manufacturing the Same
JPH06326211A (en) * 1993-05-17 1994-11-25 Hitachi Ltd Semiconductor package and circuit board and electronic equipment using-same
JPH07245360A (en) * 1994-03-02 1995-09-19 Toshiba Corp Semiconductor package and its manufacture

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