JP2858760B2 - Organic-inorganic composite multilayer substrate - Google Patents

Abstract

PURPOSE:To improve the manufacturing yield and facilitate a high speed operation and high density size reduction by a method wherein a ceramic board having a low dielectric constant and a low thermal expansion coefficient is soldered to the chip mounting part of an organic multilayer board and the two boards are unified by filling and bonding with specific resin. CONSTITUTION:A ceramic board 1 having a low dielectric constant and a low thermal expansion coefficient is soldered to the chip or chip carrier mounting part of a Teflon system organic multilayer board 2. The boards 1 and 2 are unified by filling and bonding with resin having a thermal expansion coefficient between that of solder and that of the board 2. As the thermal expansion coefficient is low in the chip carrier mounting part, excellent repair-resistance and a high density can be realized and a thin film resistance layer can be formed on the surface. Moreover, by selecting the thermal expansion coefficient of the filling resin between that of the solder and that of the board 2, temperature- cycle resistance can be improved. With this constitution, the manufacturing yield can be improved and the high speed processing can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention is suitable for an LSI mounting module substrate that plays the most important role of a CPU (Central Processing Unit) of an ultra-large, ultra-high-speed computer, and has excellent high-speed performance, a chip, or
The present invention relates to a low dielectric constant organic-inorganic composite multilayer substrate having excellent repairability for mounting a chip carrier and excellent usability.

[Prior art]

In order to increase the capacity and speed of a computer, it is considered ideal to mount it on an organic multilayer substrate by a flip-chip mounting method that is advantageous for increasing the density of terminals. Conventionally, as an example of mounting a flip chip on an organic substrate, a literature (LE
As shown in EE Tr. Comp, and Vol, CHMT-2, No. 1, 1979-3), there is a polyimide substrate (epoxy substrate) containing aramid fiber. The polyimide substrate containing aramid fiber (epoxy substrate) has a coefficient of thermal expansion of 6-8 × 10 ⁻⁶ / ° C., a dielectric constant (ε) of 3.5, and a Teflon-based organic substrate (ε = 2-2.
Compared to 5), high-speed performance (delay time is in proportion to √ε) is inferior, and thermal expansion coefficient is similar to Al ₂ O ₃ substrate. Mounting is impossible (4-5mm □ is the mounting limit). In addition, even if a chip carrier is formed using a low thermal expansion ceramic substrate having a thermal expansion coefficient of 3 to 4 × 10 ⁻⁶ / ° C.
No. 57-19578) Due to the difference in thermal expansion between the organic substrate and the chip carrier, a large chip of 10 mm □ cannot be mounted. Therefore, instead of the organic multilayer substrate, a ceramic multilayer substrate excellent in reliability and usability has been used (for example, Japanese Patent Application Laid-Open No. 57-18350). However, although the ceramic multilayer substrate can be made to have a low thermal expansion, the dielectric constant is inferior to that of the organic multilayer substrate (e.g., ε is 5 with a low dielectric constant material), so that it is inferior in high-speed operation. Therefore, the resin structure was studied in consideration of highly reliable mounting of a large chip on a low dielectric constant substrate. Until now U.S. Patent 4,190,855
(1976-8) As shown in FIG. 2 (a), a structure has been proposed in which a Si chip 10 is mounted on a glass substrate or the like 14 and a resin is inserted between the chip and the substrate. This kind of integrated structure is
In each case, the element is directly mounted on the substrate, and repair of the chip is not considered. In addition, a structure in which a chip carrier is soldered in consideration of chip repair has been proposed.

[Problems to be solved by the invention]

An object of the present invention is to mount a large chip (10 mm square) on a low dielectric constant organic multilayer substrate with high reliability by a flip chip method. The functions required for an LSI-mounted module substrate for large-capacity, high-speed calculations are as follows, and an organic multilayer substrate cannot meet the required specifications. 1) Thermal expansion coefficient of 3 to 4 × 10 ^-6 / ° C or less 2) Repair resistance (heat resistance to metallization) 3) High-density multi-terminal pitch (250 μm pitch) 4) Formation of thin-film resistance layer for impedance matching

[Means for Solving the Problems]

To achieve the above object, solder a low dielectric constant, low expansion ceramic substrate to the chip or chip carrier mounting area on the organic multilayer substrate, fill and bond with a specific resin, and integrate with the organic multilayer substrate 1) to 4)
Requirements can be satisfied. As a result, the coefficient of thermal expansion in the chip or chip carrier mounting area on the organic-inorganic composite multilayer substrate is 3 to 4 × 10 ⁻⁶ / ° C. or less,
It has excellent repair resistance and enables high-density pitch of 250 μm and formation of a thin-film resistance layer on the surface. Organic multilayer substrate (8 × 10
^-6 / ℃) on a low expansion ceramic substrate (3.5 × 10 ^-6 /
℃) composite substrate has a thermal expansion coefficient of 15 × 10 ^-6
/ ° C greatly improved the temperature cycle resistance.

[Action]

The reason why the temperature cycle resistance was greatly improved is as follows. 1) A sea-island structure in which the ceramic substrate to be mounted is separated and independent, to reduce the stress generated between the resin and the ceramic substrate and the warpage of the organic multilayer substrate. 2) By setting the thermal expansion coefficient of the filled resin at about 15 × 10 ^-6 / ° C, which is between that of the solder and the organic multilayer substrate, stress concentration on the solder on the ceramic substrate side is reduced, and distortion is minimized. That made it possible. 3) The development of heat-resistant resin (Tg: 180 ° C) minimizes the decrease in adhesive strength at high temperatures. 4) Development of a resin with little deterioration at high temperature. 5) Realization of a nearly complete filling structure using a solventless resin with excellent fluidity. 6) Strong metallization on the side where stress is applied. The reason for enabling high-speed calculation is as follows. 1) The chip can be directly mounted on an organic multilayer substrate having a low dielectric constant. 2) The wiring length from the chip to the multilayer substrate must be short. 3) By integrating the ceramic substrate,
A structure that can incorporate capacitors etc. The reasons for the usability are as follows. 1) Repair-resistant structure (ceramic substrate is used for bonding part) 2) Flip chip mounting method on ceramic substrate has been proven. 3) Coexistence with resin is possible by selecting a soldering agent with a temperature hierarchy (using a plurality of solders with different melting points).

【Example】

Large-sized computers are aiming for large capacity and high speed. For this reason, as a mounting system for mounting a CPU, 1) lowering the dielectric constant of a multilayer substrate material and 2) high-density mounting in which the wiring length is shortened are particularly required. Therefore, the present invention has proposed a mounting method with a highly reliable structure using a material that is close to ideal. FIG. 1 shows a sectional view of the present invention. Ideally, a multilayer substrate that is optimal as a low dielectric constant material is composed of air having a dielectric constant of 1, but has a problem in reliability (mechanical and electrical). The (fluorine-based) organic multilayer substrate 2 is ideal. The Teflon material itself has a high coefficient of thermal expansion and has problems in adhesion to the material and the like. In order to mount a chip, it is necessary to reduce the thermal expansion coefficient in the lateral direction (x, y) as much as possible in order to reduce the expansion and improve the strength of the multilayer substrate. When made by normal process, low dielectric constant, low expansion coefficient quartz fiber (or organic aramid fiber) is put,
Even a copper-containing multilayer board has a thermal expansion coefficient of 8 to 10 × 10 ⁻⁶ / ° C., which is far from the level at which a 10 mm square chip can be mounted with high reliability. In the organic multilayer substrate 2, there is a demand for thinning the insulating layer and the increase in the number of copper wiring layers due to the increase in the number of layers, so that even if the number of low expansion fibers is increased, there is a limit to the low thermal expansion, and the low thermal expansion is not achieved unlike the ceramic substrate. . The surface layer in which adhesion is regarded as important can be solved by replacing the surface layer with a material system having an inclined adhesion. In addition, although the dielectric constant is inferior to that of Teflon, isomeramine (dielectric constant of 3 to 3.
5) Multilayer substrates are superior to Teflon in terms of adhesion, heat resistance, and ease of use. The organic multilayer substrate system 2 which is formed by a batch lamination system as the number of layers increases is more suitable. The through holes of the organic multilayer substrate 2 are generally formed by a drill. Due to the demand for large capacity and high speed, multilayer boards have become increasingly multilayered and thick,
And the pitch is seeking the limit. In the case of providing two wiring layers between pitches in a multi-layer board of 7 mm, technically, a 0.45 mm pitch and a 0.3 mm hole are technically limited. On the other hand, the element for CPU is a flip-chip surface mounting of a Si chip, and a pitch of 0.25 to 0.30 mm is sufficiently possible. 0.25
In order to mount a Si chip having a pitch of 0.30 mm on an organic multilayer substrate, it is common to provide a matching layer using polyimide-based photoresist on the surface of the organic multilayer substrate. If a photoresist is used, terminals with a fine pattern of 0.25 to 0.30 mm can be formed. However, this method has a problem in heat resistance of the organic multilayer substrate in polyimide etching or the like. Therefore, as shown in the figure, the present invention mounts a chip or a low-permittivity ceramic substrate larger than the chip carrier on the terminal of the chip or chip carrier mounting area on the organic multilayer substrate, and A structure was devised in which the terminals were joined by soldering or thermocompression bonding. A matching layer having a pitch of 0.45 mm on the organic multilayer substrate side of the ceramic substrate and a pitch of 0.25 mm on the chip or chip carrier mounting side of the ceramic substrate was provided in the ceramic substrate. This is a possible level for mass production technology. The method of joining a chip or a chip carrier on the organic multilayer substrate 2 is the same as the method of flip-chip joining a chip to a ceramic substrate. The material of the ceramic substrate is a glass-ceramic 1 system with the lowest dielectric constant, which has a coefficient of thermal expansion of 3.5 × 10.
^The reliability test target can be satisfied even when a 10 mm square Si chip is mounted barely at ^-6 / ° C. The dimensions of the ceramic substrate were set to 15 mm square, which allows repair wiring around the substrate and wiring to adjacent ceramic substrates.
The thickness of the ceramic substrate is as follows: 1) The organic multilayer substrate must have a bending stiffness and an extension stiffness that do not affect the coefficient of thermal expansion of 8 to 10 × 10 ⁻⁶ / ° C. 2) The thickness is set to 0.6 to 0.8 mm in consideration of shortening the wiring length. Even if a ceramics substrate is simply joined to the organic multilayer substrate 2 by soldering in an island shape, low reliability can be easily predicted from the data so far. For example, the life of a 15 mm square glass ceramic (coefficient of thermal expansion: 3.5 × 10 ⁻⁶ / ° C.) flip-chip bonded to an organic multipurpose substrate 2 (coefficient of thermal expansion: 8 to 10 × 10 ⁻⁶ / ° C.) is −55 to 150 At 200 ° C, 1 cycle / h is 200 cycle level, far from the target 1000 cycle. Therefore, for a lifetime increase, it has a low thermal expansion coefficient of solder, and, by the Young's modulus is filled with a resin of 1700Kgf / mm ² between the two substrates, and stress concentration involved in the solder, and the solder By alleviating the stress concentration and reducing the strain applied to the solder, an organic-inorganic composite multilayer substrate having a low dielectric constant of 1500 cycles or more has been made possible. The effect of mounting a Si chip on an alumina substrate or a glass substrate and filling it with a resin to reinforce it is disclosed in JP-A-60-63951. According to this publication, it is pointed out that the resin suitable for the structure is to insert a quartz filler, adjust the coefficient of thermal expansion to that of the solder, and to insert rubber particles. The present invention is not a Si chip but a glass ceramic substrate provided with terminals on the back surface, and is an organic multilayer substrate having a low Young's modulus instead of an alumina substrate and a glass substrate. According to the analysis by the finite element method, the Young's modulus of the organic multilayer substrate is low, and unlike the Si chip mounted substrate, stress concentration is particularly high on the glass ceramic substrate side with a high Young's modulus and low thermal expansion coefficient. Do you get it. Therefore, it has been found that it is important to make the thermal expansion coefficient of the resin smaller than that of the solder and larger than that of the organic multilayer substrate to improve the life. It has been found that the mechanism for reducing the strain applied to the solder is complicated, and is determined by a combination of four types of material properties (thermal expansion coefficient, Young's modulus) of the glass ceramic substrate 1, the solder, the resin, and the organic multilayer substrate 2. It is a point of ensuring high reliability that the stress concentration of the solder near the interface between the glass ceramic substrate and the solder is reduced in this system. As a solution to this, 1) the thermal expansion coefficient of the resin is set to 15 × 10 ^-6
/ ° C (between solder and organic multilayer substrate). 2) It was found that the use of solder having a low coefficient of thermal expansion was effective. The metallization of the glass ceramic substrate is a thick film process that is baked at a high temperature. Therefore, unlike the thin film metallization of the Si chip, the metallization is strong. Therefore, it is not necessary to consider the influence of stress on the metallization. Therefore, it is important to consider the thermal fatigue of the solder near the interface between the glass ceramic substrate and the solder. Next, the necessary conditions of various constituent material properties obtained from the finite element method analysis and the experiment were obtained. The thermal expansion coefficient of the low dielectric constant organic multilayer substrate is αp, the thermal expansion coefficient of the ceramic substrate on the organic multilayer substrate is αc ₁ , the thermal expansion coefficient of the resin is αr ₂ , the Young's modulus of the resin is Er, chip, or chip carrier. when the thermal expansion coefficient .alpha.c _2, and can be cleared by αc ₁ = αc ₂ ...... (approximately material having a same thermal expansion coefficient) αp-αc2 <of 7 × 10 ^-6 / ℃ ...... (resin working 5 × 10 ^-6 / ℃ <αr <30 × 10 ^-6 / ℃ …… (The range of the thermal expansion coefficient of the resin can be covered by Young's modulus. Although it is difficult, it is possible to reduce the expansion difference with a polyimide resin, but providing a difference in the thermal expansion between the solder and the resin is a problem because a large strain is generated at the interface.) The appropriate region of the product of the expansion coefficient and the Young's modulus was investigated. Young's modulus of the resin is in the range of 200~2000Kgf / mm ^2. [Young's modulus / coefficient of thermal expansion] 1) 200 (small) ・ 30 × 10 ^-6 (large) = 0.006 ... Influence of resin: small Judgment: × 2) 200 (small) ・ 5 × 10 ^-6 (small) = 0.001 ...... Influence of resin: small Judgment: × 3) 800 (medium) · 25 × 10 ^-6 (medium) = 0.02 judgment: ○ 4) 2000 (large) · 5 × 10 ^-6 (small) = 0.01 Judgment: ○ 5) 1700 (large) ・ 15 × 10 ⁻⁶ (medium) = 0.025 Judgment: ○ An equation was obtained from the above results. 0.007 <αr · Er <0.03... FIG. 3 shows an organic-inorganic composite low dielectric constant multilayer substrate of the present invention. (A) is a structure having a large bump height using a soft solder of Sn-5% Sb5 as a solder material. (B)
Is a structure having a low bump height joined by a thermocompression bonding method using a hurdle solder of Au-20% Sn32. (C) shows a structure in which a depression is provided in the organic multilayer substrate 2 and the ceramic substrate 1 is buried and flattened. On the low dielectric constant Teflon-based multilayer substrate 2 (hereinafter, referred to as a printed circuit board) shown in FIG. 1A, double terminals 3 connected to through holes are arranged in a grid pattern. The through hole pitch is 0.45 mm and the hole diameter is 0.3 mm. The ceramic substrate is a glass ceramic having a low dielectric constant (approximately ε = 5), and the pitch is internally adjusted in multiple layers. The terminal pitch on the ceramic substrate chip or chip carrier mounting side is 0.25 mm. The terminal pitch on the printed circuit board side is 0.45 mm. The size of the glass ceramic substrate is 15mm □ × 0.8t, and all terminals are lattice-shaped.
The chip mounting area is provided in the center. The glass ceramic conductor may be thick copper paste 4 and the solder connection may be plated with Ni-Au to prevent solder erosion. In addition, a mullite substrate (Al ₂ O ₃ .SiO ₂ ) having a low expansion and a low dielectric constant can be used as the ceramic substrate. The mullite wiring layer is a W conductor, and the solder connection terminals are plated with Ni-Au on W. As for the solder material, the temperature hierarchy with the chip or chip carrier was considered. In other words, as a solder having a melting point that does not melt the solder used to connect the ceramic substrate and chip or chip carrier,
Sa-based Sn-5% Sb (232 ° C.) 5 was used. Other Sn-based Sn-3.5% Ag (221 ℃), low expansion pure Sn
(232 ° C) is also possible. The solder was supplied using a ball having a diameter of about 0.3φ, and was first joined to the ceramic substrate side. The gap at the connection between the ceramic substrate and the printed board is about 150 μm. Soldering was performed in a furnace using a rosin-based flux. After washing and drying sufficiently, the resin 7 is supplied to the side of the ceramic substrate with a dispenser,
Two methods are possible: a method of flowing by the action of surface tension and gravity, and a method of combining suction and pressure in a vacuum. Both methods enable voiding. As a precautionary measure, it was confirmed that minute voids diffused and disappeared when pressure was applied. As the resin structure, the structure on the left side of (a) is a case where the resin is not wet on the side surface of the ceramic substrate.
The structure on the right side of the figure shows a case where the resin is wet on the side surface of the ceramic substrate. As a result of the stress analysis, it is desirable that the solder applied to the ceramic substrate near the center of the side surface be a highly reliable structure in which the stress applied to the solder is small, but the structure shown in FIG. . In the case of the structure (b), the terminal of the printed circuit board is Sn
(1 part Au) is supplied, and Au or Au-Su is supplied in advance to the terminal on the ceramics side, and it is possible to bond by heating and pressing. Since the gap between the ceramics and the printed board is small, it is necessary to reduce the filler particle size with a resin having good fluidity. When the resin does not adversely affect the bonding, it is also possible to apply the resin uniformly to the terminals in advance, and then perform thermocompression bonding (fluxless) from above. (C) Since the structure has a problem in cleaning with flux,
It is desirable that the bonding be performed in a hydrogen atmosphere. Originally, in the case of a bare chip, a wire breaks in a rapid cycle in a temperature cycle test. Until now, Al ₂ O ₃ substrates, glass substrates, etc.
The appropriate value for the physical properties of the resin mounted chip has been set to 25 × 10 ^-6 / ° C, which is almost the same as that of solder.
The combination here is a glass ceramic substrate on an organic multilayer substrate. For this reason, a different way of thinking was required. First, it is necessary to improve the heat resistance of the resin, so that the epoxy resin is an acid anhydride alicyclic epoxy to increase the Tg (glass transition temperature). It must be silicone rubber. As a result, deterioration of the resin at high temperatures was reduced. In FIG. 10, the horizontal axis represents the coefficient of thermal expansion of the resin, and the vertical axis represents the maximum flexural strain applied to the outermost solder bump (point A). The Young's modulus of the resin 800 kgf / mm ² and 1700
The results are for kgf / mm ² . According to the finite element analysis, the position where the maximum shear strain acting on the solder is taken is point A on the glass ceramic substrate side. As a result, the Young's modulus of the resin is reduced (800 kgf / m
m ² ) and the thermal expansion coefficient of the optimal resin that minimizes shear strain tended to increase, and the minimum value of shear strain also tended to increase. Therefore, as an appropriate value, the region with a high Young's modulus (1700kgf / mm
² ) minimizes the shear strain on the solder 15
× 10 ⁻⁶ / ° C. This appropriate value is solder (25 × 10 ^-6 /
℃) and the printed board (8 × 10 ^-6 / ℃). Therefore, the coefficient of thermal expansion is 15 × 10 ^-6 / ° C and the Young's modulus is 1700Kgf / m
of m ² Tg: 230 ℃ results of testing ten samples using a fluid good resin having a glass transition temperature of -55 to 150
At ℃, 1h / ∞ test, no conduction failure occurred, confirming high reliability. Under the same conditions, the coefficient of thermal expansion is 25 × 10 ⁻⁶ / ° C, Young's modulus is 8
The resin having a temperature of 00 kgf / mm ² and a Tg of 180 ° C. was tested. It can be understood from the fact that even when the values of the maximum shear strain of both are compared (0.8% and 1.2% from FIG. 10), they hardly change. In addition, since the value of the shear strain of the resin-free (bare) structure is 7.8, there is a considerable difference compared with the resin structure, and the effect of the resin is understood. The results of study of the amount of quartz filler (hereinafter sometimes abbreviated as filler) and the amount of rubber in this resin system will be described. Acid anhydride cured alicyclic epoxy as epoxy resin to improve the heat degradation characteristics and Tg (glass transition temperature) of the resin.
Alternatively, one composed of at least one of bisphenol A type epoxy was used. FIG. 4A shows the relationship between the Young's modulus and the coefficient of thermal expansion with respect to the filler volume content of the resin. Here, ○ indicates the Young's modulus, and △ indicates the thermal expansion coefficient. The resin itself is an epoxy having a low Young's modulus. As can be seen from FIG. 4A, the Young's modulus and the coefficient of thermal expansion have an inverse correlation. As can be seen from FIG. 4, the coefficient of thermal expansion is 30 × 10 ⁻⁶ / ° C.
Filler content should be at least 45Vol% to be below
The above is preferred. On the other hand, it is necessary to fill the space between the ceramic substrate and the organic multilayer substrate. FIG. 4 (b) shows the relationship between the Young's modulus and the coefficient of thermal expansion with respect to the rubber content for lowering the Young's modulus. In the figure, the mark ○ indicates the Young's modulus, and the mark △ indicates the coefficient of thermal expansion. Polybutadiene-based and silicone-based rubbers are possible, but silicone-based materials having excellent heat-resistant deterioration characteristics are shown. As the silicone content increases, the coefficient of thermal expansion increases slightly, but the Young's modulus decreases after 5 wt%. 1
If the content is 5 wt% or more, the dispersibility becomes poor, and problems such as an increase in the coefficient of thermal expansion (approaching about 30 × 10 ⁻⁶ / ° C.) occur. Therefore, in order to reduce the Young's modulus and improve the heat cycle resistance, the silicone content of the resin is preferably 5 to 15% by weight. The following composition was selected as an example of the resin composition. The epoxy resin is a non-solvent type, but the concept regarding the resin properties is the same for the solvent type polyimide resin. Fig. 5 shows an organic-inorganic composite multilayer substrate with a Si chip mounted (left) and a chip carrier mounted (right).
FIG. Glass ceramic substrate has low expansion (3.
(5 × 10 ^-6 / ° C) and high rigidity make it less susceptible to printed circuit boards with a high coefficient of thermal expansion, ensuring high reliability even when a 10 mm square Si chip is mounted. Since the chip carrier on the right side is also a low dielectric constant glass-ceramic substrate having the same coefficient of thermal expansion as the substrate of the chip carrier, the bonding portion has high reliability. By making the glass ceramic substrate on the printed board wider than the chip carrier, the terminal 19 for repair wiring was formed, and wiring to the adjacent ceramic substrate was made possible. In addition, Pb-60% Sn
Solder 16 (melting point: 183 ° C) was used, and it was designed to be able to join without dissolving Sn-5% Sb solder (melting point: 232 ° C) forming the organic-inorganic composite multilayer substrate. The Si chip in the chip carrier is made of Pb-5% Sn solder (melting point 300
° C), the sealing part and the heat sink part use Pb-15% Sn solder (melting point 260 ° C), so that there is no problem during repair and soldering. Fig. 6 shows the bellows for heat diffusion after the chip carrier is mounted on the organic-inorganic composite multilayer substrate.
FIG. 2 is a cross-sectional view of a structure in which a 21-inch water-cooled unit 23 is attached with low-temperature solder 24. For high-speed calculation, it is necessary to efficiently cool a high-power chip of several tens of W class, so the carrier 20 sealing frame shows a thermal expansion coefficient almost equivalent to that of glass ceramics, and
High thermal conductivity AIN was used. Similarly, the material in contact with the carrier of the water cooling unit was SiC having low thermal expansion and high thermal conductivity. FIG. 7 shows a structure in which a capacitor is built in a ceramic substrate of a chip carrier (a). The electrodes provided on the inner surface of the sheet-like high dielectric material are connected to the ground and the power supply. Significant speed-up is possible by incorporating a capacitor. A thin-film resistance layer 26 for impedance matching is formed on a surface of a glass ceramic substrate provided on a printed board. (B) is an enlarged view of the thin film resistance layer. A resistance layer 26 is provided between adjacent bumps. The insulating layer is polyimide and the thin film is Al or Cu. The resistance layer may be provided on the back side (printed board) of the glass ceramic substrate, and the printed board side is preferable from the viewpoint of protection. The structure of the present invention makes it possible to incorporate a resistance layer and a capacitor in this ceramic substrate, or to provide a repair wiring, and to add functions that were not possible with conventional printed boards. Was. FIG. 8 shows an example of a simplified package structure according to the present invention. 3A, the back surface of the chip 10 is bonded with a thermal conductive grease 31 and can be sealed with a copper-based material. In the case of solder sealing 24, the thermal expansion is 8 × 10
A Cu-C, Cu-W composite material of ^-6 / ° C is desirable for thermal stress. (B) shows a multi-chip carrier.
In this case, since the chip is protected by the chip carrier, the whole sealing may be made of resin. FIG. 9 shows an example in which a matching layer is provided in a ceramic substrate example of a chip carrier since no matching layer is provided in the ceramic substrate of the organic-inorganic composite multilayer substrate. In this case, there is no space on the ceramic substrate on the printed board for providing the repair wiring.

【The invention's effect】

According to the present invention, it is possible to speed up the calculation,
The yield is expected to be greatly improved, and high-density and compact mounting is possible.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is a sectional view of a conventional technique.

FIG. 3 is a sectional view of an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a high reliability mechanism of the present invention.

FIG. 5 is a cross-sectional view in which a chip and a chip carrier using the present invention are mounted.

FIG. 6 is a cross-sectional view when a water cooling structure is attached to the present invention.

FIG. 7 is a sectional view (a) and an enlarged view (b) of a structure obtained by adding functionality to the present invention.

FIG. 8 is a sectional view of a simplified module using the present invention.

FIG. 9 is a sectional view of a modification in which a chip carrier is mounted on the present invention.

FIG. 10 is an explanatory diagram of a high reliability mechanism of the present invention.

[Explanation of symbols]

 1. Glass ceramics 2. Organic multilayer substrate 3. Copper foil terminals

Continued on the front page (72) Inventor Mamoru Sawahata 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratory, Ltd. (72) Inventor Ichiji Yamada 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture, Hitachi, Ltd. 72) Inventor Satoru Ogiwara 4026 Kuji-cho, Hitachi City, Ibaraki Pref.Hitachi, Ltd.Hitachi Research Laboratories, Ltd. (72) Inventor 3 ▲ Yoshi ▼ Tadahiko 4026 Kuji-cho, Hitachi City, Ibaraki Pref.Hitachi, Ltd. Person Shigeo Amagi 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Laboratory (72) Inventor Toru Koyama 4026 Kuji-machi, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Laboratory Co., Ltd. (72) Inventor Fumiko Kobayashi No. 1 Horiyamashita, Hadano-shi, Pref.Hitachi, Ltd. Kanagawa Factory (72) Inventor Minoru Yamada 1-280, Higashi Koikebo, Kokubunji-shi, Tokyo Within the Central Research Laboratory of Hitachi, Ltd. (56) References JP-A-57-166051 , )

Claims (7)

(57) [Claims] 1. A ceramic substrate having a low dielectric constant and a low expansion in which a front terminal and a rear terminal are electrically connected, a chip or a chip carrier connected to the front terminal of the ceramic substrate, and an organic substrate connected to the rear terminal of the ceramic substrate. An organic-inorganic composite multilayer substrate comprising: a multilayer substrate; and a resin filling a gap between the organic multilayer substrate and the ceramic substrate. 2. The organic-inorganic composite multilayer substrate according to claim 1, wherein a plurality of said ceramic substrates are mounted on said organic multilayer substrate. 3. The organic-inorganic composite multilayer substrate according to claim 1, wherein a pitch of front terminals of the ceramic substrate is smaller than a pitch of rear terminals joined to the organic multilayer substrate. 4. The organic-inorganic material according to claim 1, wherein the ceramic substrate is provided with a terminal for repair wiring other than a connection region with the chip or the chip carrier. Composite multilayer board. 5. The organic-inorganic material according to claim 2, wherein said ceramic substrate is provided with a terminal for connection with said ceramic substrate adjacent to a region other than a connection region of said chip or said chip carrier. Composite multilayer board. 6. The organic-inorganic composite multilayer substrate according to claim 1, wherein the ceramic substrate has a resistance layer for impedance matching. 7. The organic-inorganic composite multilayer substrate according to claim 1, wherein a capacitor for increasing the speed is provided inside the ceramic substrate.