JP3589928B2 - Semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which semiconductor modules each having a build-up wiring layer capable of increasing a mounting density are stacked.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the integration density of semiconductor chips has increased, and semiconductor packaging technology is also required to have higher density. Typical examples of the high-density mounting technology of this semiconductor chip include a wire bonding technology and a TAB technology. As the highest-density mounting technology, a flip-chip mounting technology is used. It is widely used as a technology for mounting on a computer.
[0003]
Further, a semiconductor package as a semiconductor device is described in, for example, Journal of the Institute of Electronics Packaging Vol. 1, No. 1, pp. 19-23, 1998, a BGA (Ball Grid Array) capable of coping with the increase in the number of pins has been developed. Has become the mainstream of high-density packaging technology.
[0004]
However, these high-density mounting technologies involve two-dimensionally arranging semiconductor chips on a circuit wiring board, and there is a physical limit to the area for mounting a semiconductor device on the circuit wiring board. There has been a limit in the mounting area as a technology for mounting small and high-density system electronic devices that require a large number of components to be mounted.
[0005]
For this reason, in the current advanced mounting technology, a three-dimensional mounting technology in which the space direction is also a mounting region of the semiconductor device is being developed, compared to the conventional two-dimensional mounting technology.
[0006]
As an example, FIG. 10 shows a mounting example in which MCMs (Multichip Modules) are stacked. As a method of three-dimensionally mounting different kinds of semiconductor chips, as shown in FIG. 10, a plurality of semiconductor chips 103 are flip-chip mounted on a circuit wiring board 104, and vertical wirings 109 are formed on side surfaces of the circuit wiring board. Is commonly done. As a proposal for three-dimensionally mounting the MCM unit substrate on which the semiconductor chip is mounted as described above, for example, JP-A-5-235255 can be cited.
[0007]
However, although the above-described method of stacking the MCM circuit wiring board or the TCP semiconductor package and performing three-dimensional mounting can be easily realized in terms of structure by an extension of the conventional two-dimensional mounting technology, the MCM can be easily realized. The connection area for vertically stacking with the plane wiring area of the circuit wiring board and the mounting area for vertically connecting with the sealing area of the TCP semiconductor package are factors that hinder the improvement of the mounting density, and the semiconductor chip mounting. There has been a limit to achieving the ultimate high density.
[0008]
To cope with this problem, Japanese Patent Application Laid-Open Nos. 8-279588 and 8-316408 disclose that a multilayer wiring metal exposed on the side surface of an MCM multilayer circuit wiring board is used as a side electrode of a three-dimensional mounting block, and then, in a vertical direction. A proposal is made to connect a circuit board that connects to each other to block side electrodes to increase the density of the vertical mounting area. This structure is an application of the bare chip semiconductor device shown in FIG. 11 to a multi-layer wiring board. I have.
[0009]
The semiconductor device shown in FIG. 11 is obtained by stacking semiconductor modules in which a circuit wiring layer 115 connected to a semiconductor chip 113 mounted on a circuit wiring board 114 extends to the peripheral end of the substrate 114. A side surface electrode 116 is formed on the side surface (laminated surface).
[0010]
However, although the vertical electrode connection by the side electrode can increase the density of the vertical wiring area, it does not basically improve the two-dimensional mounting density. As the wiring board, a build-up wiring board capable of increasing the density of circuit wiring is often used as a unit board of a multilayer unit.
[0011]
However, when this build-up multilayer substrate is used as a laminated unit substrate, the thickness of the Cu wiring cannot be increased due to the manufacturing process, so that the electrode terminal area cannot be sufficiently secured in order to use the Cu multilayer wiring cross section as the block side electrode. was there. Furthermore, when the build-up multilayer wiring is used as the block side electrode, stress distortion generated in the block side electrode due to the difference in the coefficient of thermal expansion between the base substrate, the build-up wiring, and the side wiring substrate is increased. There is a problem in connection reliability in which stress strain cannot be sufficiently reduced by concentrating on the up multilayer wiring layer portion.
[0012]
[Problems to be solved by the invention]
As described above, it is effective to use a build-up wiring board as a technique for mounting semiconductor chips at high density, but the wiring in the build-up wiring board has a large film thickness due to the manufacturing method. This is difficult, or the thermal expansion coefficient between the laminating direction of the wiring and the surface direction of the side-surface electrode substrate is different.
[0013]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor device having high connection reliability between a build-up wiring substrate and a side electrode substrate.
[0014]
[Means for Solving the Problems]
A semiconductor device of the present invention includes a base substrate, a first conductor layer formed on the base substrate, and having a circuit wiring having an end extending to the peripheral end of the base substrate; An interlayer insulating layer and a second conductor layer are laminated, the first conductor layer and each of the second conductor layers are connected by a via hole at a peripheral end of the substrate, and the via hole is formed on the laminated surface. A semiconductor module comprising an exposed build-up wiring layer and a semiconductor chip mounted on the build-up wiring layer is stacked.
[0015]
Further, a side wiring board electrically connected to an end of the base substrate of the first conductive layer may be provided.
[0016]
Furthermore, it is also possible to expose the build-up wiring layer on the lamination surface and to electrically connect to the side wiring substrate via the via hole.
[0017]
That is, the present invention has been realized in that the stress due to the difference in the thermal expansion coefficient between the semiconductor module having the build-up wiring layer and the side wiring board increases as the distance from the base substrate increases. According to the present invention, by electrically connecting the side wiring board and the semiconductor module in the conductive layer closest to the base substrate, it is possible to reduce a decrease in connection reliability due to stress strain.
[0018]
Furthermore, the via holes connecting the conductive layers formed on the surface of the base substrate and the conductive layers in the build-up wiring are thicker than the single-layer conductive layers. By connecting to a wiring board, it is possible to increase the strength and further improve the connection reliability.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described with reference to FIGS.
[0020]
FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a first sectional process view showing a method for manufacturing a semiconductor device according to the present invention, and FIG. FIG. 4 is a sectional view showing a second step of the method for manufacturing a semiconductor device according to the present invention. FIG. 5 is a partially enlarged cross-sectional view of the semiconductor device according to the present invention.
[0021]
The semiconductor device shown in FIG. 1 includes a first semiconductor module 1 and a second semiconductor module. 2 Are laminated, and a side surface wiring board 15 is bonded to a side surface (laminated surface) of the laminated body.
[0022]
In each of the semiconductor modules 1 and 2, a base substrate wiring layer 10 serving as a first conductive layer is formed on the surface of the base substrate 7 provided with the through hole 9, and an interlayer insulating layer 12 is formed on the surface of the base substrate wiring layer 10. Further, a build-up multilayer wiring layer 8 is formed in which build-up wiring layers 11 made of conductive layers are sequentially stacked. Further, the build-up wiring layers 11 or the build-up wiring layer 11 and the base wiring layer 10 are partially connected by via holes 22. The semiconductor chips 3, 4, 5, and the chip component 6 are mounted on the build-up multilayer wiring layer 8, and are connected to the base substrate wiring 10 via the ball electrodes 14, respectively. Further, the semiconductor chips 4 and 5 are mounted on the surfaces facing the first semiconductor module 1 and the second semiconductor module 2, respectively, and are arranged so as not to overlap in the stacking direction, so that the mounting density in the stacking direction is reduced. Raising.
[0023]
The semiconductor modules 1 and 2 are laminated by an insulating resin 18 made of an adhesive.
[0024]
The side wiring board 15 joined to the side surface of the stacked body composed of the semiconductor modules 1 and 2 has a substrate 23 and a multilayer wiring 24 formed on the joining surface side of the substrate 23. The multilayer wiring 24 is connected to the external connection terminal 25 via the through hole 9 formed in the substrate 23.
[0025]
The stacked body and the side wiring board 15 are reinforced by the sealing resin 21, and an end portion (side surface electrode) of the base board wiring layer 10 exposed on the stacked surface of the stacked body including the semiconductor modules 1 and 2. Are connected to the multilayer wiring 24 on the side surface base substrate 25 via the ball electrodes 14 arranged on the side.
[0026]
Next, a method for manufacturing a semiconductor device as shown in FIG. 1 will be described with reference to FIG.
[0027]
First, a circuit wiring board on which the semiconductor chips 3, 4 and the chip component 6 are mounted is prepared (FIG. 2f). This circuit wiring board material is generally used for the purpose of the present invention. For example, the printed circuit board SLC disclosed in U.S. Pat. No. 4,811,082 or a system in which an insulating layer and a conductor layer are mutually built up on a normal glass epoxy board is disclosed. (Surface Laminar Circuit) substrate can be used. Therefore, for example, it is also possible to use a multilayer flexible substrate of a system in which copper wiring is build-up formed on the surface using a polyimide resin as a substrate main material, or a ceramic multilayer substrate of a build-up system. Although not particularly limited, a multi-layer circuit wiring board having a basic configuration of an SLC substrate having a glass epoxy base plate as a material of the multi-layer circuit wiring board is used for the explanation in this embodiment.
[0028]
A semiconductor module constituting a semiconductor device according to the present invention using this multilayer wiring board can be manufactured by the following method.
[0029]
First, by a known method, 0.39 mm thick of 96 m in which an 18 μm thick copper foil 10 ′ is laminated on a base substrate 7 made of glass epoxy m A × 96 mm double-sided copper-clad glass epoxy substrate is prepared (FIG. 2a).
[0030]
Next, a 250 μmφ through-hole is formed in a necessary portion of the base substrate 7 with a drill, and plating is performed by a known method using an electroless plating method and an electroplating method to form a through-hole 9. The thickness of the 18 μm copper foil is increased to 22 μm by this copper through-hole plating (FIG. 2B).
[0031]
Next, a resist film is coated on the copper foil 10 'on the base substrate in which the through holes 9 are formed, and a base substrate wiring layer 10 is formed by a known method using iron (III) chloride (FIG. 2C). Although this wiring pattern is not particularly limited, in the present embodiment, in consideration of the production yield, the layout is such that 72 11.5 mm × 5.2 mm semiconductor modules are arranged. It was designed with a pattern in which the copper wiring was extended to the divided dicing line so as to be exposed, with a line / space = 100 μm / 100 μm and a through hole land diameter of 550 μm.
[0032]
Next, a photosensitive epoxy resist was applied on the entire surface of the substrate on which the base substrate wiring 10 was formed by a known technique, and then the interlayer insulating layer 12 having the vias 22 formed at necessary places was formed by exposure / development. The arrangement of the vias 22 is not particularly limited, but in this embodiment, the via diameter is set to 75 μm and the land diameter is set to 150 μm. However, from the gist of the present invention, the via hole 22 provided in the wiring portion on the dicing line was designed to have an opening of 100 μm × 400 μm in order to improve the manufacturing yield.
[0033]
Further, a copper build-up wiring layer 11 having a thickness of 18 μm is formed on the interlayer insulating layer 12 by a known method. Although this wiring pattern is not particularly limited, Line / Space = 75 μm / 75 μm in the present embodiment (FIG. 2D).
[0034]
Using a similar method, a plurality of interlayer insulating layers 12 and build-up wiring layers 11 were sequentially formed to form a build-up multilayer wiring layer 8. The build-up wiring layer 12 formed on the uppermost layer has Line / Space = 50 μ / 50 μm in consideration of the I / O pitch of the semiconductor chip to be mounted (FIG. 2E).
[0035]
Further, a solder resist 25 of 120 μm was formed on the front and back surfaces of the build-up substrate except for the electrode portions.
[0036]
In addition, a build-up multilayer wiring layer and a semiconductor chip were mounted on the back surface of the base substrate in the same manner.
[0037]
Next, the semiconductor chips 3, 4 and the chip component 6 are mounted on the obtained multilayer circuit wiring board.
[0038]
In this manner, a semiconductor module block as shown in FIG. 2F is created, and the semiconductor module blocks are stacked and divided and diced to form a semiconductor device in which the first semiconductor module and the second semiconductor module are stacked. Created.
[0039]
The semiconductor chip and chip components mounted on the semiconductor module are general and not particularly limited from the gist of the present invention, but the present invention is applied to a micro visual module which is a micro CCD camera shown in FIG. A CCD imaging signal processing circuit to be mounted is configured. The semiconductor chips constituting the stacked semiconductor modules include a CCD element 44, an amplifier element 45 for amplifying an analog signal from the CCD element 44, and a digital / analog conversion element (CDS) for converting an analog image signal from the CCD element 44 into a digital signal. / AD) 46, a driver element (v-driver) 47 for driving the CCD element, or a gate array element (GPA) 48 for wirelessly controlling the CCD image signal converted into a digital signal.
[0040]
A 2.0 mm × 3.25 mm V-driver having I / O = 19 as a first semiconductor chip, and a 3.38 mm × 3.23 mm CDS / AD chip having I / O = 64 as a second semiconductor chip As a third semiconductor chip, a 3.8 mm × 3.8 mm G / A chip having I / O = 80, 14 chips of 1005 chip capacitors, 2 chips of 2012 chip capacitors, and 4 chips of 1005 chip resistors were used.
[0041]
A method for manufacturing a semiconductor module by mounting a semiconductor chip and a chip component on a multilayer circuit wiring board will be specifically described below.
[0042]
First, after a solder paste is screen-printed on the electrode terminals provided on the circuit wiring board by using a screen printing metal mask, chip components are mounted and the whole is reflowed. As the solder paste, a Pb / Sn = 95/5 solder paste is used. After solder reflow, the BGA circuit wiring board is washed with isopropyl alcohol for 10 minutes.
[0043]
One semiconductor chip is mounted on a multilayer circuit wiring board by flip-chip mounting using a known bump electrode. Specifically, using a flip-chip bonder that performs alignment using a half mirror, which is a well-known technique, a V-driver semiconductor chip on which solder bump electrodes are formed and circuit wiring on a multilayer circuit wiring board are configured. Of the electrode terminals to be adjusted. The semiconductor chip is held in a collet having a heating mechanism and is preheated in a nitrogen atmosphere at 350 ° C.
[0044]
Next, in a state where the bump electrodes of the semiconductor chip and the electrode terminals of the circuit wiring board are in contact with each other, the collet is further moved downward to a pressure of 30 kg / mm. ² , And the electrode terminals of the circuit wiring board and the bump electrodes are brought into contact with each other with a mechanical pressure applied. Further, in this state, the temperature is raised to 370 ° C. to melt the solder, and the electrode terminals of the circuit wiring board and the bump electrodes of the semiconductor chip are connected.
[0045]
Using the same method, the CDS / AD as the second semiconductor chip and the GA as the third semiconductor chip are flip-chip mounted on the circuit wiring board. This solder bump electrode uses Pb / Sn = 37/63 eutectic solder as an electrode material.
[0046]
According to this method, a semiconductor device in which a semiconductor chip is flip-chip mounted on a multilayer circuit wiring board can be realized.
[0047]
Furthermore, it is also possible to dispose a sealing resin, which is a known technique, in a gap portion formed between the semiconductor chip and the multilayer circuit wiring board. The resin to be sealed is not particularly limited, but for example, an epoxy resin containing a bisphenol-based epoxy and an imidazole curing catalyst, an acid anhydride curing agent and a spherical quartz filler in a weight ratio of 45 wt%, or the like may be used. it can.
[0048]
Next, the first semiconductor module and the second semiconductor module are stacked and connected to the side wiring board to complete the semiconductor device. The method will be described with reference to FIG.
[0049]
For example, after the first semiconductor module 1 and the second semiconductor module 2 are aligned using a known mounter (FIG. 4A), an insulating resin 18 for bonding is arranged on the surface of the first semiconductor module. Further, after the second semiconductor module 2 is pressed against the first semiconductor module 1 with the insulating resin 18 interposed therebetween, the insulating resin is thermally cured (FIG. 4B).
[0050]
The insulating resin 18 for adhesion is not particularly limited, but in the present embodiment, 100 parts by weight of a cresol novolac type epoxy resin (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.), and a phenol resin 54 as a curing agent Parts by weight, 100 parts by weight of fused silica as a filler, 0.5 parts by weight of benzyldimethylamine as a catalyst, 3 parts by weight of carbon black as an additive, and 3 parts by weight of a silane coupling agent. A resin melt was used.
[0051]
In the present embodiment, as the first semiconductor module 1, a V-driver, a G / A, 5 chips of 1005 chip capacitors, 1 chip of 2012 chip capacitors, and 1 chip of 1005 chip resistors are mounted, and a second semiconductor module 1 In this example, a CDS / AD, 9 chips of 1005 chip capacitors, 1 chip of 2012 chip capacitors, and 1 chip of 1005 chip resistors are mounted, but these configurations are not particularly limited.
[0052]
Further, when the step of laminating the semiconductor modules shown in FIG. 4A is performed, it is preferable to arrange a spacer or the like between the first semiconductor module and the second semiconductor module as necessary. Thereby, the thickness of the insulating resin for block lamination can be made uniform, and as a result, the thickness of the blocks to be laminated can be made uniform. The lamination spacer is not particularly limited. For example, in this embodiment, a 5 mmW × 1 mmD × 0.18 mmH rectangular parallelepiped block made of a silicon material was used.
[0053]
Further, a sealing resin of the same material as the insulating resin for block lamination, for example, is disposed on the front surface portion of the first semiconductor module unit and the rear surface portion of the second semiconductor module unit as needed. Although this sealing resin material is not particularly limited, the same material as the insulating resin for block lamination is effective for relieving stress and strain concentrated on the ball electrode, and is preferable from the viewpoint of connection reliability. is there.
[0054]
Next, split dicing is performed using a known dicing apparatus. FIG. 5 is a diagram for explaining division dicing.
[0055]
FIG. 5 is a partially enlarged view of a cross section of a region where the divided dicing line 17 of the semiconductor module and the base substrate 7 intersect.
[0056]
As described above, since the vias 22 are formed on the first base substrate wiring 10, the vias 22 are integrated with the build-up wiring layer and have a large thickness.
[0057]
Along the dividing dicing line 17, the laminated module substrate block is divided into 72 11.5 mm × 5.2 mm semiconductor modules. By dividing the module substrate along the dicing line, a 98 I / O semiconductor device having a 40 μm-thick Cu wiring cross section having a sufficient connection area as a block side electrode can be realized.
[0058]
The semiconductor device manufactured by the above process had an outer dimension of 5.2 mmW × 5.2 mmH × 11.5 mmD. However, if necessary, the block side electrode and the block outer dimension were highly accurate by the following method. Can be
[0059]
Specifically, the glass epoxy substrate and the epoxy sealing resin are mechanically polished. In the mechanical polishing, it is preferable to make the unevenness to about ± 3 μm or less by micro-polishing after uniformizing to ± 5 μm by macro-polishing, in order to increase the precision of the block external dimensions. Macro-polishing uses, for example, cerium oxide having a particle size of about 5 μm to 10 μm, or water-resistant abrasive paper of about # 1000, and micro-polishing uses cerium oxide, alumina oxide, or diamond having a particle size of about 0.3 μm. Is preferred. At this time, if a wet polishing method using a liquid polishing paste as an abrasive is used, a difference in the polishing rate occurs between the glass fiber and the epoxy resin, and irregularities are generated. It is preferable to use a dry polishing method using a disc disk.
[0060]
By using the above polishing method, the semiconductor device according to the present invention can improve the external dimensions up to dimensions of 5.2 mm ± 0.1 mm × 5.2 mm ± 0.1 mm × 11.5 mm ± 0.1 mm. As a result, the unevenness of the side electrode of the block can be improved to ± 1 μm.
[0061]
Further, the semiconductor device is mounted on the side wiring board 15 as shown in FIG.
[0062]
The steps of mounting the semiconductor device on the side wiring board 15 are as follows.
[0063]
Specifically, first, the side wiring board 15 is prepared. Although the configuration of the side wiring board is not particularly limited, in the present embodiment, a printing method of a system in which an insulating layer and a conductor layer are mutually built up on US Pat. Substrate An SLC (Surface Laminar Circuit) substrate was used. Therefore, it is also possible to use a multilayer flexible substrate of a system in which a copper wiring is build-up formed on the surface using, for example, a polyimide resin as a main material of the substrate, or a ceramic multilayer substrate of a build-up system.
[0064]
Further, 98 I / O solder ball electrodes 20 having a size of 200 μmφ corresponding to the block side electrodes of the three-dimensionally mounted semiconductor device are arranged on the surface of the side wiring board, and are interconnected with the solder balls inside the wiring board. Circuit wiring is formed. The internal circuit wiring is not particularly limited, either, a metal selected from Al, Au, W, Cu, Ni, Cr, Pt, Pd or the like as a wiring material, or a laminated metal selected from these metals, or An alloy containing a metal as a main component is preferable, and it is preferable that a region other than a region connected to a semiconductor chip of a circuit wiring formed on a main surface of the multilayer circuit wiring board is covered with a solder resist. In the present embodiment, a structure in which a circuit wiring pattern having a Cu wiring thickness of 20 μm is formed as a build-up layer is used as a side wiring substrate.
[0065]
For mounting the semiconductor device on the side wiring board, a bonder having a half mirror and performing alignment can be used. At this time, the heater for mounting the connection wiring substrate in the vertical direction and the collet for holding the semiconductor device are heated to 180 ° C., but this temperature is lower than the eutectic temperature of the solder constituting the ball electrode, so that the ball electrode is melted. Not in a state.
In addition, ball electrodes on the side wiring board 14 Align As described above, the collet is further moved downward while the semiconductor device and the ball electrode on the circuit wiring board are in contact with each other, and a pressure of 30 kg / mm 2 is applied to the collet. 14 And the side electrode of the semiconductor device (the cross section of the base substrate wiring layer) is brought into contact with the substrate under a state where a mechanical pressure is applied. Further, in this state, the temperature is raised to 250 ° C. to melt the solder, and the side electrode terminal and the ball electrode are connected. Solder ball at this time Electrode 14 The composition is Pb / Sn = 37/63, and the composition of the solder bump for flip-chip mounting the semiconductor chip is also Pb / Sn = 37/63. Since the semiconductor chip is firmly fixed by the sealing resin, the solder bump electrode of the semiconductor chip does not re-melt and no connection failure occurs.
[0066]
It should be noted that the solder balls may not be arranged on the side wiring board, but may be arranged directly on the side surfaces of the semiconductor device. In this case, it is possible to optimize the side-surface electrode arrangement of the semiconductor device by forming a Cu / polyimide multilayer wiring on the side surface of the semiconductor device and performing vertical connection wiring.
[0067]
By performing the above steps, a CCD imaging signal processing circuit block for a micro visual module in which a 5.2 mmW × 5.2 mmH × 11.5 mmD semiconductor device is mounted on a circuit wiring board as shown in FIG. 1 is realized. it can.
[0068]
Further, when the performance of the semiconductor device according to the present invention manufactured by the above steps was evaluated, the following results could be obtained.
[0069]
FIG. 6 shows a first semiconductor module mounting a 11.5 mm × 5.2 mm V-driver and a G / A used for describing an embodiment of a semiconductor device according to the present invention, and a 11.5 mm × 5.2 mm. The second semiconductor module mounting the CDS / AD is manufactured as a three-dimensional mounting block module of 5.2 mmW × 5.2 mmH × 11.5 mmD as described above. It is a result of comparing mounting densities manufactured by MCM three-dimensional mounting, TCP three-dimensional mounting, and secondary current mounting.
[0070]
As is clear from FIG. 6, in the conventional two-dimensional mounting technology, the mounting density decreases as the number of semiconductor chips mounted increases. This is because the peripheral circuit area required for mounting a semiconductor chip is extremely large, and the peripheral circuit area increases as the number of semiconductor chips mounted on a circuit wiring board increases, thereby lowering the mounting density.
[0071]
However, when a three-dimensional mounting technology is used as a method for mounting a semiconductor chip, one or more regions that cannot be realized with the two-dimensional mounting technology can be secured as the mounting density. However, when the MCM circuit wiring board and the TCP are stacked as a stacked structure, the circuit wiring area, the package sealing area, and the vertical wiring connection area of the circuit wiring board cannot be neglected as the number of mounted semiconductor chips increases. Therefore, there is a limit in improving the mounting density as compared with the case where semiconductor bare chips having the same dimensions are stacked.
[0072]
In order to solve this problem, the semiconductor device according to the present invention uses a build-up multilayer wiring board as a wiring board on which a semiconductor module is mounted, and further uses a block side electrode that does not have a problem of mounting density reduction due to a vertical connection region. Therefore, it is possible to bring the mounting density of the semiconductor device close to the value of the lamination of semiconductor bare chips of the same dimensions, which enables the highest density.
[0073]
Further, when the reliability of the semiconductor device according to the present invention was evaluated, the results shown in FIG. 7 were obtained.
[0074]
FIG. 7 shows a sample in which a 5.2 mmW × 5.2 mmH × 11.5 mmD semiconductor device obtained as described above is mounted on a side wiring board composed of a glass epoxy multilayer wiring board using solder balls. This is the result of evaluating the connection reliability and is indicated by a solid line.
[0075]
For comparison, the results when only the build-up wiring layer is extended to the end of the semiconductor device and the single-layer build-up wiring layer and the side wiring board are connected using solder balls are also indicated by dotted lines. I do.
[0076]
The case where the connection was opened at even one of the 98 pins was regarded as defective, and the vertical axis represents the cumulative failure rate and the horizontal axis represents the number of temperature cycles. The number of samples was 1,000, and the temperature cycle conditions were (-55 ° C (30 min) to 25 ° C (5 min) to 125 ° C (30 min) to 25 ° C (5 min)).
[0077]
In the structure using only the build-up multilayer wiring layer as the side electrode, about 20% of the connection failure occurred in 1000 cycles, and 100% of the connection failure occurred in 2000 cycles. From the graph, it is considered that two types of connection failures especially occur. The connection failure in the initial stage up to 1000 cycles is an initial connection failure due to a thin build-up wiring film thickness, and occurs after 1000 cycles. The connection failure is considered to be fatigue failure due to stress strain of the ball electrode. In order to confirm this consideration, samples of poor connection at each stage were extracted and analyzed by cross-sectional observation. As a result, the connection failure in the initial stage up to 1000 cycles occurred at the interface between the block side electrode and the solder ball, and the connection failure after 1000 cycles occurred inside the solder ball, and the connection failure up to 1000 cycles. Is a defect that occurs because the build-up wiring film thickness is thin, and the defect that occurs after 1000 cycles is the fatigue failure of the ball electrode.
[0078]
Further, in a structure using the build-up multilayer wiring layer as a side electrode, a known sealing resin was disposed at a solder ball portion. As a result, although the reliability of the semiconductor device is slightly improved, two types of connection failure occur as in the case of the structure in which the sealing resin is not provided, and the connection reliability of the block side electrode cannot be sufficiently ensured. confirmed.
[0079]
On the other hand, in the structure of the present invention in which the side electrode is formed on the base substrate, no connection failure occurs up to 3500 cycles, and it has been confirmed that the connection reliability is extremely improved. In particular, it can be seen that the connection reliability is significantly improved when compared with the experimental results in which the structure in which the semiconductor chip is not sealed with the block side surface electrode structure according to the present invention does not cause connection failure until 3000 cycles. This is because the semiconductor device according to the present invention has a cross section of the wiring film thickness obtained by summing the wiring film thickness on the base substrate and the build-up wiring film thickness, so that the wiring cross section can secure a sufficient value as the block side surface electrode area. In addition, since the wiring arranged on the base substrate constitutes the block side electrode, the thermal expansion coefficients of the connection wiring substrate and the base substrate in the vertical direction match, and the build-up having different thermal expansion coefficients is performed. This is probably because the layer acts as a layer for alleviating stress strain caused by the difference in thermal expansion coefficient.
[0080]
From the above results, the semiconductor device according to the present invention can easily increase the mounting density and extremely high connection reliability with respect to different types of semiconductor chips having different external dimensions of the semiconductor chip. It was confirmed that it was highly effective in solving the problem.
[0081]
The present invention is not limited to the above embodiment, and can be variously modified without departing from the gist thereof. For example, in this embodiment, three types of semiconductor chips are described. However, the number and types of semiconductor chips to be mounted, and chip components to be mounted are not particularly limited. The module is not particularly limited. Furthermore, it goes without saying that the sealing resin disposed between the semiconductor chips and the ball electrodes connected to the circuit wiring board are not limited.
[0082]
For example, FIG. 8 shows a schematic cross-sectional view of a semiconductor device as a modification.
[0083]
In the semiconductor device shown in FIG. 8, metal heat radiating paths 31, 32, and 33 are formed on the surface of each semiconductor module, and the heat generated from the semiconductor chips is brought into contact with the back surfaces of the semiconductor chips 3, 4, and 5, respectively. Is emitted outside the semiconductor device.
[0084]
When the reliability of this semiconductor device was evaluated, the results shown in FIG. 9 were obtained.
[0085]
FIG. 9 shows the result of evaluating the connection reliability of a sample in which the side wiring board is mounted on the semiconductor device shown in FIG. 8 as shown in FIG.
[0086]
When the semiconductor chip and the passive chip component are arranged so as to overlap with each other on the opposing semiconductor module surface, a connection failure occurs at 3000 cycles, and the connection failure becomes about 50% at 4000 cycles. Further, the connection reliability of the sample sealed with resin in this layout arrangement was improved up to 3500 cycles. From the graph, it is considered that two types of connection failures occur in particular, and connection failures in the initial stage up to 3500 cycles are caused by operation failures caused by local concentration of heat generated from the semiconductor chips. It is considered to be a failure, and the connection failure occurring after 3500 cycles is considered to be a fatigue failure due to stress strain of the ball electrode formed on the block side surface electrode. In order to confirm this consideration, samples at each failure stage were extracted and the semiconductor device was disassembled, and then the electrical characteristics of the module were evaluated. As a result, the connection failure in the initial stage up to 3500 cycles resulted in breakage of the semiconductor chip in the portion where the semiconductor chips overlap with each other, and the connection failure after 3500 cycles resulted in breakage of the solder ball of the block side electrode. From this, the connection failure up to 3500 cycles is a failure of the semiconductor chip caused by local concentration of heat generated from the semiconductor chip, and the connection failure occurring after 1000 cycles is the fatigue failure of the ball electrode. Was confirmed.
[0087]
On the other hand, in the semiconductor device of the present embodiment in which the semiconductor chip and the passive chip component are arranged so as not to overlap each other on the opposing semiconductor module unit surface, no connection failure occurs up to 4500 cycles, and the connection reliability is extremely improved. It was confirmed that. In particular, in a layout arrangement in which the semiconductor chip and the passive chip component according to the present invention do not overlap each other, the structure without the resin sealing around the side electrode of the block does not show a connection failure up to 5000 cycles. It can be seen that the performance has been greatly improved. This is presumably because the semiconductor device according to the present invention is uniformly distributed on the semiconductor module surface on which heat generated from the semiconductor chip is stacked, and the heat is efficiently distributed and radiated to the entire block.
From the above results, it has been confirmed that the semiconductor device according to the present invention is a highly effective technology that can easily improve the mounting density and heat dissipation in the module stacking direction.
[0088]
【The invention's effect】
As described above, according to the present invention, it is possible to obtain a semiconductor device having a high mounting density and high connection reliability with the side wiring board.
[Brief description of the drawings]
FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.
FIG. 2 is a first sectional process view showing a method for manufacturing a semiconductor device according to the present invention.
FIG. 3 is an explanatory view when the semiconductor layer of the present invention is used for a CCD.
FIG. 4 is a second sectional process view showing the method for manufacturing the semiconductor device according to the present invention.
FIG. 5 is a partially enlarged sectional view showing an embodiment of the semiconductor device according to the present invention.
FIG. 6 is a diagram showing a mounting density of the semiconductor device of the present invention.
FIG. 7 is a diagram showing connection reliability of the semiconductor device of the present invention.
FIG. 8 is a sectional view showing another embodiment of the semiconductor device of the present invention.
FIG. 9 is a diagram showing connection reliability of the semiconductor device of the present invention.
FIG. 10 is a cross-sectional view of a conventional semiconductor device.
FIG. 11 is a sectional view of another conventional semiconductor device.
[Explanation of symbols]
1. First semiconductor module
2... Second semiconductor module
3, 4, 5, ... semiconductor chip
7 Base board
8: Build-up multilayer wiring layer
9: Through-hole
10. Wiring of base board
11 Build-up wiring layer
12 ... interlayer insulating layer
14 Ball electrode
15 Side wiring board

Claims (2)

A substrate,
A first conductive layer formed on the substrate surface;
An insulating layer laminated on the first conductive layer;
A second conductive layer formed on the insulating layer , forming a build-up multilayer wiring layer together with the substrate, the first conductive layer, and the insulating layer;
A via conductor that penetrates through the insulating layer, is connected to at least one of the first conductive layer and the second conductive layer, and is exposed at least over the thickness of the insulating layer on a side surface of the build-up multilayer wiring layer ;
A semiconductor chip mounted on the build-up multilayer wiring layer ,
The semiconductor device according to claim 1, wherein the via conductor is electrically connectable on a surface exposed on a side surface of the build-up multilayer wiring layer . 2. The semiconductor device according to claim 1, further comprising: a side wiring substrate provided on a side surface of the build-up multilayer wiring layer and electrically connected to an exposed surface of the via conductor.

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