JPH118474A - Manufacture of multilevel board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a multilevel board which enables improvement in the reliability of connections between semiconductor chips and boards, the reduction in manufacturing time and improvement in productivity by including only a single heat treatment process. SOLUTION: A manufacturing method includes a process, in which a plurality of boards 1 on which semiconductor chips 2 are mounted, and which have electrode pads 4 and 5 on their surfaces and rears respectively, are provided, a process in which a plurality of the boards 1 are layered with connection solder members 7 between the electrode pads 4 and 5 of the respective board 1, and a process in which the layered boards 1 are heated so as to have the connection solder members 7 melted to connect the respective boards 1 to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer substrate, and more particularly, to a method for manufacturing a multilayer substrate suitable for stacking substrates made of a material having a high coefficient of thermal expansion such as glass epoxy.

[0002]

2. Description of the Related Art In recent years, with the development of multimedia,
There has been an increasing demand for electronic devices such as office computers, personal computers, game machines, and automation equipment to be smaller and lighter and have a larger memory capacity. In order to meet these demands, a technique for manufacturing a multilayer substrate in which substrates on which semiconductor chips are mounted is stacked has been developed.

FIGS. 4 to 7 are explanatory views showing a conventional method for manufacturing a multilayer substrate. As shown in FIG. 4, a semiconductor chip 11 is formed on a surface of a substrate 10 on which a circuit pattern is formed.
Is mounted, and the space between the substrate 10 and the semiconductor chip 11 is sealed with a sealing resin 12. Electrode pads 13 and 14 are provided on the front and rear ends of the substrate 10, respectively.

When manufacturing a multilayer substrate, first, the substrate 10
A flux 16 is applied to the electrode pad 13 on the surface of the solder ball and a solder ball 15 as a solder member for connection is mounted (see FIG. 4).

Next, the substrate 1 on which the solder balls 15 are mounted
0 is heated to melt the solder balls 15 and the electrode pads 1
The connection electrode 17 is formed on the substrate 3 (see FIG. 5).

Next, after the connection electrodes 17 formed on the substrate 10 and the electrode pads 14 formed on the back surface of the other substrate 10 are aligned, they are brought into contact with each other via a flux 18 and are sequentially laminated (FIG. 6).

Finally, the laminated substrate 10 is heated,
The connection electrodes 17 are melted to connect the respective substrates 10 (FIG. 7).
reference).

Japanese Patent Application Laid-Open No. 7-273146 discloses a flip-chip mounting method for a semiconductor device. FIG. 8 is a cross-sectional view for describing a method of mounting the semiconductor device. As shown in FIG. 8, the multilayer wiring board 2
A recess 20a is formed on the surface of the semiconductor device 21 at a position facing the solder bump 21a of the semiconductor device 21.

When mounting the semiconductor device 21 on the multilayer wiring board 20, first, a first solder paste 23 is filled and solidified on the conductor layer 22 formed on the bottom surface of the concave portion 20a of the multilayer wiring board 20.

Next, the solidified first solder paste 23
The space of the upper concave portion 20a is filled with a second solder paste 24 having a melting point lower than the melting points of the solder bumps 21a and the first solder paste 23.

Next, the semiconductor device 21 is mounted on the multilayer wiring board 20 so that the solder bumps 21a and the recesses 20a are aligned.
Place on top.

Finally, a reflow process is performed at the melting point temperature of the second solder paste 24.

Japanese Patent Application Laid-Open No. 7-273146 discloses that
It discloses that the solder bumps 21a are mounted on the multilayer wiring board 20 and then heated and melted.

[0014]

In the conventional method of manufacturing a multi-layer substrate, a solder ball 15 as a connection solder member is heated and melted on an electrode pad 13 of a substrate 10 by heating and melting the connection electrode 1.
After forming 7, the connection electrodes 17 of each substrate 10 and the electrode pads 14 on the back surface of the substrate 10 are aligned and stacked, and then heat-treated again to connect the substrates 10. Therefore, two heat treatment steps are required, and the semiconductor chip 1
A stress is generated at a connection portion between the semiconductor chip 11 and the substrate 10 based on a difference in thermal expansion coefficient between the semiconductor chip 11 and the substrate 10.

In particular, in the case of the substrate 10 made of an organic material such as glass epoxy, the substrate 10 is warped or thermally expanded due to thermal stress on the substrate 10 by two heat treatment steps, and There is a problem that the connection reliability between the substrate 11 and the substrate 10 is reduced.

Further, since two steps are required, that is, a step of mounting the solder balls 15 on the substrate 10 and a step of connecting the respective substrates 10, there is a problem that the manufacturing time becomes long.

JP-A-7-273146 discloses a method of mounting a semiconductor device and a multilayer substrate, but does not disclose a manufacturing method of stacking substrates. In addition, there is a problem that a process for connecting a solder bump to a semiconductor device is required, and that a different type of solder paste has to be filled.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and improves the reliability of connection between a semiconductor chip and a substrate by reducing the number of heat treatment steps to one. It is another object of the present invention to provide a method for manufacturing a multilayer substrate which can improve productivity.

[0019]

According to the present invention, there is provided a method of manufacturing a multi-layer substrate, comprising the steps of: (1) providing a plurality of substrates each having a semiconductor chip mounted thereon and having an electrode pad on each of the front and back surfaces;
(2) a step of laminating a plurality of substrates by sandwiching the connecting solder members between the electrode pads of each substrate; and (3) a step of heating the laminated substrates to melt the connecting solder members, thereby forming a connection between the substrates. And a connecting step.

According to the present invention, since the number of heat treatment steps is reduced from two to one as compared with the conventional manufacturing method, the connection between the semiconductor chip and the substrate is determined based on the difference in thermal expansion coefficient between the semiconductor chip and the substrate. The resulting stress can be reduced.

It is preferable to include a step of bonding between the substrate and the solder member for connection with a paste-like flux.

The connection solder member is, for example, a solder ball, and may include a substance having a melting point higher than the solder melting temperature.

The substrate is made of, for example, a material selected from the group consisting of glass ceramics, alumina, glass epoxy, and polyimide. In particular, when the substrate is made of a material having a large coefficient of thermal expansion such as glass epoxy, Has a greater effect.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are longitudinal sectional views showing a method for manufacturing a multilayer substrate according to the present invention.

As shown in FIG. 1, a semiconductor chip 2 is flip-chip mounted on the surface of a substrate 1, and the space between the substrate 1 and the semiconductor chip 2 is sealed with a sealing resin 3.
Further, electrode pads 4 and 5 are provided on the front and rear ends of the substrate 1, respectively. The electrode pads 4 provided on the front surface of the substrate 1 and the electrode pads 5 provided on the back surface are electrically connected through through holes (not shown).

The substrate 1 is made of an inorganic material such as glass ceramics, alumina, or an organic material such as glass epoxy,
Although it is made of polyimide or the like, in this embodiment, it is made of glass epoxy.

When manufacturing a multilayer substrate, first, a flux 6 is applied to the surface of the electrode pad 4 provided on the surface side of the substrate 1.
Is applied, the connection solder member 7 is mounted on the electrode pad 4.

The supply of the flux 6 onto the electrode pads 4 on the substrate 1 includes a printing method using a metal mask, a display method, a transfer method using pogo pins, and the like. When the flux 6 is supplied by the transfer using the pogo pins, the tips of the pogo pins arranged at the electrode pad positions of the substrate 1 are pressed against the liquid flux adjusted to a constant film thickness on the surface of the flat plate, and a certain amount of the flux 6 is supplied. Attach to pogo pin tip. Then, the pogo pins to which the flux 6 is attached are
A certain amount of flux 6 is applied onto the electrode pads 4 of the substrate 1 by pressing the electrode pads 4 on the electrode pads 4.

Further, as a method of supplying the connection solder member 7 on the electrode pad 4 of the substrate 1, mounting of a solder ball or printing with a metal mask is possible. In the present embodiment, the power is supplied by mounting a solder ball.

The method of mounting the solder balls 7 on the electrode pads 4 of the substrate 1 is, for example, by adsorbing the solder balls 7 on a collet surface having holes for vacuum adsorption at the arrangement positions of the electrode pads 4 on the substrate 1. After the solder balls 7 are arranged, the solder balls 7 and the electrode pads 4 on the substrate 1 are aligned and mounted.

Next, after aligning the solder balls 7 mounted on the substrate 1 with the electrode pads 5 formed on the back surface of the other substrate 1, the solder balls 7 are brought into contact with each other via a flux 6 and sequentially laminated (see FIG. 2). ).

Next, the laminated multilayer substrate is heated to the melting temperature of the solder balls 7 so that the solder balls 7 are melted.
To electrically connect the electrode pads 4 of the lower substrate 1 to the electrode pads 5 of the upper substrate 1 (see FIG. 3).

As the solder ball 7, for example, S
An n-Pb eutectic solder or a copper core solder ball having a copper ball surface coated with Sn-Pb eutectic solder is used.
Copper does not melt at the solder melting temperature because of its high melting point.
Therefore, by using a copper ball having a diameter larger than the thickness of the semiconductor chip, the gap between the substrates 1 can be made larger than the thickness of the semiconductor chip, and the contact between the front surface of the semiconductor chip 2 and the back surface of the substrate 1 can be made. Can be prevented.

According to the method for manufacturing a multilayer board of the present invention, after applying flux 6 to the electrode pads 4 on the surface of the board 1, the board 1 on which the solder balls 7 are placed is stacked, and then the solder balls 7 are heated and melted. Electrode pads 4 and 5 of each substrate 1
Connect between.

Therefore, the number of heat treatment steps is reduced from two to one as compared with the conventional manufacturing method.
Based on the thermal expansion coefficient difference between the semiconductor chip 2 and the substrate 1, the stress generated at the connection between the semiconductor chip 2 and the substrate 1 can be reduced, and the connection reliability between the semiconductor chip 2 and the substrate 1 is improved. In particular, a glass epoxy substrate 1 having a large thermal expansion coefficient
This effect is large when is used.

Also, by reducing the number of heat treatment steps from two to one, it is possible to shorten the manufacturing time of the multilayer substrate, thereby improving the productivity.

The present invention is not limited to the above embodiment, and various changes can be made within the scope of the technical matters described in the claims. For example, in the embodiment, the substrate 1 is stacked in four stages, but may be stacked in a plurality of stages other than the four stages. The materials of the substrate 1 and the solder balls 7 can be appropriately changed according to the application.

[0038]

According to the method for manufacturing a multilayer substrate of the present invention,
By sandwiching the connection solder members between the electrode pads of the respective substrates, a plurality of substrates are stacked, and then the stacked substrates are heated to melt the connection solder members, thereby connecting the respective substrates. Therefore, since the number of heat treatment steps is reduced from two to one as compared with the conventional manufacturing method, it is possible to reduce the stress generated at the connection between the semiconductor chip and the substrate based on the difference in the coefficient of thermal expansion between the semiconductor chip and the substrate. The connection reliability between the semiconductor chip and the substrate is improved. This effect is particularly significant when a glass epoxy substrate having a large coefficient of thermal expansion is used.

Further, by reducing the number of heat treatment steps from two to one, the manufacturing time of the multilayer substrate can be shortened, so that the productivity is improved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view for explaining a method for manufacturing a multilayer substrate according to the present invention.

FIG. 2 is a longitudinal sectional view for explaining a method for manufacturing a multilayer substrate according to the present invention.

FIG. 3 is a longitudinal sectional view for explaining a method for manufacturing a multilayer substrate according to the present invention.

FIG. 4 is a longitudinal sectional view illustrating a conventional method for manufacturing a multilayer substrate.

FIG. 5 is a longitudinal sectional view for explaining a conventional method for manufacturing a multilayer substrate.

FIG. 6 is a longitudinal sectional view for explaining a conventional method for manufacturing a multilayer substrate.

FIG. 7 is a longitudinal sectional view illustrating a conventional method for manufacturing a multilayer substrate.

FIG. 8 is a longitudinal sectional view for describing a method of mounting a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 7-273146.

[Explanation of symbols]

 1: substrate 2: semiconductor chip 3: sealing resin 4: electrode pad 5: electrode pad 6: flux 7: soldering member for connection (solder ball)

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H05K 3/36 (72) Inventor Naoji Senba 7-1-1 Shiba, Minato-ku, Tokyo Inside NEC Corporation

Claims (6)

[Claims] (1) a step of mounting a plurality of substrates each having a semiconductor chip and having electrode pads on the front and rear surfaces, and (2) sandwiching a connection solder member between the electrode pads of each substrate. Laminating a plurality of substrates,
And (3) a step of heating the laminated substrates to melt the connection solder members and connecting the respective substrates. 2. The method according to claim 1, further comprising the step of bonding the substrate and the connection solder member with a paste-like flux. 3. The method according to claim 1, wherein the connection solder member is a solder ball. 4. The method according to claim 1, wherein the connection solder member includes a substance having a melting point higher than a solder melting temperature. 5. The method according to claim 1, wherein the substrate is made of a material having a high coefficient of thermal expansion. 6. The substrate according to claim 1, wherein said substrate is made of a material selected from the group consisting of glass ceramics, alumina, glass epoxy and polyimide.
The method for manufacturing a multilayer substrate according to any one of the above items.