JP3465809B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP3465809B2 JP3465809B2 JP21790896A JP21790896A JP3465809B2 JP 3465809 B2 JP3465809 B2 JP 3465809B2 JP 21790896 A JP21790896 A JP 21790896A JP 21790896 A JP21790896 A JP 21790896A JP 3465809 B2 JP3465809 B2 JP 3465809B2
- Authority
- JP
- Japan
- Prior art keywords
- anisotropic conductive
- conductive film
- substrate
- chip
- electronic components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Abstract
Description
【０００１】[0001]
【目次】以下の順序で本発明を説明する。 発明の属する技術分野 従来の技術（図７（Ａ）〜（Ｅ）） 発明が解決しようとする課題 課題を解決するための手段 発明の実施の形態 （１）第１実施例（図１（Ａ）〜図２（Ｅ）） （２）第２実施例（図３（Ａ）及び（Ｂ）） （３）第３実施例（図４（Ａ）〜図５（Ｅ）） （４）他の実施例（図６） 発明の効果[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional technology (FIGS. 7A to 7E) Problems to be Solved by the Invention Means for solving the problems Embodiment of the invention (1) First embodiment (FIGS. 1A to 2E) (2) Second embodiment (FIGS. 3A and 3B) (3) Third embodiment (FIGS. 4A to 5E) (4) Another embodiment (FIG. 6) The invention's effect
【０００２】[0002]
【発明の属する技術分野】本発明は半導体装置及びその
製造方法に関し、例えばマルチチツプモジユール（ＭＣ
Ｍ：Multi Chip Module ）等の半導体装置及びその製造
方法に適用して好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, for example, a multi-chip module (MC
M: Multi Chip Module) and the like, and is suitable for application to a semiconductor device and its manufacturing method.
【０００３】[0003]
【従来の技術】従来、信号伝送速度の向上のために高密
度実装を図るべく、１枚の多層配線基板の基板上に各チ
ツプ間の配線長さが短くなるように複数のＩＣチツプ
（主として半導体チツプ）を搭載した高速性能を有する
マルチチツプモジユール（ＭＣＭ：Multi Chip Module
）が開発されている。2. Description of the Related Art Conventionally, a plurality of IC chips (mainly, a plurality of IC chips (mainly on the substrate of a multi-layered wiring board) are arranged so that the wiring length between the chips is shortened in order to achieve high-density mounting in order to improve signal transmission speed. High-speed multi-chip module (MCM: Multi Chip Module) equipped with a semiconductor chip
) Is being developed.
【０００４】ここで図７（Ａ）〜（Ｅ）において、マル
チチツプモジユール１の製造方法を示す。まず１枚の多
層配線基板２の一面２Ａ及び他面２Ｂにそれぞれ所定パ
ターンでランド３及び４を形成した後、当該各ランド３
に対応してそれぞれペースト状のはんだ５を印刷すると
共に、当該各ランド４を除く他面２Ｂにレジスト６を塗
布する（図７（Ａ））。続いて多層配線基板２の一面２
Ａの各ランド３に対応して印刷された各はんだ５を加熱
溶融することにより、それぞれはんだバンプ５Ａを形成
する（図７（Ｂ））。Here, FIGS. 7A to 7E show a method of manufacturing the multi-chip module 1. First, lands 3 and 4 are formed in a predetermined pattern on one surface 2A and the other surface 2B of one multilayer wiring board 2, respectively, and then each land 3 is formed.
Corresponding to the above, the paste-like solder 5 is printed, and the resist 6 is applied to the other surface 2B excluding the respective lands 4 (FIG. 7A). Then, one surface 2 of the multilayer wiring board 2
The solder bumps 5A are respectively formed by heating and melting the solders 5 printed corresponding to the lands 3 of A (FIG. 7B).
【０００５】この後、多層配線基板２の他面２Ｂに形成
された各ランド４に対応してそれぞれはんだバンプ７を
印刷した後、当該他面２Ｂ全体を覆うようにフラツクス
８を塗布する（図７（Ｃ））。この状態において、多層
配線基板２の他面２Ｂの各はんだバンプ７に位置合わせ
してＩＣチツプ９及び他の電子部品（コンデンサ又は抵
抗等）１０をマウントした後、リフロー炉（図示せず）
内において約 220〜 230〔℃〕でリフローすることによ
りフラツクス８を洗浄する（図７（Ｄ））。After that, solder bumps 7 are printed corresponding to the respective lands 4 formed on the other surface 2B of the multilayer wiring board 2, and then a flux 8 is applied so as to cover the entire other surface 2B (FIG. 7 (C)). In this state, the IC chip 9 and other electronic components (capacitors or resistors) 10 are mounted by aligning with the solder bumps 7 on the other surface 2B of the multilayer wiring board 2 and then a reflow furnace (not shown).
The flask 8 is washed by reflowing at about 220 to 230 [° C.] inside (FIG. 7 (D)).
【０００６】ここで、ＩＣチツプ９の実装面９Ａには外
部接続用の金属（例えば高温はんだでなる) バンプ１１
が形成され、当該金属バンプ１１に対応して多層配線基
板２の他面２Ｂにランド４及びはんだバンプ７が形成さ
れている。これにより、ＩＣチツプ９をマウントした状
態でリフローした場合、ＩＣチツプ９の金属バンプ１１
は、溶融したはんだバンプ７を介してランド４と電気的
に接続される。この後、ＩＣチツプ９を樹脂１２で封止
することにより、マルチチツプモジユール１が製造され
る（図７（Ｅ））。On the mounting surface 9A of the IC chip 9, bumps 11 for external connection metal (made of high temperature solder, for example) are used.
And the lands 4 and the solder bumps 7 are formed on the other surface 2B of the multilayer wiring board 2 corresponding to the metal bumps 11. As a result, when the IC chip 9 is mounted and reflowed, the metal bumps 11 of the IC chip 9 are
Are electrically connected to the lands 4 via the molten solder bumps 7. After that, the IC chip 9 is sealed with the resin 12 to manufacture the multi-chip module 1 (FIG. 7E).
【０００７】[0007]
【発明が解決しようとする課題】ところが、このような
マルチチツプモジユール１の製造工程においては、ＩＣ
チツプ９の実装面９Ａに形成された各金属バンプ１１
と、多層配線基板２の他面２Ｂに形成された各ランド４
との接続が、それぞれはんだバンプ７を介して接合され
ることから、各ランド４間のピツチが非常に短い場合
（約 150〔μｍ〕以下）にはブリツジが生じるおそれが
あり、フアインピツチでの実装が困難となる問題があつ
た。However, in the manufacturing process of such a multi-chip module 1, the IC
Each metal bump 11 formed on the mounting surface 9A of the chip 9
And each land 4 formed on the other surface 2B of the multilayer wiring board 2.
Since the connection with each is connected via the solder bumps 7, if the pitch between the lands 4 is very short (about 150 [μm] or less), there is a risk of bridging and mounting with the fine pitch. There was a problem that made it difficult.
【０００８】またフアインピツチ化に対応すべく、各は
んだバンプ７の大きさを縮小すると、当該各はんだバン
プ７が熱疲労に対して弱いため熱膨張係数の差によつて
クラツクが生じるおそれがあつた。さらに各はんだバン
プ７の形成時におけるリードタイム（例えばバリアメタ
ル等の形成工程）が長いため、各はんだバンプ７を形成
するまでに非常に時間がかかるという煩雑さがあつた。
さらにフラツクス８を洗浄する工程が必要となると共
に、その洗剤として有機溶剤を用いる必要があつた。When the size of each solder bump 7 is reduced in order to cope with the fine pitch, the solder bumps 7 are vulnerable to thermal fatigue, which may cause cracking due to the difference in thermal expansion coefficient. . Further, since the lead time (for example, the step of forming a barrier metal or the like) at the time of forming each solder bump 7 is long, it takes much time to form each solder bump 7.
Further, a step of washing the flux 8 is required, and it is necessary to use an organic solvent as the detergent.
【０００９】本発明は以上の点を考慮してなされたもの
で、簡易な構成でかつ比較的短時間で高密度実装を実現
し得る半導体装置及びその製造方法を提案しようとする
ものである。The present invention has been made in view of the above points, and an object thereof is to propose a semiconductor device which has a simple structure and can realize high-density mounting in a relatively short time, and a manufacturing method thereof.
【００１０】[0010]
【課題を解決するための手段】かかる課題を解決するた
め本発明においては、基板の一面上に当該一面に形成さ
れた所定の電極パターンに対応して複数の電子部品が実
装されると共に、基板の他面に電極パターンと導通接続
された外部接続用の端子がそれぞれ形成されてなる半導
体装置において、電子部品のうち少なくとも半導体チツ
プは、基板の一面に異方性導電膜を介して実装されてお
り、異方性導電膜は、基板の一面における各半導体チツ
プ以外の各電子部品の実装位置が開口されてなる。In order to solve such a problem, according to the present invention, a plurality of electronic components are mounted on one surface of a substrate in correspondence with a predetermined electrode pattern formed on the one surface, In a semiconductor device in which terminals for external connection, which are conductively connected to the electrode pattern, are formed on the other surface, at least a semiconductor chip among electronic components is mounted on one surface of the substrate via an anisotropic conductive film. The anisotropic conductive film is formed by opening the mounting position of each electronic component other than each semiconductor chip on one surface of the substrate.
【００１１】また本発明においては、基板の一面上に当
該一面に形成された所定の電極パターンに対応して複数
の電子部品が実装されると共に、基板の他面に電極パタ
ーンと導通接続された外部接続用の端子がそれぞれ形成
されてなる半導体装置の製造方法において、電子部品の
うち少なくとも半導体チツプの実装位置を覆うように異
方性導電膜を被着すると共に、当該各半導体チツプ以外
の各電子部品に対応する電極パターンにそれぞれ導電性
接着剤を塗布し又は金属バンプを形成する第１の工程
と、各半導体チツプ以外の各電子部品を基板の一面上に
位置決めした状態で、導電性接着剤又は金属バンプを加
熱すると同時に異方性導電膜を加熱する第２の工程とを
設けるようにした。Further, in the present invention, a plurality of electronic components are mounted on one surface of the substrate so as to correspond to a predetermined electrode pattern formed on the one surface, and electrically connected to the electrode pattern on the other surface of the substrate. In a method of manufacturing a semiconductor device in which terminals for external connection are respectively formed, an anisotropic conductive film is deposited so as to cover at least a mounting position of a semiconductor chip in an electronic component, and each of the semiconductor chips other than the semiconductor chip is covered. The first step of applying a conductive adhesive or forming a metal bump to the electrode pattern corresponding to the electronic component, and the conductive bonding in the state where each electronic component other than each semiconductor chip is positioned on one surface of the substrate. The second step of heating the anisotropic conductive film at the same time as heating the agent or the metal bump is provided.
【００１２】このように複数の電子部品と対応する各電
極パターンに異方性導電膜を被着し、当該異方性導電膜
上からそれぞれ電子部品をマウントするようにしたこと
により、各電極パターンのピツチの長短にかかわらず、
各電子部品を対応する電極パターンのそれぞれに導通接
続することができる。これに加えて、異方性導電膜にお
ける各半導体チツプ以外の各電子部品の実装位置に開口
を設けて、当該開口を介して各電子部品を露出させるよ
うにしたことにより、異方性導電膜を半導体チツプの数
だけ当該各半導体チツプの外形に応じて形成するといつ
た煩雑さを回避し得、この結果、半導体装置の製造時間
を格段と短縮することができる。As described above, by depositing an anisotropic conductive film on each electrode pattern corresponding to a plurality of electronic components and mounting the electronic component on each anisotropic conductive film, each electrode pattern is formed. Regardless of the pitch of the
Each electronic component can be conductively connected to each corresponding electrode pattern. In addition to this, an opening is provided at a mounting position of each electronic component other than each semiconductor chip in the anisotropic conductive film, and each electronic component is exposed through the opening. If the number of semiconductor chips is formed according to the outer shape of each semiconductor chip, the complexity can be avoided, and as a result, the manufacturing time of the semiconductor device can be significantly shortened.
【００１３】[0013]
【発明の実施の形態】以下図面について、本発明の一実
施例を詳述する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings.
【００１４】（１）第１実施例
図７（Ｅ）との対応部分に同一符号を付して示す図１
（Ａ）及び（Ｂ）において、第１実施例による半導体装
置としてのマルチチツプモジユール２０を示す。このマ
ルチチツプモジユール２０には、多層配線基板２の他面
２Ｂにおける各ＩＣチツプ９の実装位置に対応してそれ
ぞれ異方性導電膜２１が各ランド４を覆うように所定の
膜厚で形成され、当該各異方性導電膜２１を介してそれ
ぞれＩＣチツプ９が接続されている。(1) First Embodiment FIG. 1 in which parts corresponding to those in FIG.
1A and 1B show a multi-chip module 20 as a semiconductor device according to the first embodiment. An anisotropic conductive film 21 is formed on the multi-chip module 20 with a predetermined film thickness so as to cover each land 4 in correspondence with the mounting position of each IC chip 9 on the other surface 2B of the multilayer wiring board 2. The IC chips 9 are connected to each other through the anisotropic conductive films 21.
【００１５】これら各異方性導電膜２１は、所定の割合
で微細な導電粒子が混入されたエポキシ樹脂等の樹脂及
び溶剤でなる異方性導電接着剤を例えばドクタブレード
法により１枚のフイルム状でなる異方性導電膜を形成し
た後、この異方性導電膜をそれぞれ対応するＩＣチツプ
９の外形より若干大きい程度に切断加工することにより
形成される。Each of the anisotropic conductive films 21 is made of a film of an anisotropic conductive adhesive composed of a resin such as an epoxy resin mixed with fine conductive particles at a predetermined ratio and a solvent, for example, by a doctor blade method. After forming the anisotropic conductive film having a shape, the anisotropic conductive film is cut to a size slightly larger than the outer shape of the corresponding IC chip 9.
【００１６】実際上、図７（Ａ）〜（Ｅ）との対応部分
に同一符号を付して示す図２（Ａ）〜（Ｅ）において、
マルチチツプモジユール２０の製造方法を示す。まず１
枚の多層配線基板２の一面２Ａ及び他面２Ｂにそれぞれ
所定パターンでランド３及び４を形成した後、当該一面
２Ａ側に形成された各ランド３に対応してそれぞれペー
スト状のはんだ５を印刷する（図２（Ａ））。続いて多
層配線基板２の一面２Ａの各ランド３に対応して印刷さ
れた各はんだ５を加熱溶融することにより、それぞれは
んだバンプ５Ａを形成する（図２（Ｂ））。2A to 2E in which parts corresponding to those in FIGS. 7A to 7E are given the same reference numerals in practice.
A method of manufacturing the multi-chip module 20 will be described. First 1
After the lands 3 and 4 are formed on the one surface 2A and the other surface 2B of the multi-layered wiring board 2 in a predetermined pattern, respectively, paste solder 5 is printed corresponding to each land 3 formed on the one surface 2A side. (FIG. 2 (A)). Subsequently, the solder bumps 5A are formed by heating and melting each solder 5 printed corresponding to each land 3 on the one surface 2A of the multilayer wiring board 2 (FIG. 2B).
【００１７】この後、多層配線基板２の他面２Ｂにおけ
るＩＣチツプ９の実装位置に相当する各ランド４には、
当該各ランド４を覆うように所定の膜厚でなる異方性導
電膜２１を形成する（張り合わせ又は印刷する）と共
に、この他面２ＢにおけるＩＣチツプ９を除く他の電子
部品（コンデンサ又は抵抗等）１０の実装位置に相当す
る各ランド４には、当該各ランド４に対応してそれぞれ
はんだバンプ７を印刷する（図２（Ｃ））。Thereafter, each land 4 corresponding to the mounting position of the IC chip 9 on the other surface 2B of the multilayer wiring board 2 is
An anisotropic conductive film 21 having a predetermined film thickness is formed (laminating or printing) so as to cover the respective lands 4, and at the same time, other electronic parts (capacitors or resistors, etc.) other than the IC chip 9 on the other surface 2B are formed. ) Solder bumps 7 are printed on the lands 4 corresponding to the mounting positions of 10) corresponding to the lands 4 (FIG. 2C).
【００１８】この状態において、多層配線基板２の他面
２Ｂにおける所定の各ランド４に位置合わせしてＩＣチ
ツプ９をマウントした後、各異方性導電膜２１を高温及
び高圧という条件（ 180〜 230〔℃〕及び５〜10〔kg/c
m2〕）下で熱圧着することにより、各ランド４を当該異
方性導電膜２１内の導電粒子（図示せず）を介してＩＣ
チツプ９の各金属バンプ１１と接合させる（図２
（Ｄ））。続いて、多層配線基板２の他面２Ｂにおける
各はんだバンプ７に位置合わせして他の電子部品１０を
マウントした後リフローする（図２（Ｅ））。In this state, after the IC chip 9 is mounted by aligning with the predetermined lands 4 on the other surface 2B of the multilayer wiring board 2, each anisotropic conductive film 21 is subjected to high temperature and high pressure conditions (180- 230 [℃] and 5-10 [kg / c
m 2 ]) by thermocompression bonding, the respective lands 4 are exposed to the IC through the conductive particles (not shown) in the anisotropic conductive film 21.
Bonding to each metal bump 11 of the chip 9 (FIG. 2)
(D)). Subsequently, the other electronic component 10 is mounted by aligning with each solder bump 7 on the other surface 2B of the multilayer wiring board 2 and then reflowed (FIG. 2 (E)).
【００１９】以上の構成において、マルチチツプモジユ
ール２０を製造するにあたつて、多層配線基板２の他面
２ＢにＩＣチツプ９を実装する際、当該ＩＣチツプ９側
に形成された各金属バンプ１１と他面２Ｂ側に形成され
た各ランド４との間にそれぞれ異方性導電膜２１を介挿
するようにしたことにより、当該各異方性導電膜２１内
の導電粒子が非常に小さいことから、各ランド４間のピ
ツチの長短にかかわらず、ＩＣチツプ９の各金属バンプ
１１をそれぞれ異方性導電膜２１を介して対応するラン
ド４とのみ電気的に接続することができる。In manufacturing the multi-chip module 20 having the above-mentioned structure, when the IC chip 9 is mounted on the other surface 2B of the multilayer wiring board 2, each metal bump formed on the IC chip 9 side. Since the anisotropic conductive film 21 is interposed between each of the lands 11 formed on the side of the other surface 2B and the anisotropic conductive film 21, conductive particles in each anisotropic conductive film 21 are very small. Therefore, each metal bump 11 of the IC chip 9 can be electrically connected only to the corresponding land 4 through the anisotropic conductive film 21 regardless of the length of the pitch between the lands 4.
【００２０】また、各異方性導電膜２１を設けるように
したことにより、従来のようにＩＣチツプ９の各金属バ
ンプ１１と各ランド４との間にそれぞれはんだバンプ７
（図７（Ｅ））を介して接合する場合と比較して、各は
んだバンプ７を形成するほど時間がかからなくて済み、
全体として製造工程にかかる時間を格段と短縮すること
ができる。さらに従来のようにフラツクス８を洗浄する
工程が必要とならなくて済み、有機溶剤を用いないこと
から、耐環境性における問題を解決することができる。Further, since the anisotropic conductive films 21 are provided, the solder bumps 7 are respectively provided between the metal bumps 11 of the IC chip 9 and the lands 4 as in the conventional case.
(Compared with the case of joining via (FIG. 7 (E)), it does not take much time to form each solder bump 7,
As a whole, the time required for the manufacturing process can be significantly shortened. Further, unlike the conventional case, the step of cleaning the flux 8 is not required, and since no organic solvent is used, the problem in environmental resistance can be solved.
【００２１】以上の構成によれば、ＩＣチツプ９側に形
成された各金属バンプ１１と多層配線基板２の他面２Ｂ
側に形成された対応する各ランド４との間に、それぞれ
異方性導電膜２１を挟んで設けるようにしたことによ
り、簡易な構成でかつ比較的短時間で高密度実装された
マルチチツプモジユール２０を実現することができる。According to the above structure, each metal bump 11 formed on the IC chip 9 side and the other surface 2B of the multilayer wiring board 2 are formed.
Since the anisotropic conductive film 21 is provided between each of the corresponding lands 4 formed on the side, the multi-chip module which has a simple structure and is densely mounted in a relatively short time is provided. Yule 20 can be realized.
【００２２】（２）第２実施例
図１（Ａ）及び（Ｂ）との対応部分に同一符号を付して
示す図３（Ａ）及び（Ｂ）において、マルチチツプモジ
ユール３０は、第１実施例のマルチチツプモジユール２
０と異なり、多層配線基板２の他面２Ｂの全体に亘つて
所定の膜厚でなる１枚の異方性導電膜３１が形成されて
いる。この異方性導電膜３１における所定数の電子部品
１０の各実装部分には、それぞれ電子部品１０の実装位
置に対応して所定の大きさでなる切欠き３１Ａが形成さ
れている。(2) Second Embodiment In FIGS. 3A and 3B in which parts corresponding to those in FIGS. 1A and 1B are designated by the same reference numerals, the multichip module 30 is Multichip module 2 of one embodiment
Unlike 0, one anisotropic conductive film 31 having a predetermined film thickness is formed over the entire other surface 2B of the multilayer wiring board 2. A notch 31A having a predetermined size is formed in each mounting portion of the predetermined number of electronic components 10 in the anisotropic conductive film 31, corresponding to the mounting position of the electronic component 10.
【００２３】この場合、多層配線基板２の他面２Ｂにお
ける各電子部品１０の実装位置に相当する各ランド４
は、それぞれ異方性導電膜３１の切欠き３１Ａを介して
露出しており、当該各ランド４に対応してそれぞれはん
だバンプ７が形成されている。なお第２実施例における
マルチチツプモジユール３０の製造方法は、図２（Ａ）
〜（Ｅ）に示す第１実施例の場合とほぼ同様である。In this case, each land 4 corresponding to the mounting position of each electronic component 10 on the other surface 2B of the multilayer wiring board 2.
Are exposed through the notches 31A of the anisotropic conductive film 31, and the solder bumps 7 are formed corresponding to the respective lands 4. The manufacturing method of the multi-chip module 30 in the second embodiment is shown in FIG.
This is almost the same as the case of the first embodiment shown in FIGS.
【００２４】以上の構成によれば、多層配線基板２の他
面２Ｂのほぼ全体に亘つて異方性導電膜３１を積層形成
し、ＩＣチツプ９側に形成された各金属バンプ１１と多
層配線基板２の他面２Ｂ側に形成された対応する各ラン
ド４とを異方性導電膜３１を介して導通接続するように
したことにより、簡易な構成でかつ比較的短時間で高密
度実装されたマルチチツプモジユール３０を実現するこ
とができる。According to the above structure, the anisotropic conductive film 31 is laminated and formed on the other surface 2B of the multilayer wiring board 2 almost entirely, and the metal bumps 11 and the multilayer wiring formed on the IC chip 9 side. Since the corresponding lands 4 formed on the other surface 2B of the substrate 2 are electrically connected to each other through the anisotropic conductive film 31, a high density mounting can be achieved with a simple structure in a relatively short time. The multi-chip module 30 can be realized.
【００２５】また異方性導電膜３１を所定数の切欠き３
１Ａが形成された１枚のフイルム状のものを用いるよう
にしたことにより、第１実施例の場合のように、異方性
導電膜２１を所定数のＩＣチツプ９の数だけ当該各ＩＣ
チツプ９の外形に応じて形成するといつた煩雑さを回避
し得、かくしてマルチチツプモジユール３０の製造時間
を格段と短縮することができる。Further, the anisotropic conductive film 31 is provided with a predetermined number of notches 3
By using the one film-shaped one on which 1A is formed, as in the case of the first embodiment, as many anisotropic conductive films 21 as the IC chips 9 of a predetermined number are provided.
If it is formed according to the outer shape of the chip 9, the complexity can be avoided, and thus the manufacturing time of the multi-chip module 30 can be significantly shortened.
【００２６】（３）第３実施例
図３（Ａ）及び（Ｂ）との対応部分に同一符号を付して
示す図４（Ａ）及び（Ｂ）において、第３実施例による
マルチチツプモジユール４０は、第２実施例のマルチチ
ツプモジユール３０とほぼ同様に、多層配線基板２の他
面２Ｂの全体に亘つて所定の膜厚でなる１枚の異方性導
電膜４１が形成されている。(3) Third Embodiment In FIGS. 4 (A) and 4 (B) in which parts corresponding to those in FIGS. 3 (A) and 3 (B) are denoted by the same reference numerals, the multichip module according to the third embodiment is used. The Yule 40 is formed with one anisotropic conductive film 41 having a predetermined film thickness over the entire other surface 2B of the multilayer wiring board 2 in substantially the same manner as the multi-chip module 30 of the second embodiment. ing.
【００２７】この場合、マルチチツプモジユール４０
は、第２実施例とは異なり、異方性導電膜４１における
所定数の電子部品１０の各実装部分には切欠きが形成さ
れておらず、また多層配線基板２の他面２Ｂに形成され
た各ランド４にははんだバンプが形成されていない。従
つて、ＩＣチツプ９以外の他の電子部品１０をも異方性
導電膜４１を介して対応する各ランド４と導通接続させ
ることができ、この結果、各ランド４に対応してそれぞ
れはんだバンプを形成する必要がなくて済む。In this case, the multichip module 40
Unlike the second embodiment, the notch is not formed in each mounting portion of the predetermined number of electronic components 10 in the anisotropic conductive film 41, and it is formed on the other surface 2B of the multilayer wiring board 2. Solder bumps are not formed on each land 4. Therefore, the electronic component 10 other than the IC chip 9 can be conductively connected to the corresponding lands 4 through the anisotropic conductive film 41. As a result, the solder bumps corresponding to the respective lands 4 can be formed. Need not be formed.
【００２８】なお第３実施例におけるマルチチツプモジ
ユール４０の製造方法は、図２（Ａ）〜（Ｅ）に示す第
１実施例の場合とほぼ同様でなる。すなわちまず１枚の
多層配線基板２の一面２Ａ及び他面２Ｂにそれぞれ所定
パターンでランド３及び４を形成した後、当該一面２Ａ
側に形成された各ランド３に対応してそれぞれペースト
状のはんだ５を印刷する（図５（Ａ））。続いて多層配
線基板２の一面２Ａの各ランド３に対応して印刷された
各はんだ５を加熱溶融することにより、それぞれはんだ
バンプ５Ａを形成する（図５（Ｂ））。The manufacturing method of the multi-chip module 40 in the third embodiment is almost the same as that of the first embodiment shown in FIGS. 2 (A) to 2 (E). That is, first, lands 3 and 4 are formed in a predetermined pattern on one surface 2A and the other surface 2B of one multilayer wiring board 2, respectively, and then the one surface 2A is formed.
The paste-like solder 5 is printed corresponding to each land 3 formed on the side (FIG. 5A). Subsequently, the solder bumps 5A are formed by heating and melting the solders 5 printed corresponding to the lands 3 on the one surface 2A of the multilayer wiring board 2 (FIG. 5B).
【００２９】この後、多層配線基板２の他面２Ｂの全体
に亘つて所定の膜厚でなる１枚の異方性導電膜３１を各
ランド４を覆うように形成した後（図５（Ｃ））、多層
配線基板２の他面２Ｂにおける所定の各ランド４に位置
合わせして各ＩＣチツプ９及び各電子部品１０をそれぞ
れマウントする（図５（Ｄ）。After that, one anisotropic conductive film 31 having a predetermined film thickness is formed over the entire other surface 2B of the multilayer wiring board 2 so as to cover each land 4 (see FIG. )), Each IC chip 9 and each electronic component 10 are mounted by aligning with each predetermined land 4 on the other surface 2B of the multilayer wiring board 2 (FIG. 5D).
【００３０】この状態において、異方性導電膜３１を高
温及び高圧という条件（ 180〜 230〔℃〕及び５〜10
〔kg/cm2〕）下で熱圧着することにより、各ランド４を
当該異方性導電膜２１内の導電粒子（図示せず）を介し
て、各ＩＣチツプ９の各金属バンプ１１及び各電子部品
１０の各電極端子（図示せず）とそれぞれ接合させる
（図５（Ｅ））。In this state, the anisotropic conductive film 31 is subjected to high temperature and high pressure conditions (180 to 230 [° C.] and 5 to 10).
[Kg / cm 2 ]) by thermocompression bonding, the respective lands 4 are connected via the conductive particles (not shown) in the anisotropic conductive film 21 to the metal bumps 11 and the respective metal bumps 11 of the respective IC chips 9. Each electrode terminal (not shown) of the electronic component 10 is bonded (FIG. 5E).
【００３１】以上の構成によれば、多層配線基板２の他
面２Ｂの全体に亘つて異方性導電膜３１を積層形成し、
ＩＣチツプ９側に形成された各金属バンプ１１と多層配
線基板２の他面２Ｂ側に形成された対応する各ランド４
とを異方性導電膜４１を介して導通接続すると共に、他
の電子部品１０側に形成された各電極端子（図示せず）
をも異方性導電膜４１を介して対応する各ランド４と導
通接続するようにしたことにより、多層配線基板２の他
面２Ｂに形成された各ランド４にはんだバンプを設ける
必要がなくて済み、かくして簡易な構成でかつ比較的短
時間で高密度実装されたマルチチツプモジユール３０を
実現することができる。According to the above construction, the anisotropic conductive film 31 is laminated and formed over the entire other surface 2B of the multilayer wiring board 2.
The metal bumps 11 formed on the IC chip 9 side and the corresponding lands 4 formed on the other surface 2B side of the multilayer wiring board 2.
Are electrically connected to each other through the anisotropic conductive film 41, and each electrode terminal (not shown) formed on the other electronic component 10 side.
Also, by conducting the conductive connection with each corresponding land 4 through the anisotropic conductive film 41, it is not necessary to provide a solder bump on each land 4 formed on the other surface 2B of the multilayer wiring board 2. Thus, it is possible to realize the multi-chip module 30 having a simple structure and high-density packaging in a relatively short time.
【００３２】（４）他の実施例
なお上述の実施例においては、多層配線基板２の他面２
Ｂに異方性導電膜２１（３１、４１）を介して所定数の
ＩＣチツプ９及び所定数の電子部品１０を実装した場合
について述べたが、本発明はこれに加えて、当該他面２
Ｂの全面に例えばシリコン系樹脂及びガラスエポキシ系
樹脂等を塗布することにより、当該他面２Ｂをオーバー
コートするようにしても良い。すなわち図６に示すマル
チチツプモジユール６０のように、例えば第２実施例の
マルチチツプモジユール３０において、各ＩＣチツプ９
及び各電子部品１０を実装した後、当該各ＩＣチツプ９
及び各電子部品１０並びに異方性導電膜３１を覆うよう
に、多層配線基板２の他面２Ｂの全面に樹脂６１を塗布
してオーバーコートするようにしても良い。(4) Other Embodiments In the above embodiment, the other surface 2 of the multilayer wiring board 2 is used.
The case where a predetermined number of IC chips 9 and a predetermined number of electronic components 10 are mounted on B via the anisotropic conductive films 21 (31, 41) has been described.
The other surface 2B may be overcoated by applying, for example, a silicon resin and a glass epoxy resin on the entire surface of B. That is, like the multi-chip module 60 shown in FIG. 6, for example, in the multi-chip module 30 of the second embodiment, each IC chip 9 is used.
After mounting each electronic component 10, each IC chip 9
Further, the resin 61 may be applied to the entire other surface 2B of the multilayer wiring board 2 so as to cover each electronic component 10 and the anisotropic conductive film 31 and be overcoated.
【００３３】また第１及び第２実施例においては、多層
配線基板２の他面２ＢにＩＣチツプ９以外の他の電子部
品１０をマウントする場合には、当該他面２Ｂに形成さ
れた各ランド３にはんだバンプ７を印刷する場合につい
て述べたが、本発明はこれに限らず、はんだバンプ７以
外にも種々の金属バンプを印刷しても良く、さらには金
属バンプに代えて導電性接着剤（図示せず）を形成する
ようにしても良い。なお、導電性接着剤を形成する場合
には、対応するランド４に載置した後、例えば 150
〔℃〕かつ30〔min 〕で加熱硬化させれば良い。Further, in the first and second embodiments, when the electronic component 10 other than the IC chip 9 is mounted on the other surface 2B of the multilayer wiring board 2, each land formed on the other surface 2B is mounted. Although the case where the solder bumps 7 are printed on 3 is described above, the present invention is not limited to this, various metal bumps other than the solder bumps 7 may be printed, and a conductive adhesive may be used instead of the metal bumps. (Not shown) may be formed. When a conductive adhesive is formed, it is placed on the corresponding land 4 and then, for example, 150
It may be cured by heating at [° C] and 30 [min].
【００３４】さらに上述の実施例においては、多層配線
基板２の一面２Ａに形成された各ランド３にそれぞれペ
ースト状のはんだ５を印刷してはんだバンプ５Ａを形成
した場合について述べたが、本発明はこれに限らず、球
状はんだを載置してリフローすることによつてはんだバ
ンプ（図示せず）を形成し、いわゆるＢＧＡ（Ball Gri
d Array ）を構成するようにしても良い。また各ランド
３には何も形成することなく、いわゆるＬＧＡ（Land G
rid Array ）を構成するようにしても良い。Further, in the above-described embodiment, the case where the paste-like solder 5 is printed on each land 3 formed on the one surface 2A of the multilayer wiring board 2 to form the solder bumps 5A has been described. Is not limited to this, a solder bump (not shown) is formed by placing a spherical solder and reflowing, so-called BGA (Ball Gri).
d Array) may be configured. Moreover, so-called LGA (Land G) is not formed on each land 3.
rid Array) may be configured.
【００３５】[0035]
【発明の効果】上述のように本発明によれば、基板の一
面上に当該一面に形成された所定の電極パターンに対応
して複数の電子部品が実装されると共に、基板の他面に
電極パターンと導通接続された外部接続用の端子がそれ
ぞれ形成されてなる半導体装置及びその製造方法におい
て、電子部品のうち少なくとも半導体チツプの実装位置
を覆うように異方性導電膜を被着すると共に、当該各半
導体チツプ以外の各電子部品に対応する電極パターンに
それぞれ導電性接着剤を塗布し又は金属バンプを形成し
ておき、各半導体チツプ以外の各電子部品を基板の一面
上に位置決めした状態で、導電性接着剤又は金属バンプ
を加熱すると同時に異方性導電膜を加熱するようにした
ことにより、各電極パターンのピツチの長短にかかわら
ず、各電子部品を対応する電極パターンのそれぞれに導
通接続することができると共に、異方性導電膜を半導体
チツプの数だけ当該各半導体チツプの外形に応じて形成
するといつた煩雑さを回避することができ、かくして簡
易な構成でかつ比較的短時間で高密度実装し得る半導体
装置及びその製造方法を実現できる。As described above, according to the present invention, a plurality of electronic components are mounted on one surface of a substrate corresponding to a predetermined electrode pattern formed on the one surface, and electrodes are mounted on the other surface of the substrate. In a semiconductor device and a manufacturing method thereof in which terminals for external connection electrically connected to a pattern are formed, an anisotropic conductive film is deposited so as to cover at least a mounting position of a semiconductor chip among electronic components, In a state in which each of the electronic components other than the semiconductor chips is positioned on one surface of the substrate by applying a conductive adhesive or forming a metal bump on the electrode pattern corresponding to each electronic component other than the semiconductor chips. By heating the conductive adhesive or the metal bump at the same time as heating the anisotropic conductive film, each electronic component can be heated regardless of the pitch of each electrode pattern. It is possible to make conductive connection to each of the corresponding electrode patterns and to avoid complexity by forming anisotropic conductive films according to the outer shape of each semiconductor chip by the number of semiconductor chips. It is possible to realize a semiconductor device having a simple structure and capable of high-density mounting in a relatively short time, and a manufacturing method thereof.
【図１】第１実施例によるマルチチツプモジユールの構
成を示す略線図及び部分的断面図である。FIG. 1 is a schematic diagram and a partial sectional view showing a structure of a multi-chip module according to a first embodiment.
【図２】第１実施例によるマルチチツプモジユールの製
造工程の説明に供する部分的断面図である。FIG. 2 is a partial sectional view for explaining a manufacturing process of the multi-chip module according to the first embodiment.
【図３】第２実施例によるマルチチツプモジユールの構
成を示す略線図及び部分的断面図である。FIG. 3 is a schematic diagram and a partial sectional view showing the structure of a multi-chip module according to a second embodiment.
【図４】第３実施例によるマルチチツプモジユールの構
成を示す略線図及び部分的断面図である。FIG. 4 is a schematic diagram and a partial sectional view showing a structure of a multi-chip module according to a third embodiment.
【図５】第３実施例によるマルチチツプモジユールの製
造工程の説明に供する部分的断面図である。FIG. 5 is a partial cross-sectional view for explaining the manufacturing process of the multi-chip module according to the third embodiment.
【図６】他の実施例によるマルチチツプモジユールの構
成を示す部分的断面図である。FIG. 6 is a partial sectional view showing a structure of a multi-chip module according to another embodiment.
【図７】従来のマルチチツプモジユールの構成を示す部
分的断面図である。FIG. 7 is a partial cross-sectional view showing the structure of a conventional multi-chip module.
１、２０、３０、４０……マルチチツプモジユール、２
……多層配線基板、２Ａ……一面、２Ｂ……他面、３、
４……ランド、５Ａ、７……はんだバンプ、９……ＩＣ
チツプ、１０……電子部品、１１……金属バンプ、３１
Ａ……切欠き。1, 20, 30, 40 ... Multichip module, 2
... Multi-layer wiring board, 2A ... One side, 2B ... Other side, 3,
4 ... Land, 5A, 7 ... Solder bump, 9 ... IC
Chip, 10 ... Electronic parts, 11 ... Metal bumps, 31
A: Notch.
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 25/00 - 25/18 ─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 25/00-25/18
Claims (2)
の電極パターンに対応して複数の電子部品が実装される
と共に、上記基板の他面に上記電極パターンと導通接続
された外部接続用の端子がそれぞれ形成されてなる半導
体装置において、 上記電子部品のうち少なくとも半導体チツプは、上記基
板の一面に異方性導電膜を介して実装されており、 上記異方性導電膜は、上記基板の一面における各上記半
導体チツプ以外の各上記電子部品の実装位置が開口され
てなる ことを特徴とする半導体装置。 1.Predetermined on one surface of the substrate
Multiple electronic components are mounted corresponding to the electrode pattern of
At the same time, conductively connects to the electrode pattern on the other surface of the substrate.
Semiconducting device, which has terminals for external connection
In the body device, At least the semiconductor chip among the above electronic components is the above-mentioned substrate.
It is mounted on one side of the board via an anisotropic conductive film, The anisotropic conductive film is formed on each surface of the substrate.
The mounting positions of the above electronic components other than the conductor chips are opened.
Become A semiconductor device characterized by the above.
の電極パターンに対応して複数の電子部品が実装される
と共に、上記基板の他面に上記電極パターンと導通接続
された外部接続用の端子がそれぞれ形成されてなる半導
体装置の製造方法において、 上記電子部品のうち少なくとも半導体チツプの実装位置
を覆うように異方性導電膜を被着すると共に、当該各半
導体チツプ以外の各上記電子部品に対応する上記電極パ
ターンにそれぞれ導電性接着剤を塗布し又は金属バンプ
を形成する第１の工程と、 各上記半導体チツプ以外の各上記電子部品を上記基板の
一面上に位置決めした状態で、上記導電性接着剤又は上
記金属バンプを加熱すると同時に上記異方性導電膜を加
熱する第２の工程と を具えることを特徴とする半導体装
置の製造方法。 2.Predetermined on one surface of the substrate
Multiple electronic components are mounted corresponding to the electrode pattern of
At the same time, conductively connects to the electrode pattern on the other surface of the substrate.
Semiconducting device, which has terminals for external connection
In the method of manufacturing the body device, Mounting position of at least semiconductor chip among the above electronic parts
An anisotropic conductive film is applied so as to cover the
The electrode patterns corresponding to the above electronic components other than the conductor chip
Apply conductive adhesive to each turn or metal bump
A first step of forming Each of the electronic components other than the semiconductor chip is mounted on the substrate.
When positioned on one side, the conductive adhesive or the above
At the same time as heating the metal bump, the anisotropic conductive film is added.
With the second step of heating Semiconductor device characterized by comprising
Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21790896A JP3465809B2 (en) | 1996-07-31 | 1996-07-31 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21790896A JP3465809B2 (en) | 1996-07-31 | 1996-07-31 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1050931A JPH1050931A (en) | 1998-02-20 |
| JP3465809B2 true JP3465809B2 (en) | 2003-11-10 |
Family
ID=16711643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21790896A Expired - Fee Related JP3465809B2 (en) | 1996-07-31 | 1996-07-31 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3465809B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69938582T2 (en) * | 1998-09-09 | 2009-06-04 | Seiko Epson Corp. | SEMICONDUCTOR ELEMENT, ITS MANUFACTURE, PCB AND ELECTRONIC APPARATUS |
-
1996
- 1996-07-31 JP JP21790896A patent/JP3465809B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH1050931A (en) | 1998-02-20 |
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