JPH0770677B2 - Module mounting structure - Google Patents

Abstract

PURPOSE:To make possible the highly reliable connection of a 10-mm square chip to a multilayered substrate having a thermal expansion coefficient comparable to that of Al2O3 by a method wherein the gap between the semiconductor chip and the surface of a carrier substrate is filled with a resin, whose thermal expansion coefficient is close to that of a solder. CONSTITUTION:A high-output (20W/chip or more) large-sized chip (the level of a 10-mm square) is formed in a face down structure) wherein the rear of the chip can be liquid cooled, and a resin 3 of a specified composition is filled in the gap between a carrier substrate 2 having the same thermal expansion coefficient as that of a multilayered substrate 7 and the chip 1. Accordingly, a shear stress which is applied to solder bumps is reduced and moreover, the chip is formed into a carrier, a resistor for characteristic impedance matching or a capacitor is incorporated and an increase in the integration of the chip can be contrived. Thereby, a highly reliable structure, which has a superior repair property and is at a level to satisfy 10-15 years being regarded as the requirement longevity of a computer, can be made possible for the large- sized chip.

Description

The present invention relates to a high-density module mounting structure of a logic LSI of a CPU of a novel ultra-large-sized computer.

[Conventional technology]

FIG. 2 shows a conventional example of a structure for cooling from the back surface of the chip in the flip chip structure. As described in JP-B-56-31743, the back surface of the chip is metalized and the cooling stud 10
It is a flip-chip mounting structure that is adhered to.

Although the cooling effect of this flip chip system is sufficient, when a large chip is used, the thermal fatigue life due to the difference in thermal expansion between the chip and the multilayer substrate poses a problem. For example, a 5 mm □ chip (the distance between the outermost solder bumps is 6.5 mm) is Al ₂ O ₃
Flip-chip connection to the board (6.8 × 10 ^-6 / ° C)
The limit is 1000∞ for a cycle of 55 to 150 ° C and 1∞ / h.
Therefore, a mounting method for connecting a large flip chip to a multilayer substrate with high reliability is required.

Along with the increase in capacity and speed of computers, the number of logic gates in the chip increases year by year, the wiring pitch becomes higher, and the output is large (10 mm □ level) and high output (20 W / chip or more).
Therefore, mounting with a terminating resistor and a capacitor has come to be required.

[Problems to be solved by the invention]

The above-mentioned prior art has a sufficient cooling effect as the flip chip system, but does not consider reducing the difference in thermal expansion between the chip and the multilayer substrate when a large chip is used, and has a short thermal fatigue life. There was a problem such as.

Further, in order to increase the speed and prevent noise such as signal reflection, there is a problem in high-density mounting of a resistor for characteristic impedance matching or a capacitor.

The object of the present invention is a structure in which a large chip with high output is face-down connected to a multilayer substrate, a method of directly or indirectly liquid cooling the back surface of the chip, and a characteristic impedance matching resistor or a large resistor for high speed. It is to provide a module mounting structure that is excellent in high-density mounting and high reliability (especially thermal fatigue resistance) and chip-preparation (removal, reconnection) by incorporating a capacitor that can be expected to achieve a high speed.

[Means for solving problems]

The present invention, high output (20W / chip or more) large chip (10mm
□ level), the back surface of the chip has a face-down structure that can be liquid-cooled, and the solder bumps are sheared by filling the gap between the carrier substrate and the chip, which has the same coefficient of thermal expansion as the multilayer substrate, with a resin of a specific composition. Reduced stress, made into a chip carrier, made high in density by incorporating a resistor or capacitor for characteristic impedance matching, excellent in repairability, and highly reliable at a level that satisfies the required life of the computer for 10 to 15 years. The structure can be made possible with large chips.

According to the present invention, a Si chip is soldered to a carrier substrate such as a ceramic by a flip chip connection method, a gap between the chip and the carrier substrate is filled with resin, and a terminal on the back side of the carrier substrate provided through a through-hole conductor of the carrier substrate. Is soldered to a multi-layered substrate, and the back surface of the chip is a module mounting structure in which it is air-cooled or liquid-cooled through a heat conductive medium such as metal or ceramics.

It is preferable that the resin has a coefficient of thermal expansion of ± 30% or less of the solder used. The resin preferably contains 30 to 60% by volume of quartz powder. Quartz powder is 100 mesh or less, preferably 10
μm or less. Similarly, the carrier substrate preferably has a coefficient of thermal expansion of ± 30% or less of the multilayer plate.

[Action]

The cause that made this life improvement possible is 1). In the conventional bare chip flip chip method, stress concentration was done at the outermost solder bumps, but by filling the resin with low expansion, the stress concentration on the solder bumps was alleviated,
Reducing stress 2). By adjusting the thermal expansion coefficient of the resin to that of the solder, the strain applied to the solder bumps was reduced 3). Dispersing fine-grained and spherical polybutadiene rubber in the resin has a stress relaxation action against thermal shock.

By using a carrier substrate having a large flexural rigidity with a coefficient of thermal expansion that is the same as that of the multilayer substrate, thermal stress that would cause a problem is not generated in the solder connection portion between the multilayer plate and the carrier substrate.

As a result, it was previously impossible to make a 10 mm square chip of Al.
It is possible to realize highly reliable connection to a multilayer substrate having a thermal expansion coefficient similar to that of ₂ O ₃ .

Epoxy resin or polyimide resin is used as the resin.

〔Example〕

FIG. 1 shows a module mounting structure using an embodiment of a semiconductor resin package structure according to the present invention, in which a Si chip 1 has a Si chip cooling plate on its back surface via a low temperature solder 11.
The cooling plate 12 connected to 12 is connected to the nickel bellows 8 and cooled by water 9. The electrode of the surface of the Si chip 1 is connected to the upper surface of the carrier substrate 2 by soldering (Pb-5% Sn), and the gap between the Si chip 1 and the carrier substrate 2 is made of resin 3
Filled with. The lower surface portion of the carrier board 2 electrically connected to the upper surface soldering portion of the carrier board 2 through the through-hole conductor 5 of the carrier board 2 is solder 6 (Pb
-60% Sn) to connect to the multilayer substrate 7, where it is connected to a predetermined printed circuit in the multilayer substrate 7. In the structure shown in FIG. 1, the Si chip 1 and the carrier substrate 2 are connected by solder 4 and filled with a resin 10 to form a semiconductor resin package structure. For the resin 3, refer to FIG. 3 and the like later. As described in detail, solder with a composition in which quartz powder is mixed with epoxy resin 3
It has the same coefficient of thermal expansion as. Al ₂ O ₃ is used for the multilayer substrate 7, and the carrier substrate 2 is assumed to have a coefficient of thermal expansion substantially equal to that of the multilayer substrate 7 such as Al ₂ O ₃ or mullite (Al ₂ O ₃ , SiO ₂ ) And so on. The composition of the solder 6 is different from the composition of the solder 4 and has a low melting point so that they can be alternately soldered.

The coefficient of thermal expansion of the resin 3 is set to be similar to that of the solder 4 to disperse the stress, and the coefficient of thermal expansion of the carrier substrate 9 is made substantially equal to that of the multilayer substrate 7 to cause a problem between the carrier substrate 2 and the multilayer substrate 7. The problem of thermal stress due to the difference in thermal expansion coefficient between the semiconductor chip 1 and the multilayer substrate 7 is solved by preventing the thermal stress to the extent that or,
At the same time, the semiconductor chip 1 together with the carrier substrate 2 can be easily re-soldered with the multilayer substrate 7 for each semiconductor chip, so that the semiconductor chip or an apparatus using the semiconductor chip can be easily inspected and maintained. It can be done economically.

In this embodiment, the multilayer substrate 7 has 30 layers of tungsten (W) conductor, and the surface conductor layer is made of tungsten (W).
It has a structure in which nickel (Ni) plating and gold (Au) coating are applied, the carrier substrate 2 has four layers, and the through-hole conductor 5 is plated with copper and then subjected to immersion soldering. Used. A SiO ₂ film is formed on the Al film on the surface of the semiconductor chip 1, and SiO ₂ is removed at the electrode portion, and Cr is 0.1% with Cr-CuAu.
A thin film of μm, Cu of 3 μm, and Au of 0.1 μm is used.

The back surface of the Si chip can be configured to be liquid-cooled directly or indirectly, and in addition to the structure shown in FIG. 1, it can be air-cooled or liquid-cooled through a heat transfer medium such as metal or ceramics. it can.

FIG. 3 shows the results of the temperature cycle acceleration test under the conditions of −55 to 150 ° C. and 1 h / ∞. (A) is 10 mm □ on Al ₂ O ₃ 7 substrate
Chip 1 soldered 3 structure (bare chip), (b)
After soldering the chip on the Al ₂ O ₃ carrier board 2,
This is a structure in which the resin 4 is filled in the gap between the chip and the carrier substrate and then mounted on the carrier substrate Al ₂ O ₃ multilayer substrate 7 with the low temperature solder 6.

(C) is the result of the acceleration test. The chip carrier structure has a 10 times longer life than the bare chip structure. The double value of this accelerated life is the operating life of the computer.
It is said that the level has been sufficient for 15 years.

In the structure (b), Al ₂ O ₃ was used for both the carrier substrate and the multi-layer substrate. However, by using as the carrier substrate, one having a thermal expansion coefficient that is close to or the same as the coefficient of thermal expansion of the multi-layer substrate, The solder joint portion 6 with the multilayer substrate has a structure in which thermal fatigue does not occur. At this time, the flexural rigidity of the carrier substrate needs to be higher than that of the Si chip, so that the carrier substrate does not warp and high reliability can be maintained.

The through-hole conductors 5 on the carrier substrate may be copper-plated and then dip-soldered, or a sintered sintered conductor such as W, Mo, or Cu, or a structure in which a pin material is embedded.

The main reason why the chip carrier structure has higher thermal fatigue resistance than the bare chip is based on the thermo-elasto-plastic analysis results by the finite element method1). The resin relaxes the stress concentration concentrated on a part of the solder bump 2). Matching the thermal expansion coefficient of the resin with that of the solder 3). It is considered that this is because the thermal shock of fine spherical polybutadiyun rubber dispersed in the resin is mitigated. Detailed description will be given below.

The resin composition used is as follows.

Epoxy resin 828 100 parts Polybutadiene (CTBN) 15 parts Dicyandiamide 10 parts Imidazole (2P4MHZ) 5 parts A-187 2 parts Quartz powder (EMC-Y40) 55vol% This resin has low expansion like solder, but fluidity Well, due to the effect of surface tension, it penetrates and fills the gap between the chip and the carrier substrate. Conventionally used Dual Inline Pack
Since the age resin is a molding and casting method in which pressure is applied, it is necessary to have good mold releasability from the mold. In addition, because of the chip face-up connection method, resin penetration does not become a big problem, and no special consideration is given to fluidity.

Therefore, the adhesiveness of the resin at the lead interface decreases,
Due to thermal shock, temperature cycle, etc., water is transmitted through the interface, corroding the Al conductor part on the chip surface and breaking the wire.

However, in the flip-chip structure using the above resin composition, due to the face-down connection method, it is necessary to use the surface tension effect to penetrate into the narrow gap of about 100 μm between the chip and the carrier substrate. (About 10 times that of the mold resin) and good adhesion to Si chips and carrier substrates. For this reason, the structure has a small amount of infiltration of water and excellent corrosion resistance.

When the temperature of the temperature cycle test condition is changed from 150 ° C to -55 ° C, the main stress distribution acting on the solder bumps on the outermost periphery, which receives the largest force, is the same as in the conventional flip chip structure (bare chip without resin). Stress concentration occurs at the boundary between the outside of the bump and the chip and the board, and cracking occurs in the solder, leading to disconnection. The magnitude of the principal stress appears remarkably depending on the location, and particularly large stress concentration is observed at the joint interface.

In the flip chip structure of the present invention filled with resin, the influence of the location of the main stress is small, and a state in which the stress is dispersed almost uniformly is observed. Further, no stress concentration is observed at the joint interface, and the magnitude of stress is smaller than that of the conventional structure.

From this, it is considered that the effect of the resin is that the stress concentration applied to the solder bump is relaxed and the stress is dispersed, thereby improving the thermal fatigue life.

As the next effect, as shown in FIG. 4, the ratio of the maximum principal stress acting on the outermost peripheral solder bump when the coefficient of thermal expansion of the resin of the resin-filled chip with respect to the conventional chip structure (without resin) is changed is shown. It is a thing.

It can be seen that the maximum principal stress applied to the solder is minimized at the position where the thermal expansion coefficient of the resin matches the Pb-5% Sn solder. It means that the maximum principal stress increases even if the coefficient of thermal expansion of the resin becomes smaller than that of the solder. However, the stress applied to the Si chip (element) naturally increases as much as the thermal expansion coefficient of the resin increases, so it is desirable that it is small for the Si chip, but with the same thermal expansion coefficient as the solder An example of a problem with
It is not an ine Package.

Incidentally, the selection of the resin composition is as described in detail in JP-A-60-63951.
5% Sn) and a resin adjusted to about 25 × 10 ⁻⁶ / ° C. was used. Making the coefficient of thermal expansion of the resin equal to that of the solder means that the solder bump itself is not constrained by the resin and stress concentration is reduced, so that the stress and strain applied to the solder itself are reduced. However, since stress and strain are applied to the Si element itself due to the difference in thermal expansion between the resin and Si,
It is desirable that the coefficient of thermal expansion be small, but it is not at a level that will hinder the device even if it is used in combination with solder.

As conditions for the resin for the carrier substrate, what is required other than lowering the thermal expansion coefficient of the resin to the level of solder is:
It is a fluidity that can penetrate into the gap between the chip and the carrier substrate without penetrating the barriers of the solder bumps distributed in the grid and creating a space inside.

If quartz powder or the like is added in order to lower the expansion of the epoxy resin, the fluidity will decrease (in order to obtain an expansion coefficient similar to that of solder, approximately 55 vol% must be added). Therefore, by dispersing spherical polybutadiene rubber having a diameter of 1 to 5 μm as a means for improving the fluidity, the fluidity could be suppressed from decreasing. In addition, polybutadiene rubber
If blended at 20% or more, the dispersion cannot be maintained and a part of the particles agglomerate, and polybutadiene itself has a large thermal expansion coefficient (80 × 10 ^-6 / ° C.), which has an adverse effect.

It is described in JP-A-60-63951 that if the blending ratio of polybutadiene is 20% or less, it has the effects of improving fluidity and mitigating thermal shock to improve thermal fatigue resistance.

This mechanism is used when sudden temperature changes occur (eg 15
From 0 ° C to room temperature → -55 ° C), the elastic action of this rubber has the effect of relieving shocking stress on the chip, substrate, solder, etc.

As the resin composition, the mixing ratio of the low expansion material quartz powder and the buffer material polybutadiene and the thermal fatigue life judgment (○: good,
Table 1 shows the relationship with (Δ: almost good, ×: bad).

The mixing ratio of quartz powder is limited to 60 to 65 volume% with respect to the entire resin. The mixing ratio of polybutadiene is limited to 20 parts by weight. Quartz powder is preferably 30 to 60% by volume, and polybutadiene is preferably 5 to 15 parts by weight.

About 1 to 2% of carbon black was added to the resin to be colored black for use.

The low expansion material other than quartz may be made of at least one of alumina silicon carbide, silicon nitride, aluminum nitride, calcium carbonate, and silicon carbide mixed with beryllium oxide. It is also possible to add highly heat-conducting diamond or BN to obtain a high heat-conducting resin.

As an elastic material other than polybutadiene, polyisoprene,
It is also possible that it consists of at least one of silicones. In particular, silicone rubber is excellent in heat resistance and temperature cycle resistance, so it is used when high reliability is required.

Regarding the shape of solder bumps, considering the life of solder bumps and resin penetration, the shape of solder bumps is
When the solder is melted, the gap between the chip and the carrier is lifted to form a staggered shape, which further increases reliability and improves workability of the resin.

FIG. 5 shows application examples of various package structures.

Therefore, the structure in which the connection to the cooling plate on the back surface of the chip and the connection to the multilayer substrate of the carrier substrate are omitted.

(A) is a structure in which the resin is adhered only to the lower surface of the chip. (B) is a structure in which the resin is adhered not only to the lower surface of the chip, but also to the side surface of the chip. By using a conductive resin, you can expect some heat conduction on the resin surface. (D) Solder (or bond) the back surface of the chip and a heat conductive plate of a size larger than the chip (eg, heat conductive insulating SiC). The structure which is effective in improving the heat transfer in the lateral direction to improve the thermal conductivity, and mechanically protecting the back surface of the chip and improving the moisture resistance (e) is the terminal pitch on the multilayer board side. If the carrier board is large, the carrier board has a pitch matching function. (F) is an example in which the connection terminals are arranged in the periphery, and the resin wraps the solder bumps, but the center part is hollow. . Since it was confirmed that the thermal cycle resistance is almost the same as that of the structure filled with resin, this type of structure is also effective.

(G) is a plan view of (f).

FIG. 6 is a cross-sectional view (c) of the package structure shown in FIGS. 6A and 6B when the package structure is mounted on a stud type multistage module structure. The upper stage is the (a) structural model, the lower stage is the (b) structural model, which is a structure in which each package is uniformly pressed by a pressure plate 19 via a spring by a heat conductive flat plate 18 for water cooling 17. The back surface of the chip of (a) structure and the cooling plate surface of (b) structure are in contact with the heat conductive flat plate for water cooling or adhered with a heat conductive grease, but there is no strong restraint between each package and the heat fatigue resistance is Has been secured.

The upper surface of each package was forcibly flattened during bonding because it was necessary to be flat.

FIG. 7 shows the pin lead type package structure of (a) and (b), and the mounting method similar to that of FIG. 6 is possible. The chip is
Not limited to Si, GaAs or functional elements include all mounted chips. The same applies to elements such as C and R.

FIG. 8 shows an example applied to a boiling cooling method of immersing in the Frona liquid. A stud 19 type fin is joined to the back of the chip. Since the chips can be mounted on both sides of the multi-layer board, it has an advantage over the water cooling method in terms of high density and easy cooling.

As the multilayer substrate 7, a ceramics substrate containing Al ₂ O ₃ or the like as a main component was used. The part where the fluorocarbon is bonded to the metal is the soldering part 6 necessary for chip replacement (the side surface of the Si chip is covered with the protective resin 21). As a result of the accelerated test of Pb-60% Sn solder corrosion, it is possible to guarantee 15 years under computer operating conditions, so cooling by this method in CFC liquid is possible.

The advantages of this method are high-density mounting and easy cooling.

FIG. 9 shows a high performance cooling system for a high power chip. The bottom surface of the chip contacts the Cu block fin 32, and the SiC cooling plate 12
Is transmitted to. In 29, Cu block fin is Si chip and Si
C A spring for contacting the cooling plate. The plane is a line catalyst,
When the surface roughness is finished to 1 to 5 μm, excellent heat conduction is exhibited in a He atmosphere. The block fin 32 follows the inclination of the Si chip 1 in the vertical and horizontal directions to contact the chip surface and the cooling surface of the housing 12 to cool the chip 1.

FIG. 10 (a) shows a chip carrier as a multilayer ceramic substrate 7.
It is mounted on the top of the chip and the back side of the chip is the thermal grease 20 or He.
A module structure in which heat is transferred to an AlN cooling plate 31 by contacting with the Al fin 30 via gas is shown. Multilayer ceramic substrate 7
Is connected to the multilayer printed board through a connector.

With respect to the various module structures described above, the present invention provides the carrier substrate 2 with a resistance layer and a capacitor on the surface thereof. FIG. 11 is an enlarged view between the chip 1 and the carrier substrate 2, and the signal pin 33 is connected to the terminating resistor (thin film) 25. Insulation layer (polyimide 24 or SiO ₂ ), resistance layer
Since 25 is finally protected by a high-purity (Cl ^- amount 10 ppm, α-ray 0.5 ppb) resin, it has a moisture-resistant and α-ray resistant structure.

A vapor deposition terminal of a Cr-Cu-Au film 27 is formed on the resistance layer 25, and an Al vapor deposition film 26 adhered to the through hole conductor 33 is formed.

12 (a) to 12 (c) show a sectional structure of a chip carrier having a built-in thin film resistor. FIG. 11 (a) shows a pattern 37 in which a thin film resistor (Cr-SiO) 36 is formed on a flattened alumina substrate after forming a W conductor 5 in a through hole and laser trimmed to 50Ω. Cr− on the resistor 36
A Cu-Au vapor deposition film terminal 27 is formed. Chip 1 and carrier substrate 2 are made of high temperature Pb-5% Sn solder (melting point 300 ° C)
After connecting with 4, fill resin 3 to make a chip carrier. In FIG. 12 (b), a thin film resistor 36 and a connecting terminal 27 are formed on a flattened and flattened alumina substrate on which a soft Al vapor deposition 26 for thermal shock absorption is applied. The thin film resistor 36 is trimmed in the same manner as in (a). Thin film resistor 36
A low Young's modulus (700 to 1000 kgf / mm ² ), high purity (Cl ⁻ amount 10 ppm), and low α-ray (0.5 ppb) resin is sufficient for protection. Since the terminals on the back of the carrier can be repaired,
-Au is attached. FIG. 1 (c) shows an example in which a resistor 36 is formed on the rear surface side of the carrier. Trimming from above the polyimide protective layer 24 does not hinder the protection of the resistance layer.

〔The invention's effect〕

According to the present invention, a multilayer substrate having a large coefficient of thermal expansion (α = 10
Enables highly reliable mounting of large chips even at ~ 15 × 10 ^-6 / ° C). Therefore, it can be mounted on a low dielectric constant organic multilayer substrate (for example, Teflon-based). Further, due to the micro-packaging, the reliability of metallization is high and the maintainability, repairability, and inspectability are also excellent, which greatly contributes to the high reliability.

By incorporating a terminating resistor, it is not necessary to mount a resistance chip, enabling higher density mounting and higher speed.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of the present invention, FIG. 2 is a sectional view of a conventional example, and FIG. 3 (a) is a conventional sectional structure, (b)
Is a cross-sectional structure of the present invention, (c) is a comparison of reliability data of both, FIG. 4 is a diagram showing the relationship between the thermal expansion coefficient of the resin and the ratio of the maximum principal stress acting on the solder, FIG. (A) ~
(F) is a cross-sectional view showing an application example of various package structures,
FIG. 6 is a cross-sectional view when applied to a multi-chip module, FIG. 7 is a cross-sectional view of a pin lead type structure, FIG. 8 is a cross-sectional view of a module applied to a boiling cooling system using a CFC liquid, and FIG. Is a cross-sectional view of a contact heat conduction type module of He atmosphere, FIG. 10 is a cross-sectional view of a module structure of the present invention having a comb-shaped cooling fin, and FIG. 11 is a cross-section of the module of the present invention equipped with a chip carrier with a built-in thin film resistor. FIGS. 12 (a) to 12 (c) are cross-sectional views of a module structure having a chip carrier with a built-in resistor. 1 ... Si chip, 2 ... Carrier substrate, 3 ... Resin, 4
…… Solder (Pb-5% Sn), 5 …… Through-hole conductor,
6,13 ...... Solder (Pb-60% Sn), 7 ... Multilayer substrate, 8 ...
… Ni bellows, 10 …… stud, 11 …… low temperature solder, 12
…… SiC cooling plate, 16 …… void, 17 …… water, 18 …… water cooling heat conductive flat plate, 19 …… stud fin, 20 …… contact part (grease), 21 …… protective resin, 22 …… Connector,
23 …… Multilayer printed circuit board, 24 …… Polyimide, 25 …… Thin film resistor, 26 …… Al conductor, 27 …… Cr-Cu-Au thin film terminal, 28…
… Thin film matching layer and resistance layer, 29 …… Spring, 30 …… Al fin, 31 …… AlN cooling plate, 32 …… Cu block fin, 33…
… Pin, 34 …… Ni-Au plated terminal, 35 …… SiO ₂ , 36 ……
Thin film resistance layer, 37 ... Tomiling part, 38 ... Cr-Cu-Ni
-Au terminal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoru Ogihara 4026 Kuji Town, Hitachi City, Ibaraki Prefecture, Hitachi Research Institute, Ltd. (72) Inventor Atsushi Morihara 4026 Kuji Town, Hitachi City, Ibaraki Prefecture, Nitate Works Co., Ltd. Inside Hitachi Research Laboratory (72) Inventor Mamoru Sawahata 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hiritsu Manufacturing Co., Ltd. Inside Hitachi Research Laboratory (72) Minoru Tanaka 292 Yoshida-cho, Totsuka-ku, Yokohama City, Kanagawa Prefectural Corporation Hitachi Manufacturing Technology Inside the laboratory (72) Inventor Fumiyuki Kobayashi 1 Horiyamashita, Horiyamashita, Hadano, Kanagawa Prefecture Kanagawa Factory, Kanagawa Plant (72) Inventor Kanji Otsuka 1450, Kamimizuhonmachi, Kodaira, Tokyo Hitachi, Ltd. Computer Business Division In device development center

Claims (8)

[Claims] 1. A module actual structure for cooling the back surface of a chip by a flip chip connection method, which is placed between a semiconductor chip, a multilayer substrate, and a semiconductor chip and a multilayer substrate, and has a thermal expansion coefficient close to that of the multilayer substrate. A carrier substrate having a coefficient of thermal expansion, having a through hole to which a through-hole conductor is attached, the semiconductor chip and the through-hole conductor being soldered on the surface facing the semiconductor chip, and the semiconductor chip and the carrier substrate The carrier substrate in which the through hole conductor and the multilayer substrate are soldered on the surface facing the multilayer substrate in which the gap between the surface and the coefficient of thermal expansion is filled with resin whose thermal expansion coefficient is close to the thermal expansion coefficient of the solder, and the semiconductor chip. Electrically connected to the cooling heat conductor provided in contact with the back surface and the through-hole conductor provided on the carrier board surface. Modules mounted structure characterized by having a resistor film. 2. The module mounting structure according to claim 1, wherein the resin has a thermal expansion coefficient close to that of solder. 3. The module mounting structure according to claim 1, wherein the carrier substrate has a thermal expansion coefficient close to that of a multilayer board. 4. A module mounting structure according to any one of claims 1 to 3, which uses an epoxy resin or a polyimide resin mixed with 30 to 60% by volume of quartz powder. 5. A module mounting structure according to any one of claims 1 to 3, wherein the epoxy resin contains 5 to 15 parts by weight of polybutadiene. 6. A module mounting structure according to any one of claims 1 to 5, wherein a resistor and a capacitor are provided on the surface or inside of the carrier substrate. 7. A module mounting structure according to claim 6, wherein an adjusting portion by trimming is provided in a part of the resistor or the capacitor. 8. A module mounting structure according to any one of claims 1 to 7, wherein a thin film resistor or a capacitor is formed after the surface of the carrier substrate is ground.