JP2524428B2 - Semiconductor device manufacturing equipment - Google Patents
Semiconductor device manufacturing equipmentInfo
- Publication number
- JP2524428B2 JP2524428B2 JP2303472A JP30347290A JP2524428B2 JP 2524428 B2 JP2524428 B2 JP 2524428B2 JP 2303472 A JP2303472 A JP 2303472A JP 30347290 A JP30347290 A JP 30347290A JP 2524428 B2 JP2524428 B2 JP 2524428B2
- Authority
- JP
- Japan
- Prior art keywords
- wire
- inner lead
- view
- device manufacturing
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置製造装置に関し、特にワイヤボン
ディングの際のリードフレームのインナーリード受け治
具に関する。The present invention relates to a semiconductor device manufacturing apparatus, and more particularly to an inner lead receiving jig for a lead frame during wire bonding.
従来、この種の半導体装置製造装置は、ワイヤボンデ
ィングの際に、第５図の断面図に示すように、表面が平
坦な受け治具10上にインナーリード３が設置されて枠状
の押え４にて押えられ、半導体素子１との間をワイヤ２
でボンディングする構造となっていた。Conventionally, in this type of semiconductor device manufacturing apparatus, as shown in the cross-sectional view of FIG. 5, the inner lead 3 is installed on the receiving jig 10 having a flat surface and the frame-shaped presser 4 is used during wire bonding. The wire 2 is held between the semiconductor element 1 and
It was a structure to bond with.
上述した従来の半導体装置製造装置は、インナーリー
ドの受け治具の表面が平坦であるために、第６図の部分
断面図に示すように、インナーリード３の平坦性にばら
つきが生じた場合その先端が浮き上がり、ワイヤボンデ
ィングの際に振動を生じ、良好なワイヤ接続ができない
という欠点があった。In the above-described conventional semiconductor device manufacturing apparatus, since the surface of the receiving jig for the inner leads is flat, when the flatness of the inner leads 3 varies as shown in the partial sectional view of FIG. There is a drawback that the tip is lifted up, vibration is generated during wire bonding, and good wire connection cannot be achieved.
更に、インナーリード先端が半導体素子搭載部に向か
って下り傾斜状態となった場合には、第７図（ａ），
（ｂ）の平面図及び側面図に、ワイヤ接合部８の圧痕形
状を示すように、ワイヤ端部９にくびれが厚く残るため
ワイヤ端部９から切れにくく、ワイヤ2aの引張り切断時
にはワイヤ２がインナーリード３から外れ易いという欠
点がある。Further, when the tip of the inner lead is inclined downward toward the semiconductor element mounting portion, as shown in FIG.
In the plan view and the side view of (b), as shown by the indentation shape of the wire joint portion 8, the wire end 9 has a thick neck and is hard to be cut from the wire end 9. It has a drawback that it is easily detached from the inner lead 3.
本発明の半導体装置製造装置は、インナーリードの受
け治具の形状が半導体素子搭載部に向かって上り傾斜を
有し、且つこの受け治具のインナーリードを押える押え
に対応する部分に溝を有している。In the semiconductor device manufacturing apparatus of the present invention, the shape of the receiving jig for the inner lead has an upward inclination toward the semiconductor element mounting portion, and the portion of the receiving jig corresponding to the presser foot for holding the inner lead has a groove. are doing.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図（ａ），（ｂ）は本発明の一実施例の平面図及
びそのＡ−Ａ断面図である。1 (a) and 1 (b) are a plan view and an AA sectional view of an embodiment of the present invention.
半導体素子１はワイヤ２によりインナーリード３と接
続される。受け治具５は半導体素子１及びインナーリー
ド３を受けるが、インナーリード３の先端を受ける部分
は半導体素子１の搭載部に向かって３〜４°の上り傾斜
を有し、且つ枠状の押え４がインナーリード３を押える
箇所には、枠状の溝６が形成されている。The semiconductor element 1 is connected to the inner lead 3 by the wire 2. The receiving jig 5 receives the semiconductor element 1 and the inner lead 3, and the portion receiving the tip of the inner lead 3 has an upward inclination of 3 to 4 ° toward the mounting portion of the semiconductor element 1, and has a frame-like retainer. A frame-shaped groove 6 is formed at a position where 4 holds the inner lead 3.
又、第２図の本実施例の部分断面図に示すように、イ
ンナーリード３の先端の平坦性にばらつきを生じても、
押え４と受け治具５の溝６により歪を吸収し、インナー
リード３の先端を受け治具５の傾斜面に密着させること
ができる。Further, as shown in the partial sectional view of this embodiment in FIG. 2, even if the flatness of the tips of the inner leads 3 varies,
The strain can be absorbed by the presser 4 and the groove 6 of the receiving jig 5, and the tips of the inner leads 3 can be brought into close contact with the inclined surface of the receiving jig 5.
第３図は本実施例によるワイヤボンディング状態を表
す断面図であり、ボンディング後、ワイヤ２が切断され
てワイヤ2aがキャピラリ７と共に上方へ移動した状態を
表している。FIG. 3 is a sectional view showing a wire bonding state according to this embodiment, and shows a state in which the wire 2 is cut and the wire 2a moves upward together with the capillary 7 after bonding.
又、第４図（ａ），（ｂ）の本発明の平面図及び側面
図にワイヤ接合部８の圧痕形状を示すように、受け治具
５が半導体素子搭載部に向かって上り傾斜となっている
ためワイヤ端部９におけるくびれが薄くなり、ワイヤ2a
を引張って切断する場合、ワイヤ端部９で切断し易く、
ボンディングされたワイヤ２がインナーリード３からは
がれにくくなる。Further, as shown in the plan view and the side view of the present invention in FIGS. 4 (a) and 4 (b), the receiving jig 5 is inclined upward toward the semiconductor element mounting portion as shown by the indentation shape of the wire bonding portion 8. Because the constriction at the wire end 9 becomes thin, the wire 2a
When pulling and cutting, it is easy to cut at the wire end 9,
The bonded wire 2 is less likely to come off the inner lead 3.
以上説明したように本発明は、インナーリード先端の
平坦性にばらつきを生じても、受け治具の溝により歪を
吸収し、インナーリードの先端を受け治具の傾斜面に密
着させることができる。As described above, according to the present invention, even if the flatness of the tip of the inner lead varies, the groove of the receiving jig absorbs the strain, and the tip of the inner lead can be brought into close contact with the inclined surface of the receiving jig. .
更に、受け治具が半導体素子搭載部に向かって上り傾
斜となっているために、ワイヤを引張って切断する場
合、ワイヤ端部で切断し易いので、ボンディングされた
ワイヤがインナーリードからはがれにくいという効果が
ある。Further, since the receiving jig is inclined upward toward the semiconductor element mounting portion, when the wire is pulled and cut, it is easy to cut at the wire end portion, so that the bonded wire is difficult to be peeled from the inner lead. effective.
第１図（ａ），（ｂ）は本発明の一実施例の平面図及び
そのＡ−Ａ断面図、第２図は一実施例の部分断面図、第
３図は一実施例によるボンディング状態を示す断面図、
第４図（ａ），（ｂ）は一実施例によるワイヤ圧痕状態
を示す平面図及び側面図、第５図は従来の受け治具の断
面図、第６図は従来の問題点を示す部分断面図、第７図
（ａ），（ｂ）は従来のワイヤ圧痕状態を示す平面図及
び側面図である。 １…半導体素子、2,2a…ワイヤ、３…インナーリード、
４…押え、５…受け治具、６…溝、７…キャピラリ、８
…ワイヤ接合部、９…ワイヤ端部、10…受け治具。1 (a) and 1 (b) are a plan view and an AA sectional view of an embodiment of the present invention, FIG. 2 is a partial sectional view of the embodiment, and FIG. 3 is a bonding state according to the embodiment. Cross section showing
4 (a) and 4 (b) are a plan view and a side view showing a wire indentation state according to one embodiment, FIG. 5 is a cross-sectional view of a conventional receiving jig, and FIG. 6 is a portion showing conventional problems. A cross-sectional view and FIGS. 7A and 7B are a plan view and a side view showing a conventional wire indentation state. 1 ... Semiconductor element, 2, 2a ... Wire, 3 ... Inner lead,
4 ... Presser foot, 5 ... Receiving jig, 6 ... Groove, 7 ... Capillary, 8
... wire joining part, 9 ... wire end part, 10 ... receiving jig.
Claims (1)
ードとをワイヤで接続する半導体装置製造装置におい
て、インナーリードを載置する受け治具部が半導体素子
搭載部に向かって上り傾斜となる形状を有し、且つイン
ナーリード部を上方より固定する押え治具の前記受け治
具に対応する部分に枠状溝を有することを特徴とする半
導体装置製造装置。1. A semiconductor device manufacturing apparatus for connecting a semiconductor element and an inner lead of a lead frame with a wire, wherein a receiving jig portion on which the inner lead is mounted has a shape inclined upward toward a semiconductor element mounting portion. In addition, the semiconductor device manufacturing apparatus is characterized by having a frame-shaped groove in a portion of the holding jig for fixing the inner lead portion from above, corresponding to the receiving jig.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2303472A JP2524428B2 (en) | 1990-11-08 | 1990-11-08 | Semiconductor device manufacturing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2303472A JP2524428B2 (en) | 1990-11-08 | 1990-11-08 | Semiconductor device manufacturing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04176135A JPH04176135A (en) | 1992-06-23 |
| JP2524428B2 true JP2524428B2 (en) | 1996-08-14 |
Family
ID=17921374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2303472A Expired - Lifetime JP2524428B2 (en) | 1990-11-08 | 1990-11-08 | Semiconductor device manufacturing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2524428B2 (en) |
-
1990
- 1990-11-08 JP JP2303472A patent/JP2524428B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04176135A (en) | 1992-06-23 |
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