JP2523966B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2523966B2
JP2523966B2 JP2225789A JP22578990A JP2523966B2 JP 2523966 B2 JP2523966 B2 JP 2523966B2 JP 2225789 A JP2225789 A JP 2225789A JP 22578990 A JP22578990 A JP 22578990A JP 2523966 B2 JP2523966 B2 JP 2523966B2
Authority
JP
Japan
Prior art keywords
type
diffusion region
drain
source
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2225789A
Other languages
English (en)
Other versions
JPH04107834A (ja
Inventor
利彦 宇野
英夫 川崎
雄司 山西
宏 谷田
裕之 進藤
誠毅 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2225789A priority Critical patent/JP2523966B2/ja
Publication of JPH04107834A publication Critical patent/JPH04107834A/ja
Application granted granted Critical
Publication of JP2523966B2 publication Critical patent/JP2523966B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置に関し、特に低電圧制御論理素子
と横型パワーMOSFETを同一チップ上に形成する際に、高
電圧低オン抵抗の横型MOSFETを内蔵することを可能にし
ようとするものである。
従来の技術 従来の高電圧横型MOSFETにおいては、チップ表面上
に、ソース，ドレインの電極パットを形成し、各パット
に対し、１本のアルミワイヤーでボンディングを行って
いた。
発明が解決しようとする課題 従来の高電圧横型MOSFETにおいては、大きな電流を基
板表面上のドレイン−ソース間に流すために、オン時の
電極パット部における抵抗値が増加することになる。こ
のため、電極部での抵抗を下げるには、電極のアルミ厚
を厚くする方法が取られていた。しかし低電圧制御論理
素子パターンの制御により、横型パワーMOSFET部のアル
ミ厚を厚くすると、低電圧制御論理素子部のパターンの
集積度を落としてしまうという欠点を有していた。
課題を解決するための手段 本発明は、このような従来の欠点を解消するものであ
り、特に低電圧制御論理素子と高電圧横型MOSFETを同一
チップ上に形成することが可能となるようにしたもので
ある。すなわち、MOSFETのオン時の抵抗を低減させるた
め、ソース，ドレインそれぞれの電極パッド部におい
て、金ワイヤーを多数本ボンディングし、電極部での抵
抗を小さくする構造としている。
作用 このような本発明では、ソース，ドレインの電極部
に、多数本の金ワイヤーをボンディングして電気的接続
をとっているので、MOSFETのオン時において電極部にお
ける抵抗を低減することが可能となる。
実 施 例 以下、本発明の一実施例について、図面を参照しなが
ら説明する。
第１図は、本発明の一実施例における高電圧横型MOSF
ETのパターン部における断面構造図である。１はＰ型半
導体基板、２はＰ＋型サブストレート層、3,4は一対を
なす、Ｎ＋型ソース拡散領域,N＋型ドレイン拡散領域、
５はＮ型延長ドレイン領域、６はＰ＋型拡散領域、７は
MOSFETのゲート酸化膜、８はゲートポリシリコン電極、
９はゲート８とソース3,ドレイン４を絶縁する層間絶縁
膜、10はソースアルミ電極、11はドレインアルミ電極で
ある。
第２図は、本実施例の高電圧横型MOSFETの表面を示す
平面図である。12はソース電極にボンディングされた複
数本のソース金ワイヤー、13はドレイン電極11にボンデ
ィングされた複数本のドレイン金ワイヤーである。
第３図は、比較のために示す従来の高電圧横型MOSFET
の平面図である。14は１本のソースアルミワイヤー、15
は１本のドレインアルミワイヤーである。
アルミ電極工程において、低電圧制御論理素子部は３
μｍルールで形成しているため、アルミ厚は最大２μｍ
となっている。したがって、横型パワーMOSFET部のアル
ミ厚も２μｍとなる。そこで、電極部10,11での配線に
複数本の金ワイヤーを使用し、電極部10,11での抵抗の
低減を図った。
本実施例の構造と従来の構造との比較結果を示したの
が第４図であり、本実施例の構造によれば金ワイヤーで
の配線により、電極部での抵抗を従来に比して18％低減
することが可能となる。また、金ワイヤーでの配線によ
り、電極部の面積を10％縮小できるため、両方の効果に
より、横型MOSFETの抵抗を28％を低減するとが可能とな
る。
発明の効果 以上のように本発明によれば、低電圧制御論理素子と
高電圧横型MOSFETのオン時の抵抗を低減させることが可
能である。
【図面の簡単な説明】
第１図は本発明の一実施例における高電圧横型MOSFETの
断面図、第２図は本実施例における高電圧横型MOSFETの
平面図、第３図は従来の高電圧横型MOSFETの平面図、第
４図は従来の構造に本実施例の構造とを比較して示す特
性図である。 １……Ｐ型半導体基板、２……Ｐ＋型サブストレート
層、３……Ｎ＋型ソース拡散領域、４……Ｎ＋型ドレイ
ン拡散領域、５……延長ドレイン領域、６……Ｐ＋型拡
散領域、７……ゲート酸化膜、８……ゲートポリシリコ
ン、９……層間絶縁膜、10……ソースアルミ電極、11…
…ドレインアルミ電極、12……ソース金ワイヤー、13…
…ドレイン金ワイヤー。
───────────────────────────────────────────────────── フロントページの続き (72)発明者 谷田 宏 大阪府門真市大字門真1006番地 松下電 子工業株式会社内 (72)発明者 進藤 裕之 大阪府門真市大字門真1006番地 松下電 子工業株式会社内 (72)発明者 山口 誠毅 大阪府門真市大字門真1006番地 松下電 子工業株式会社内 (56)参考文献 特開 昭50−38467（ＪＰ，Ａ) 特開 平３−265149（ＪＰ，Ａ)

Claims (1)

    (57)【特許請求の範囲】
  1. 【請求項１】Ｐ型半導体基板と、このＰ型半導体基板下
    に設けられたＰ＋型サブストレート層と、前記半導体基
    板内の表面に横方向に間隔をとって設けられた一対のＮ
    ＋型ソース拡散領域、Ｎ＋型ドレイン拡散領域と、前記
    ドレイン拡散領域から基板表面に横方向に延長して設け
    られた延長ドレイン領域と、前記Ｎ＋型ソース拡散領域
    とＮ＋型ドレイン拡散領域の間にあり、かつ延長ドレイ
    ン拡散領域内にあるＰ＋型拡散領域と、前記Ｎ＋型ソー
    ス拡散領域と延長ドレイン拡散領域の間を覆うゲート酸
    化膜と、このゲート酸化膜上に形成されたポリシリコン
    ゲートを有するMOSFETを備え、上記ソース，ドレイン拡
    散領域の電極部に、多数本の金ワイヤーをボンディング
    して電極部の抵抗を低減させた半導体装置。
JP2225789A 1990-08-27 1990-08-27 半導体装置 Expired - Fee Related JP2523966B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2225789A JP2523966B2 (ja) 1990-08-27 1990-08-27 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2225789A JP2523966B2 (ja) 1990-08-27 1990-08-27 半導体装置

Publications (2)

Publication Number Publication Date
JPH04107834A JPH04107834A (ja) 1992-04-09
JP2523966B2 true JP2523966B2 (ja) 1996-08-14

Family

ID=16834806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2225789A Expired - Fee Related JP2523966B2 (ja) 1990-08-27 1990-08-27 半導体装置

Country Status (1)

Country Link
JP (1) JP2523966B2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2567976B2 (ja) * 1990-08-29 1996-12-25 シャープ株式会社 高周波低雑音半導体装置

Also Published As

Publication number Publication date
JPH04107834A (ja) 1992-04-09

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