JP2514910Y2 - 半導体素子収納用パッケージ - Google Patents
半導体素子収納用パッケージInfo
- Publication number
- JP2514910Y2 JP2514910Y2 JP1990127591U JP12759190U JP2514910Y2 JP 2514910 Y2 JP2514910 Y2 JP 2514910Y2 JP 1990127591 U JP1990127591 U JP 1990127591U JP 12759190 U JP12759190 U JP 12759190U JP 2514910 Y2 JP2514910 Y2 JP 2514910Y2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- metallized
- semiconductor element
- insulating substrate
- lid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990127591U JP2514910Y2 (ja) | 1990-11-28 | 1990-11-28 | 半導体素子収納用パッケージ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990127591U JP2514910Y2 (ja) | 1990-11-28 | 1990-11-28 | 半導体素子収納用パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0482853U JPH0482853U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-07-20 |
JP2514910Y2 true JP2514910Y2 (ja) | 1996-10-23 |
Family
ID=31875085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1990127591U Expired - Lifetime JP2514910Y2 (ja) | 1990-11-28 | 1990-11-28 | 半導体素子収納用パッケージ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2514910Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5591844A (en) * | 1978-12-28 | 1980-07-11 | Fujitsu Ltd | Electronic parts package |
JPS5868951A (ja) * | 1981-10-21 | 1983-04-25 | Hitachi Ltd | 半導体装置 |
US4672739A (en) * | 1985-04-11 | 1987-06-16 | International Business Machines Corporation | Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric substrate |
JPH01166547A (ja) * | 1987-12-23 | 1989-06-30 | Hitachi Ltd | セラミック基板 |
-
1990
- 1990-11-28 JP JP1990127591U patent/JP2514910Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0482853U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-07-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |