JP2507791Y2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP2507791Y2
JP2507791Y2 JP1990097000U JP9700090U JP2507791Y2 JP 2507791 Y2 JP2507791 Y2 JP 2507791Y2 JP 1990097000 U JP1990097000 U JP 1990097000U JP 9700090 U JP9700090 U JP 9700090U JP 2507791 Y2 JP2507791 Y2 JP 2507791Y2
Authority
JP
Japan
Prior art keywords
gel
metal base
insulating material
semiconductor device
mold material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1990097000U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0455147U (enrdf_load_stackoverflow
Inventor
強 中村
泰男 長谷川
充由 海老塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP1990097000U priority Critical patent/JP2507791Y2/ja
Publication of JPH0455147U publication Critical patent/JPH0455147U/ja
Application granted granted Critical
Publication of JP2507791Y2 publication Critical patent/JP2507791Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/40139Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous strap daisy chain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP1990097000U 1990-09-14 1990-09-14 半導体装置 Expired - Fee Related JP2507791Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990097000U JP2507791Y2 (ja) 1990-09-14 1990-09-14 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990097000U JP2507791Y2 (ja) 1990-09-14 1990-09-14 半導体装置

Publications (2)

Publication Number Publication Date
JPH0455147U JPH0455147U (enrdf_load_stackoverflow) 1992-05-12
JP2507791Y2 true JP2507791Y2 (ja) 1996-08-21

Family

ID=31837000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990097000U Expired - Fee Related JP2507791Y2 (ja) 1990-09-14 1990-09-14 半導体装置

Country Status (1)

Country Link
JP (1) JP2507791Y2 (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2761848B2 (ja) * 1995-01-06 1998-06-04 株式会社伊藤製作所 建築用柱打込器

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0233953A (ja) * 1988-07-22 1990-02-05 Mitsubishi Electric Corp 半導体装置
JPH02222565A (ja) * 1989-02-23 1990-09-05 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
JPH0455147U (enrdf_load_stackoverflow) 1992-05-12

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees