JP2024505483A5 - - Google Patents
Info
- Publication number
- JP2024505483A5 JP2024505483A5 JP2023544562A JP2023544562A JP2024505483A5 JP 2024505483 A5 JP2024505483 A5 JP 2024505483A5 JP 2023544562 A JP2023544562 A JP 2023544562A JP 2023544562 A JP2023544562 A JP 2023544562A JP 2024505483 A5 JP2024505483 A5 JP 2024505483A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- trace
- substrate
- metallization
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/161,105 US12021063B2 (en) | 2021-01-28 | 2021-01-28 | Circular bond finger pad |
| US17/161,105 | 2021-01-28 | ||
| PCT/US2021/065329 WO2022164565A1 (en) | 2021-01-28 | 2021-12-28 | Circular bond finger pad |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2024505483A JP2024505483A (ja) | 2024-02-06 |
| JP2024505483A5 true JP2024505483A5 (https=) | 2024-12-20 |
| JP7797515B2 JP7797515B2 (ja) | 2026-01-13 |
Family
ID=80225380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023544562A Active JP7797515B2 (ja) | 2021-01-28 | 2021-12-28 | 円形ボンドフィンガーパッド |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US12021063B2 (https=) |
| EP (1) | EP4285412A1 (https=) |
| JP (1) | JP7797515B2 (https=) |
| KR (1) | KR20230137322A (https=) |
| CN (1) | CN116711076A (https=) |
| BR (1) | BR112023014131A2 (https=) |
| TW (1) | TWI905352B (https=) |
| WO (1) | WO2022164565A1 (https=) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3581086B2 (ja) | 2000-09-07 | 2004-10-27 | 松下電器産業株式会社 | 半導体装置 |
| JP2002124744A (ja) | 2000-10-12 | 2002-04-26 | Eastern Co Ltd | 回路基板 |
| US6972152B2 (en) * | 2003-06-27 | 2005-12-06 | Intel Corporation | Use of direct gold surface finish on a copper wire-bond substrate, methods of making same, and methods of testing same |
| US8076232B2 (en) | 2008-04-03 | 2011-12-13 | Stats Chippac, Ltd. | Semiconductor device and method of forming composite bump-on-lead interconnection |
| DE102004005586B3 (de) | 2004-02-04 | 2005-09-29 | Infineon Technologies Ag | Halbleiterbauteil mit einem Halbleiterchipstapel auf einer Umverdrahtungsplatte und Herstellung desselben |
| JP5356876B2 (ja) | 2008-03-28 | 2013-12-04 | 日本特殊陶業株式会社 | 多層配線基板及びその製造方法 |
| JP6196092B2 (ja) | 2013-07-30 | 2017-09-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US20180005944A1 (en) | 2016-07-02 | 2018-01-04 | Intel Corporation | Substrate with sub-interconnect layer |
| KR102687750B1 (ko) * | 2019-06-17 | 2024-07-23 | 에스케이하이닉스 주식회사 | 서포팅 기판을 포함한 스택 패키지 |
-
2021
- 2021-01-28 US US17/161,105 patent/US12021063B2/en active Active
- 2021-12-28 EP EP21854719.8A patent/EP4285412A1/en active Pending
- 2021-12-28 TW TW110149098A patent/TWI905352B/zh active
- 2021-12-28 JP JP2023544562A patent/JP7797515B2/ja active Active
- 2021-12-28 CN CN202180090180.5A patent/CN116711076A/zh active Pending
- 2021-12-28 KR KR1020237024938A patent/KR20230137322A/ko active Pending
- 2021-12-28 BR BR112023014131A patent/BR112023014131A2/pt unknown
- 2021-12-28 WO PCT/US2021/065329 patent/WO2022164565A1/en not_active Ceased
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