CN116711076A - 圆形结合指焊盘 - Google Patents
圆形结合指焊盘 Download PDFInfo
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- CN116711076A CN116711076A CN202180090180.5A CN202180090180A CN116711076A CN 116711076 A CN116711076 A CN 116711076A CN 202180090180 A CN202180090180 A CN 202180090180A CN 116711076 A CN116711076 A CN 116711076A
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Abstract
公开了集成电路(IC)封装件的示例。每个IC封装件可以包括衬底上的倒装芯片(FC)裸片、该FC裸片上方的引线结合裸片、连接到该引线结合裸片的引线结合件、以及在该衬底上并且包封该FC裸片、该引线结合裸片和该引线结合件的成型物。该衬底可以包括至少第一金属化层,该第一金属化层包括该第一衬底层、在第一衬底层上并且在该第一金属化层内布线以与该FC裸片的一个或多个FC互连件电耦合的迹线、以及形成在该迹线上的结合指焊盘。该结合指焊盘可以是圆形的。该引线结合件可以电连接到该迹线,使得该引线结合裸片通过该引线结合件、该结合指焊盘和该迹线与该FC裸片电耦合。
Description
相关申请的交叉引用
本专利申请要求2021年1月28日提交的标题为“CIRCULAR BOND FINGER PAD(圆形结合指焊盘)”的美国非临时申请第17/161,105号的权益,该申请被转让给本申请的受让人并且其全部内容通过引用明确地并入本文。
技术领域
本公开总体涉及集成电路(IC)封装件,并且更特别地,但不排他地,涉及例如用于5G设备的圆形结合指焊盘。
背景技术
集成电路技术通过有源元件的小型化在提高计算能力方面取得了长足的进步。封装件设备可以在许多电子设备中找到,包括处理器、服务器、射频(RF)IC等。封装件技术在高引脚数设备和/或高产量元件中变得成本有效。
示例的常规IC封装件包括衬底上的倒装芯片(FC)裸片,诸如基带调制解调器。存储器裸片位于基带调制解调器上方,其间具有裸片附接粘合剂。成型物将基带调制解调器和存储器裸片包封在衬底上方。衬底包括金属化层,其中迹线被布线成与基带调制解调器的焊料凸块电耦合。在成型物内,引线结合件(例如,由金(Au)、银(Ag)、铜(Cu)等形成)用于通过迹线将存储器裸片与基带调制解调器电耦合。引线结合件通过迹线上的结合指焊盘连接到迹线。通常,焊盘是镀镍/金(Ni/Au)表面。这意味着迹线是由电解镀覆工艺形成的。也就是说,迹线是镀覆迹线。因此,镀覆迹线延伸到衬底的边缘。边缘处的迹线连接到镀覆线,镀覆线电连接到所有结合指焊盘以用于结合指焊盘的电解上镀覆。
结合指焊盘(例如,由Cu形成)的形状通常是长方形或椭圆形。这是因为焊盘是非焊料掩模限定的(NSMD),其中焊盘是金属限定的并且焊料掩模开口比焊盘宽。这意味着由于在焊料掩模开口和焊盘之间存在间隙,整个Cu焊盘被暴露。
焊料掩模开口可以向任何方向移动。这意味着由于Ni/Au镀覆,NSMD结合指焊盘通常需要宽松的间距设计规则。不幸的是,这导致结合指区域中的低Cu密度。此外,在常规封装件中,结合指位于衬底的边缘附近,以便于镀覆迹线布线。这意味着需要长的引线结合件来将存储器芯片连接到结合指。这增加了引线结合件的电阻。长引线结合件也更难实现。
因此,需要克服常规封装件的缺陷的系统、装置和方法,包括本文提供的方法、系统和装置。
发明内容
以下给出了与本文公开的装置和方法相关联的一个或多个方面和/或示例的简要概述。因此,以下概述不应被认为是与所有考虑方面和/或示例相关联的广泛综述,也不应被认为是确定与所有考虑方面和/或示例相关联的关键或重要元件,或描绘与任何特定方面和/或示例相关联的范围。因此,以下概述的唯一目的是在下文呈现的详细描述之前以简化的形式呈现与一个或多个方面相关的某些概念和/或与本文公开的装置和方法相关的示例。
公开了示例性集成电路(IC)封装件。IC封装件可以包括衬底、倒装芯片(FC)裸片、设置在FC裸片上方的引线结合裸片、引线结合件,连接到引线结合裸片、以及衬底上的成型物。该成型物可以包封FC裸片、引线结合裸片和引线结合件。衬底可以包括一个或多个金属化层,包括第一金属化层。第一金属化层可以包括第一衬底层、迹线和结合指焊盘。迹线可以形成在第一衬底层上,并且在第一金属化层内布线以与FC裸片的一个或多个FC互连件电耦合。结合指焊盘可以形成在迹线上。结合指焊盘的形状可以基本上是圆形的。引线结合件可以电连接到结合指焊盘,使得引线结合裸片通过引线结合件、结合指焊盘和迹线与FC裸片电耦合。
公开了一种制造集成电路(IC)封装件的方法。该方法可以包括形成衬底。该方法还可以包括在衬底上设置倒装芯片(FC)裸片。该方法还可以包括在FC裸片上方设置引线结合裸片。该方法还可以包括形成引线结合件,该引线结合件连接到引线结合裸片。该方法还可以包括在衬底上形成成型物,该成型物包封FC裸片、引线结合裸片和引线结合件。衬底可以被形成为包括一个或多个金属化层,包括第一金属化层。第一金属化层可以包括第一衬底层、迹线和结合指焊盘。迹线可以形成在第一衬底层上,并且在第一金属化层内布线以与FC裸片的一个或多个FC互连件电耦合。结合指焊盘可以形成在迹线上。结合指焊盘的形状可以基本上是圆形的。引线结合件可以形成为电连接到结合指焊盘,使得引线结合裸片通过引线结合件、结合指焊盘和迹线与FC裸片电耦合。
基于附图和具体实施方式,与本文公开的装置和方法相关联的其他特征和优点对于本领域技术人员来说将是显而易见的。
附图说明
当结合附图考虑时,通过参考下面的具体实施方式,将容易获得对本公开的各方面及其许多伴随优点的更完整的理解,附图仅用于说明而非限制本公开。
图1图示了常规集成电路(IC)封装件的示例。
图2图示了常规IC封装件的结合指焊盘。
图3图示了根据本公开的一个或多个方面的IC封装件的示例。
图4图示了根据本公开的一个或多个方面的IC封装件的结合指焊盘。
图5至图6图示了根据本公开的一个或多个方面的IC封装件的更多示例。
图7是根据本公开的一个或多个方面的制造用于IC封装件的衬底的不同阶段的工艺流程。
图8是根据本公开的一个或多个方面的组装IC封装件的不同阶段的工艺流程。
图9图示了根据本公开的一个或多个方面的制造IC封装件的示例方法的流程图。
图10图示了可以利用本公开的一个或多个方面的各种电子设备。
基于附图和具体实施方式,与本文公开的方面相关联的其他目的和优点对于本领域技术人员来说将是显而易见的。根据惯例,附图所示的特征可能不是按比例绘制的。因此,为了清楚起见,所描绘的特征的尺寸可以任意扩大或缩小。根据惯例,为了清楚起见,一些附图被简化。因此,附图可能没有描绘特定装置或方法的所有部件。此外,在整个说明书和附图中,相同的附图标记表示相同的特征。
具体实施方式
在针对具体实施例的以下描述和相关附图中图示了本公开的各方面。在不脱离本文教导的范围的情况下,可以设计替代的方面或实施例。另外,本文的说明性实施例的众所周知的元件可能没有被详细描述或可能被省略,以便不会模糊本公开中教导的相关细节。
在某些描述的示例实现方式中,标识了各种部件结构和操作部分可以取自已知的常规技术,并且然后根据一个或多个示例实施例来布置的示例。在此类情况下,可以省略已知的常规部件结构和/或操作部分的内部细节,以帮助避免本文公开的说明性实施例中中图示的概念的潜在混淆。
本文使用的术语仅是为了描述特定的实施例的,而不是为了限制。如本文所用,单数形式“一”、“一个”和“该”也旨在包括复数形式,除非上下文清楚地指出不是这样。还应理解,术语“包括(comprises)”、“包括(comprising)”、“包括(includes)”和/或“包括(including)”在本文使用时,指定所陈述的特征、整数、步骤、操作、元件和/或部件的存在,但是不排除一个或多个其他特征、整数、步骤、操作、元件、部件和/或其组合的存在或添加。
根据本文的各个方面,提出解决与常规IC封装件相关联的问题。作为背景,图1图示了常规IC封装件的示例。常规IC封装件100包括作为在三层衬底上的倒装芯片(FC)裸片的基带调制解调器110。存储器裸片120在基带调制解调器110上方,其间具有裸片附接粘合剂130。成型物140将基带调制解调器110和存储器裸片120包封在衬底上方。
三层衬底包括金属化层M1、M2和M3。M1层包括第一衬底层170,M2层包括第二衬底层180,并且M3层包括第三衬底层190。在金属化层M1内,迹线172被布线成与基带调制解调器110的焊料凸块115电耦合。同样在金属化层M1内,阻焊剂(SR)178形成在迹线172上以及第一衬底170上。在阻焊剂178的开口内的迹线172上形成结合指焊盘150(下文对此有更多描述)。焊球165形成在第三衬底层-190的下表面上。
在成型物140内,引线结合件160(例如,由金(Au)、银(Ag)、铜(Cu)等形成)用于通过迹线172将存储器裸片120与基带调制解调器110电耦合。引线结合件160通过结合指焊盘150电连接到迹线172。
通常,结合指焊盘150是镀在迹线172表面上的镍/金(Ni/Au)。因此,迹线172也可以被称为镀覆迹线。镀覆迹线172延伸到衬底的边缘。边缘处的镀覆迹线172连接到一个或多个镀覆线(未示出),该一个或多个镀覆线电连接到结合指焊盘150以用于结合指焊盘150的电解上镀覆。
在图1中,结合指焊盘150的附近用虚线圆突出显示。应注意的是,结合指焊盘150形成在阻焊剂178的开口内。还要应注意的是,在结合指焊盘150的任一侧,在结合指焊盘150和阻焊剂178之间存在间隙。也就是说,阻焊剂178的开口——也称为阻焊剂开口(SRO)——比结合指焊盘150宽。
图2图示了结合指焊盘附近的M1层的俯视图。这里,两个结合指焊盘150被图示为形成在SRO内,SRO是迹线172的未被阻焊剂178覆盖的区域。如图所示,结合指焊盘150(例如,由Ni/Au镀覆形成)的形状通常是长方形或椭圆形。例如,每个结合指焊盘150的尺寸可以是100μm(例如,图2中的左右)乘以50μm(例如,图2中的上下)。
结合指焊盘150是非焊料掩模限定的(NSMD)焊盘的示例。如所指出的,SRO比结合指焊盘150宽。这意味着结合指焊盘150的形状不由阻焊剂178(也称为焊料掩模)限定。而是,结合指焊盘150是金属限定的。
由于SRO比结合指焊盘150宽,所以由于SRO和结合指焊盘150之间的间隙,整个结合指焊盘150被暴露。SRO可以向任何方向移动。这意味着由于Ni/Au镀覆,结合指焊盘150需要宽松的间距设计规则。这是因为当形成结合指焊盘150时,暴露在SRO中的包括任何迹线172的任何金属也可能经受镀覆。这意味着迹线172会变粗。因此,相邻的迹线172可能被短路。宽松的间距设计意味着在相邻结合指焊盘150之间提供足够的间距,以防止诸如不期望的短路的问题发生。相邻结合指焊盘150之间的间距可以很大,例如25μm或更大。不幸的是,松散的间距导致SRO区域中的低Cu密度。在印刷电路板(PCB)中,低铜密度区域可能会出现诸如翘曲(例如,2mm或更大)的不良问题。这对于预浸PCB来说尤其如此。
另一个问题如下。返回参考图1,NSMD结合指焊盘150位于衬底的边缘附近,以便更容易将镀覆迹线布线到衬底的边缘。这意味着引线结合件160需要非常长。不幸的是,长的引线结合件与电气(例如,高电阻)和工艺问题(例如,引线短路)相关联。
根据本文公开的各个方面,为了解决与常规IC封装件相关联的问题,提出了提供焊料掩模限定(SMD)的圆形结合指焊盘。在SMD焊盘中,焊料掩模小于构成结合指焊盘的实际金属。这意味着当执行电解镀覆工艺时,仅开口(阻焊层开口(SMO))被镀覆以形成结合指焊盘。迹线不经受镀覆。因此,相邻结合指焊盘之间的间距可以减小,例如减小到15μm甚至更小,而不用担心发生短路。这意味着金属密度(例如,Cu密度)可以很高,这导致翘曲减少或甚至消除。
所提出的SMD结合指焊盘的另一个优点是可以位于任何地方。回想一下,常规的NSMD结合指焊盘150的位置被限制在衬底的边缘附近。然而,所提出的SMD结合指焊盘可以位于衬底上的任何地方。例如,所提出的SMD结合指焊盘可以位于存储器裸片附近。因此,引线结合件可以是短的,这可以降低电阻,并且还降低了引线短路的可能性。
图3图示了根据本公开的一个或多个方面的IC封装件的示例。示例IC封装件300可以包括倒装芯片(FC)裸片310。基带调制解调器芯片可以是FC裸片310的示例。FC裸片310可以在包括一个或多个金属化层(下面进一步描述)的衬底上方。引线结合裸片320(例如,存储器裸片)可以设置在FC裸片310上方,其间具有裸片附接粘合剂330。成型物340可以在衬底上和衬底上方包封FC裸片310和引线结合裸片320。
在图3中,示出了具有三个金属化层M1、M2和M3的衬底。这仅是示例。金属化层的实际数量不限于此。也就是说,衬底可以包括一个或多个金属化层。每个金属化层可以包括衬底层。例如,M1金属化层(或第一金属化层)可以包括第一衬底层370。同样,M2金属化层(或第二金属化层)可以包括第二衬底层380,M3金属化层(或第三金属化层)可以包括第三衬底层390等。衬底层370、380、390可以各自是绝缘层。
在一个、一些或所有金属化层内,迹线可以被布线成与FC裸片310的FC互连件315(例如,凸块)电耦合。例如,在图3中,在第一金属化层M1内,迹线372可以形成在第一衬底层370上并且被布线为与FC互连件315电耦合。迹线372可以由诸如Cu、铝(Al)等的导电金属形成。
同样在第一金属化层M1内,可以在迹线372上以及第一衬底层370上形成焊料掩模(SM)378(例如,阻焊剂)。结合指焊盘350可以形成在阻焊膜378的阻焊膜开口(SMO,下文将详细描述)内的迹线372上。外部互连件365(例如,焊球)可以形成在衬底的下表面上。在此情况下,外部互连件365可以形成在最低衬底层(在此情况下是衬底层390)的下表面上。
在成型物340内,可以形成引线结合件360以将引线结合裸片320与FC裸片310电耦合。例如,引线结合件360的端部可以连接到引线结合裸片320和结合指焊盘350。以此方式,引线结合裸片320可以通过引线结合件360、结合指焊盘350和迹线372与FC裸片310电耦合。引线结合件360可以由诸如金(Au)、银(Ag)、铜(Cu)等金属形成。
尽管未示出,但是应注意的是,实际上,可能会有多个引线结合件360、多个结合指焊盘350和多个迹线372。然而,为了便于描述和解释,仅图示了一个引线结合件360和对应的一个结合指焊盘350。
结合指焊盘350可以是镀在迹线372的表面上的金属(例如,镍/金(Ni/Au))。迹线372可以从结合指焊盘350延伸到第一金属化层M1内的衬底的边缘,使得衬底的边缘处的迹线372与结合指焊盘350电耦合。以此方式,迹线372可以在衬底边缘连接到一个或多个镀覆线(未示出)以用于结合指焊盘350的电解镀覆。
在图3中,结合指焊盘350的附近用虚线圆突出显示。结合指焊盘350可以形成在焊料掩模378的开口内,即,在焊料掩模开口(SMO)内。但是不同于常规IC封装件100的结合指焊盘150,在结合指焊盘350和焊料掩模378之间没有间隙。也就是说,SMO不比结合指焊盘350宽。
图4图示了结合指焊盘附近的M1层的俯视图。这里,单个结合指焊盘350被示为形成在SMO内。SMO可以被限定为第一衬底层370和迹线372上方未被阻焊膜378覆盖的区域。应注意的是,第一衬底层370和迹线372在此俯视图中不可见。这是因为第一衬底层370和迹线372至少在结合指焊盘350附近被焊料掩模378和结合指焊盘350完全覆盖。
与常规的结合指焊盘150不同,结合指焊盘350的形状(例如,形成的金属(例如,Ni/Au)镀覆)可以是圆形或基本上圆形。此外,结合指焊盘350的尺寸或大小可以做得很小。例如,结合指焊盘350的直径可以是50μm或更小,这意味着SMO也可以是50μm或更小。结合指焊盘350是焊料掩模限定的(MSD)焊盘的示例。换句话说,结合指焊盘350的特性(例如,大小、形状等)可以至少部分地由焊料掩模378限定。
回想一下,对于常规IC封装件100,宽松的间距设计是必要的。但是对于SMD结合指焊盘350,间距可以变紧。这是因为迹线372被焊料掩模378覆盖,即迹线372没有暴露。更特别地,除了迹线372的其上形成结合指焊盘350的部分,即,除了迹线372的对应于SMO的部分,迹线372没有被暴露。
因此,即使在电解镀覆工艺中使用迹线372来形成结合指焊盘350,迹线372本身也不会经受镀覆。因此,在镀覆期间,迹线372的大小不会改变,至少不会显著改变。这意味着迹线372之间发生短路的可能性可以显著降低。因此,结合指焊盘350之间的间距可以减小到例如15μm或更小。
由于迹线372之间的间距可以减小,这意味着迹线372的密度可以对应地增加。换句话说,金属密度(例如,Cu密度)可以随着SMD结合指焊盘350而增加。这是有利的,因为可以减少(例如,小于2mm)或甚至消除翘曲。
返回参考图3,注意结合指焊盘350靠近引线结合裸片320定位。实际上,可以说结合指焊盘350可以被定位成使得可以被限定为从引线结合裸片320到结合指焊盘350的距离的裸片-焊盘距离小于可以被限定为从衬底的边缘到结合指焊盘350的距离的边缘-焊盘距离。这与裸片-焊盘距离远大于边缘-焊盘距离的常规IC封装件相反。由于短的裸片-焊盘距离,引线结合件360可以对应地变短。因此,可以改善电特性(例如,更低的电阻)并且可以减少工艺问题(例如,更少的引线短路的可能性)。
此外,引线结合件360可以是反向引线结合件。也就是说,引线结合件360的一端可以球形结合到结合指焊盘350,而另一端可以针脚式结合到引线结合裸片320。尽管未示出,但是在FC裸片310上方可以有多个引线结合裸片320,并且所有引线结合裸片320和FC裸片310可以被成型物340包封。此外,多个引线结合裸片320中的每个引线结合件裸片可以通过对应的引线结合件360和结合指焊盘350电耦合到FC裸片310。
图5图示了根据本公开的一个或多个方面的IC封装件500的另一个示例。IC封装件500可以包括衬底上的倒装芯片(FC)裸片510(例如,基带调制解调器)、设置在FC裸片510上方的其间具有裸片附接粘合剂530的引线结合裸片520(例如,存储器裸片)、在衬底上和上方包封FC裸片510和引线结合裸片520的成型物540。衬底可以包括一个或多个金属化层(例如,M1、M2、M3等)并且每个金属化层可以包括对应的衬底层(例如,第一衬底层570、第二衬底层580、第三衬底层590等)。
在一个、一些或所有金属化层内,迹线可以被布线成与FC裸片510的FC互连件515(例如,凸块)电耦合。例如,在图5中,在第一金属化层M1内,迹线572-1可以形成在第一衬底层570上并且被布线为与FC互连件515电耦合。出于下面讨论的原因,迹线572-1也可以被称为第一层-1迹线572-1。
同样在第一金属化层M1内,焊料掩模(SM)578(例如,阻焊剂)可以形成在第一层-1迹线572-1以及第一衬底层570上。可以在SMO内的第一层-1迹线572-1上形成结合指焊盘550。外部互连件565(例如,焊球)可以形成在衬底的下表面上(例如,在作为衬底的最低衬底层的第三衬底层590的下表面上)。
在成型物540内,可以形成引线结合件560以将引线结合裸片520与FC裸片510电耦合。例如,引线结合件560的端部可以连接到引线结合裸片520和结合指焊盘550。以此方式,引线结合裸片520可以通过引线结合件560、结合指焊盘550和迹线第一层-1迹线572-1与FC裸片510电耦合。引线结合件560可以由诸如金(Au)、银(Ag)、铜(Cu)等金属形成。
图5的IC封装件500类似于图3的IC封装件300。IC封装件500和300之间的一个主要区别在于迹线的布线。回想在图3中,迹线372可以从结合指焊盘350延伸到整个第一金属化层M1内的衬底的边缘。镀覆线(未示出)可以在用于电解镀覆的第一金属化层M1处与迹线372电耦合。
在图5中,用于镀覆结合指焊盘550的镀覆线的电耦合也发生在第一金属化层M1。然而,简单地将迹线从结合指焊盘550延伸到第一金属化层M1内的衬底的边缘可能是困难的,甚至是不可能的。例如,可能有多条迹线需要在第一金属化层M1内布线,并且将迹线从结合指焊盘550延伸到边缘可能使得难以将其他迹线在第一金属化层M1内布线。
然而,如果用于镀覆的迹线布线可以通过其他金属化层来实现,那么迹线的布线作为一个整体可以更加优化。如图5所示,除了第一层-1迹线572-1之外,第一金属化层M1还可以包括第二层-1迹线572-2、第一层-1过孔574-1和第二层-1过孔574-2。第二层-1迹线572-2可以形成在第一衬底层570上。第一层-1过孔和第二层-1过孔574-1、574-2可以穿过第一衬底层570形成,分别从第一层-1迹线和第二层-1迹线572-1、572-2到第一金属化层M1的下表面。第一层-1迹线和第二层-1迹线572-1、572-2以及第一层1过孔和第二层-1过孔574-1、574-2中的每一者都可以由诸如Cu、Al等导电金属形成。
第二金属化层M2可以包括形成在第二衬底层580上的层-2迹线582。层-2迹线582也可以由导电金属(诸如Cu、Al等)形成。如图所示,从结合指焊盘550到衬底的边缘的镀覆布线可以依次通过第一层-1迹线572-1、第一层-1过孔574-1、层-2迹线582、第二层-1过孔574-2和第二层-1迹线572-2。
第二层-1迹线572-2可以在第一金属化层M1内从内部延伸到衬底的边缘,使得衬底的边缘处的第二层-1迹线572-2与结合指焊盘550电耦合。以此方式,第二层-1迹线572-2可以连接到衬底边缘处的一个或多个镀覆线(未示出)以用于结合指焊盘550的电解镀覆。
当存在多个金属化层时,镀覆线不必总是与第一金属化层M1处的迹线(例如,迹线372、第二层-1迹线572-2等)耦合。例如,关于图5,将层-2迹线582延伸到衬底(未示出)的边缘是一种选择。那么层-2迹线582可以连接到一个或多个镀覆线,以用于结合指焊盘550的镀覆。
图6中示出了图示了根据本公开的一个或多个方面的示例IC封装件600的另一个替代方案。IC封装件600可以包括衬底上的倒装芯片(FC)裸片610(例如,基带调制解调器)、设置在FC裸片610上方的其间具有裸片附接粘合剂630的引线结合裸片620(例如,存储器裸片)、在衬底上和上方包封FC裸片610和引线结合裸片620的成型物640。衬底可以包括一个或多个金属化层(例如,M1、M2、M3等)并且每个金属化层可以包括对应的衬底层(例如,第一衬底层670、第二衬底层680、第三衬底层690等)。
在一个、一些或所有金属化层内,迹线可以被布线成与FC裸片610的FC互连件615(例如,凸块)电耦合。例如,在图6中,在第一金属化层M1内,层-1迹线672可以形成在第一衬底层670上并且被布线为与FC互连件615电耦合。
同样在第一金属化层M1内,可以在层-1迹线672以及第一衬底层670上形成焊料掩模(SM)678(例如,阻焊剂)。结合指焊盘650可以形成在SMO内的层-1迹线672-1上。外部互连件665(例如,焊球)可以形成在衬底的下表面上(例如,在作为衬底的最低衬底层的第三衬底层690的下表面上)。
在成型物640内,可以形成引线结合件660以将引线结合裸片620与FC裸片610电耦合。例如,引线结合件660的端部可以连接到引线结合裸片620和结合指焊盘650。以此方式,引线结合裸片620可以通过引线结合件660、结合指焊盘650和层-1迹线672与FC裸片610电耦合。引线结合件360可以由诸如金(Au)、银(Ag)、铜(Cu)等金属形成。
图6的IC封装件600类似于图3和图5的IC封装件300和500。一个主要区别在于,对于结合指焊盘650的电解镀覆,镀覆线(未示出)可以与除了第一金属化层M1之外的金属化层处的迹线电耦合。
在图6中,除了层-1迹线672之外,第一金属化层M1还可以包括层-1过孔674。层-1过孔674可以穿过第一衬底层370形成。第二金属化层M2可以包括层-2迹线682和层-2过孔684。层-2迹线682可以形成在第二衬底层680上,并且层-2过孔684可以穿过第二衬底层680形成。第三金属化层M3可以包括形成在第三衬底层690上的层-3。层-1迹线672、层-1过孔674、层-2迹线682、层-2过孔684和层-3迹线692中的每一者都可以由诸如铜、铝等导电金属形成。
如图所示,用于从结合指焊盘650到衬底的边缘的镀覆布线可以依次通过层-1迹线672、层-1过孔674、层-2迹线682、层-2过孔684和层-3迹线692。层-3迹线692可以在第三金属化层M3内从内部延伸到衬底的边缘,使得衬底的边缘处的层-3迹线692与结合指焊盘650电耦合。以此方式,层-3迹线692可以在衬底边缘连接到一个或多个镀覆线(未示出)以用于结合指焊盘650的电解镀覆。
图7图示了制造用于IC封装件的衬底的不同阶段的工艺流程700。在框705中,可以施加阻焊剂。在框710中,可以进行等离子体蚀刻。在框715中,可以进行干膜抗蚀剂(DFR)层压,随后在框720中曝光并且在框725中显影。在框730中,可以执行Ni/Au镀覆(例如,以形成结合指焊盘350、550、650)。在框735中,可以剥离衬底。
在框740中,可以执行另一DFR层压,随后是框745中的另一曝光和框750中的另一显影。然后在框755中,可以执行镀条蚀刻,随后在框760中进行剥离并且在框765中进行剥离布线。在框770中,可以应用防腐剂诸如有机可焊性防腐剂(OSP)。在框775中,可以包装衬底。
图8图示了组装IC封装件300、500、600的不同阶段的工艺流程800。在框805中,可以执行裸片准备。在框810中,倒装芯片(FC)裸片310、510、610可以被结合到衬底。在框815中,裸片附接粘合剂330、530、630可以设置在FC裸片310、510、610上。在框820中,引线结合裸片320、520、620可以通过裸片附接粘合剂330、530、630附接到FC裸片310、510、610。
在框825中,可以执行回流,随后在框830中进行助焊剂清洁。在框835中,可以执行反向引线结合件以形成与结合指焊盘350、550、650和引线结合裸片320、520、620连接的引线结合件360、560、660。在框840中,可以形成成型物340、540、640来包封FC裸片310、510、610、引线结合裸片320、520、620和引线结合件360、560、660。
在框845中,可以进行激光标记,随后在框850中进行球安装,并且在框855中进行衬底锯切。在框860中,可以执行FT O/S。在框865中,IC封装件300、500、600可以在框870中被检查和装运。
图9图示了制造IC封装件(诸如IC封装件300、500、600中的任一封装件)的示例方法900的流程图。在框910中,可以形成衬底。
在框920中,倒装芯片(FC)裸片(例如,FC裸片310、510、610)可以设置在衬底上方。
在框930中,引线结合裸片(例如,引线结合裸片320、520、620)可以设置在FC裸片上方。例如,可以使用裸片附接粘合剂(例如,裸片附接粘合剂330、530、630)。
在框940中,可以形成引线结合件(例如,引线结合件360、560、660)以连接到引线结合裸片。
在框950中,可以在衬底上形成成型物以包封FC裸片、引线结合裸片和引线结合件。
在一个方面,衬底可以在框910中形成为包括一个或多个金属化层,该一个或多个金属化层包括第一金属化层(M1)(例如,金属化层M1)。第一金属化层可以包括:第一衬底层(例如,第一衬底层370、570、670);迹线(例如,迹线372、第一层-1迹线572-1、层-1迹线672),形成在第一衬底层上并且在第一金属化层内布线以与一个或多个FC互连件(例如,FC互连件315、515、615)电耦合;以及结合指焊盘(例如,结合指焊盘350、550、650),形成在迹线上。结合指焊盘的形状可以是圆形或基本上圆形。引线结合件可以形成为电连接到结合指焊盘,使得引线结合裸片通过引线结合件、结合指焊盘和迹线与FC裸片电耦合。
第一金属化层还可以包括形成在迹线和第一衬底层上的焊料掩模(例如,焊料掩模378、578、678)。结合指焊盘可以形成在SMO内。
在一个方面,迹线(例如,迹线372)可以从结合指焊盘延伸到第一金属化层内的衬底的边缘(例如,参见图3)。
在另一方面,迹线可以是第一层-1迹线(例如,第一层-1迹线572-1),并且第一金属化层还可以包括形成在第一衬底层(例如,第一衬底层570)上并且在第一金属化层内布线的第二层-1迹线(例如,第二层-1迹线572-2)。第二层-1迹线可以与第一层-1迹线电耦合并且从衬底的内部延伸到第一金属化层内的衬底的边缘(例如,参见图5)。
在又一个方面,迹线可以是层-1迹线(例如,层-1 672),并且衬底还包括在第一金属化层(M1)下面的附加金属化层(例如,第三金属化层M3)。附加金属化层可以包括附加衬底层(例如,第三衬底层690),以及形成在附加衬底层上并且在附加金属化层内布线的附加迹线(例如,层-3迹线692)。附加迹线可以与层-1迹线(672)电耦合,并且从衬底的内部延伸到附加金属化层内的衬底的边缘(例如,参见图6)。
图10图示了根据本公开的各个方面的可以与前述集成电路封装件300、500、600中的任一集成电路封装件集成的各种电子设备。例如,移动电话装置1002、膝上型计算机装置1004和固定位置终端装置1006各自可以被认为是用户设备(UE)并且可以包括并入了如本文所描述的IC封装件300、500、600的装置1000。图10中所示的设备1002、1004、1006仅是示例性的。其他电子设备也可以包括IC封装件300、500、600,包括但不限于一组设备(例如,电子设备),包括存储或检索数据或计算机指令或其任意组合的移动设备、手持式个人通信系统(PCS)单元、便携式数据单元(诸如个人数字助理)、支持全球定位系统(GPS)的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、固定位置数据单元(诸如仪表读取设备)、通信设备、智能手机、平板计算机、计算机、可穿戴设备、服务器、路由器、机动车辆中实现的电子设备、物联网(IoT)设备或任何其他设备。
前述公开的设备和功能可以被设计并且配置到存储在计算机可读介质上的计算机文件(例如,RTL、GDSII、GERBER等)中。一些或所有这些文件可以提供到基于这些文件制造设备的制造处理者。所得产品可以包括半导体晶片,然后如本文所描述切割成半导体裸片并且封装件。
以下提供了本公开的示例的概述:
示例1:一种集成电路(IC)封装件,包括:衬底;倒装芯片(FC)裸片,设置在衬底上;引线结合裸片,设置在FC裸片上方;引线结合件,连接到引线结合裸片;以及成型物,在衬底上并且包封FC裸片、引线结合裸片和引线结合件;并且其中衬底包括一个或多个金属化层,金属化层包括第一金属化层,第一金属化层包括:第一衬底层;迹线,形成在第一衬底层上并且在第一金属化层内布线以与FC裸片的一个或多个FC互连件电耦合;以及结合指焊盘,形成在迹线上,结合指焊盘的形状基本上是圆形的,并且其中引线结合件电连接到结合指焊盘,使得引线结合裸片通过引线结合件、结合指焊盘和迹线与FC裸片电耦合。
示例2:根据示例1所述的IC封装件,其中第一金属化层还包括:焊料掩模,形成在迹线上和第一衬底层上,其中结合指焊盘形成在焊料掩模开口(SMO)内,该焊料掩模开口限定第一衬底层上方未被焊料掩模覆盖的区域。
示例3:根据示例2所述的IC封装件,其中在结合指焊盘和焊料掩模之间没有间隙。
示例4:根据示例1至3中任一者所述的IC封装件,其中迹线从结合指焊盘延伸到第一金属化层内的衬底的边缘。
示例5:根据示例1至3中任一者所述的IC封装件,其中迹线是第一层-1迹线,并且其中第一金属化层还包括:第二层-1迹线,形成在第一衬底层上并且在第一金属化层内布线,该第二层-1迹线与第一层-1迹线电耦合并且在第一金属化层内从衬底的内部延伸到衬底的边缘。
示例6:根据示例5所述的IC封装件,其中第一金属化层还包括:第一层-1过孔,从第一层-1迹线到第一金属化层的下表面穿过第一衬底层形成;以及第二层-1过孔,穿过第一衬底层从第二层-1迹线到第一金属化层的下表面形成,其中衬底还包括在第一金属化层下面的第二金属化层,第二金属化层包括:第二衬底层;以及层-2迹线,形成在第二衬底层上并且在第二金属化层内布线以与第一层-1过孔和第二层-1过孔电耦合,使得结合指焊盘依次通过第一层-1迹线、第一层-1过孔、层-2迹线和第二层-1过孔与第二层-1迹线电耦合。
示例7:根据示例1至3中任一者所述的IC封装件,其中迹线是层-1迹线,并且其中衬底还包括在第一金属化层下面的附加金属化层,该附加金属化层包括:附加衬底层;以及形成在附加衬底层上并且在附加金属化层内布线的附加迹线,该附加迹线与层-1迹线电耦合并且在附加金属化层内从衬底的内部延伸到衬底的边缘。
示例8:根据示例7所述的IC封装件,其中附加金属化层是第三金属化层,附加衬底层是第三衬底层,并且附加迹线是层-3迹线,其中衬底还包括在第一金属化层和第三金属化层之间的第二金属化层,其中第一金属化层还包括:层-1过孔,从层-1迹线到第一金属化层的下表面穿过第一衬底层形成,其中第二金属化层包括:第二衬底层;层-2迹线,形成在第二衬底层上并且在第二金属化层内布线;以及层-2过孔,穿过第二衬底层从层-2迹线到第二金属化层的下表面形成,其中结合指焊盘依次穿过层-1迹线、层-1过孔、层-2迹线和层-2过孔与层-3迹线电耦合。
示例9:根据示例1至8中任一者所述的IC封装件,其中裸片-焊盘距离小于边缘-焊盘距离,裸片-焊盘距离是从引线结合裸片到结合指焊盘的距离,并且边缘-焊盘距离是从衬底的边缘到结合指焊盘的距离。
示例10:根据示例1至9中任一者所述的IC封装件,其中IC封装件包括在FC裸片上方的多个引线结合裸片,其中多个引线结合裸片中的每个引线结合裸片通过对应的引线结合件和结合指焊盘电耦合到FC裸片。
示例11:根据示例1至10中任一者所述的IC封装件,其中迹线由铜(Cu)或铝(Al)形成。
示例12:根据示例1至11中任一者所述的IC封装件,其中结合指焊盘是镀覆金属。
示例13:根据示例12所述的IC封装件,其中镀覆金属包括镀镍或镀金或两者。
示例14:根据示例1至13中任一者所述的IC封装件,其中引线结合件是反向引线结合件,其中一端被球形结合到结合指焊盘并且另一端被针脚式结合到引线结合裸片。
示例15:根据示例1至14中任一者所述的IC封装件,其中FC裸片是基带调制解调器裸片。
示例16:根据示例1至15中任一者所述的IC封装件,其中引线结合裸片是存储器裸片。
示例17:根据示例1至16中任一者所述的IC封装件,其中该IC封装件被并入到选自由以下组成的组的装置中:音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、物联网(IoT)设备、膝上型计算机、服务器和机动车辆中的设备。
示例18:一种制造集成电路(IC)封装件的方法,该方法包括:形成衬底;在衬底上设置倒装芯片(FC)裸片;将引线结合裸片设置在FC裸片上方;形成引线结合件,该引线结合件耦合到引线结合裸片;以及在衬底上形成成型物,该成型物包封FC裸片、引线结合裸片和引线结合件,其中衬底被形成为包括一个或多个金属化层,该一个或多个金属化层包括第一金属化层,该第一金属化层包括:第一衬底层;迹线,形成在第一衬底层上并且在第一金属化层内布线以与FC裸片的一个或多个FC互连件电耦合;以及结合指焊盘,形成在迹线上,结合指焊盘的形状基本上是圆形的,并且其中引线结合件被形成为电连接到结合指焊盘,使得引线结合裸片通过引线结合件、结合指焊盘和迹线与FC裸片电耦合。
示例19:根据示例18所述的方法,其中形成衬底使得第一金属化层还包括:焊料掩模,形成在迹线上和第一衬底层上,其中结合指焊盘形成在焊料掩模开口(SMO)内,该焊料掩模开口限定第一衬底层上未被焊料掩模覆盖的区域。
示例20:根据示例19所述的方法,其中在结合指焊盘和焊料掩模之间没有间隙。
示例21:根据示例18至20中任一者所述的方法,其中衬底被形成为使得迹线从结合指焊盘延伸到第一金属化层内的衬底的边缘。
示例22:根据示例18至20中任一者所述的方法,其中迹线是第一层-1迹线,并且其中衬底被形成为使得第一金属化层还包括:第二层-1迹线,形成在第一衬底层上并且在第一金属化层内布线,第二层-1迹线与第一层-1迹线电耦合并且在第一金属化层内从衬底的内部延伸到衬底的边缘。
示例23:根据示例22所述的方法,其中衬底被形成为使得第一金属化层还包括:第一层-1过孔,从第一层-1迹线到第一金属化层的下表面穿过第一衬底层形成;以及第二层-1过孔,穿过第一衬底层从第二层-1迹线到第一金属化层的下表面形成,其中衬底被形成为还包括在第一金属化层下面的第二金属化层,第二金属化层包括:第二衬底层;以及层-2迹线,形成在第二衬底层上并且在第二金属化层内布线以与第一层-1过孔和第二层-1过孔电耦合,使得结合指焊盘依次通过第一层-1迹线、第一层-1过孔、层-2迹线和第二层-1过孔与第二层-1迹线电耦合。
示例24:根据示例18至20中任一者所述的方法,其中迹线是层-1迹线,并且其中衬底被形成为还包括在第一金属化层下面的附加金属化层,该附加金属化层包括:附加衬底层;以及附加迹线,形成在附加衬底层上并且在附加金属化层内布线,该附加迹线与层-1迹线电耦合并且在附加金属化层内从衬底的内部延伸到衬底的边缘。
示例25:根据示例24所述的方法,其中附加金属化层是第三金属化层,附加衬底层是第三衬底层,并且附加迹线是层-3迹线,其中被衬底形成为还包括在第一金属化层和第三金属化层之间的第二金属化层,其中衬底被形成为使得第一金属化层还包括:层-1过孔,从层-1迹线到第一金属化层的下表面穿过第一衬底层形成,其中衬底被形成为使得第二金属化层包括:第二衬底层;层-2迹线,形成在第二衬底层上并且在第二金属化层内布线;以及层-2过孔,穿过第二衬底层从层-2迹线到第二金属化层的下表面形成,其中结合指焊盘被形成为依次穿过层-1迹线、层-1过孔、层-2迹线和层-2过孔与层-3迹线电耦合。
示例26:根据示例18至25中任一者所述的方法,其中裸片-焊盘距离小于边缘-焊盘距离,裸片-焊盘距离是从引线结合裸片到结合指焊盘的距离,并且边缘-焊盘距离是从衬底的边缘到结合指焊盘的距离。
示例27:根据示例18至26中任一者所述的方法,其中在FC裸片上方形成多个引线结合裸片,其中多个引线结合裸片中的每个引线结合裸片通过对应的引线结合件和结合指焊盘电耦合到FC裸片。
示例28:根据示例18至27中任一者所述的方法,其中引线结合件形成为反向引线结合件,其中一端被球形结合到结合指焊盘并且另一端被针脚式结合到引线结合裸片。
如本文所用,术语“用户设备”(或“UE”)、“用户装置”、“用户终端”、“客户端设备”、“通信设备”、“无线设备”、“无线通信设备”、“手持设备”、“移动设备”、“移动终端”、“移动站”、“手机”、“接入终端”、“订户设备”、“订户终端”、“订户站”、“终端”及其变体可以互换地指代能够接收无线通信和/或导航信号的任何合适的移动设备或固定设备。这些术语包括但不限于音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器、机动车辆中的汽车设备和/或通常由人携带和/或具有通信能力(例如,无线、蜂窝、红外、短程无线电等)的其他类型的便携式电子设备。这些术语还旨在包括与另一设备通信的设备,该另一设备可以诸如通过短程无线、红外、有线连接或其他连接来接收无线通信和/或导航信号,而不管卫星信号接收、辅助数据接收和/或位置相关处理是在该设备处还是另一设备处发生。此外,这些术语旨在包括能够通过无线接入网(RAN)与核心网通信的所有设备,包括无线和有线通信设备,并且通过核心网,UE可以与诸如互联网的外部网络以及其他UE连接。当然,对于UE来说,连接到核心网和/或互联网的其他机制也是可能的,诸如通过有线接入网、无线局域网(WLAN)(例如,基于IEEE 802.11等)等。UE可以由多种类型的设备(包括但不限于印刷电路(PC)卡、紧凑型快闪设备、外部或内部调制解调器、无线或有线电话、智能手机、平板计算机、跟踪设备、资产标签等)中的任一种来实现。UE可以通过其向RAN发送信号的通信链路被称为上行链路信道(例如,反向业务信道、反向控制信道、接入信道等)。RAN可以通过其向UE发送信号的通信链路被称为下行链路或前向链路信道(例如,寻呼信道、控制信道、广播信道、前向业务信道等)。如本文所用,术语业务信道(TCH)可以指上行链路/反向或下行链路/前向业务信道。
电子设备之间的无线通信可以基于不同的技术,诸如码分多址(CDMA)、W-CDMA、时分多址(TDMA)、频分多址(FDMA)、正交频分复用(OFDM)、全球移动通信系统(GSM)、3GPP长期演进(LTE)、5G新无线电、蓝牙(BT)、蓝牙低能量(BLE)、IEEE 802.11(WiFi)和IEEE802.15.4(Zigbee/Thread)或可以在无线通信网络或数据通信网络中使用的其他协议。蓝牙低功耗(也称为蓝牙LE、BLE和蓝牙智能)是由蓝牙特别兴趣小组设计和销售的无线个人区域网技术,旨在提供显著降低的功耗和成本,同时保持类似的通信范围。随着蓝牙核心规范版本4.0的采用,BLE在2010年被合并到主要的蓝牙标准中,并且在蓝牙5中得到更新。
本文使用的词语“示例”表示“用作示例、实例或说明”。本文描述为“示例”的任何细节都不应被解释为优于其他示例。同样,术语“示例”并且不意味着所有示例都包括所讨论的特征、优点或操作模式。此外,特定特征和/或结构可以与一个或多个其他特征和/或结构组合。此外,本文所描述的装置的至少一部分可以被配置为执行本文所描述的方法的至少一部分。
应注意的是,术语“连接”、“耦合”或其任何变体表示元件之间的任何直接或间接的连接或耦合,并且可以涵盖经由中间元件“连接”或“耦合”在一起的两个元件之间的中间元件的存在,除非该连接被明确公开为直接连接。
本文中对使用诸如“第一”、“第二”等名称的元件的任何引用并不限制这些元件的数量和/或顺序。而是,这些名称被用作区分两个或多个元件和/或元件示例的便利方法。此外,除非另有说明,一组元件可以包括一个或多个元件。
本领域的技术人员将会理解,可以使用多种不同的技术和方法中的任一种来表示信息和信号。例如,贯穿以上描述可能提及的数据、指令、命令、信息、信号、位、符号和芯片可以由电压、电流、电磁波、磁场或粒子、光场或粒子或其任意组合来表示。
本申请中陈述或说明的任何内容都不旨在将任何部件、动作、特征、益处、优点或等效物奉献给公众,无论此部件、动作、特征、益处、优点或等效物是否在权利要求中陈述。
在上面的详细描述中,可以看出不同的特征在示例中被组合在一起。此公开方式不应被理解为要求保护的示例具有比相应权利要求中明确提到的更多的特征。而是,本公开可以包括少于所公开的单个示例的所有特征。因此,下面的权利要求应被视为包括在说明书中,其中每个权利要求本身可以作为单独的示例。尽管每个权利要求本身可以代表单独的示例,但是应注意的是,尽管从属权利要求在权利要求中可以指与一个或一个或多个权利要求的特定组合,但是其他示例也可以包括或包括该从属权利要求与任何其他从属权利要求的主题的组合,或任何特征与其他从属和独立权利要求的组合。本文提出了此类组合,除非明确表示不打算使用特定的组合。此外,还旨在权利要求的特征可以包括在任何其他独立权利要求中,即使该权利要求不直接从属于该独立权利要求。
此外应注意的是,说明书或权利要求书中公开的方法、系统和装置可以由包括用于执行所公开的方法的相应动作和/或功能的部件的设备来实现。
此外,在一些示例中,单个动作可以被细分成一个或多个子动作,或包括一个或多个子动作。此类子动作可以包括在单独动作的公开中,并且是单独动作的公开的一部分。
尽管前述公开内容图示了本公开内容的说明性示例,但是应注意的是,在不脱离由所附权利要求限定的本公开内容的范围的情况下,可以本文进行各种改变和修改。根据本文所描述的公开内容的示例的方法权利要求的功能和/或动作不需要以任何特定的顺序来执行。另外,将不详细描述或省略众所周知的元件,以免混淆本文所公开的方面和示例的相关细节。此外,尽管可以单数形式描述或要求保护本公开的元件,但是除非明确声明限于单数形式,否则复数形式也是可以考虑的。
Claims (28)
1.一种集成电路(IC)封装件,包括:
衬底;
倒装芯片(FC)裸片,设置在所述衬底上;
引线结合裸片,设置在所述FC裸片上方;
引线结合件,连接到所述引线结合裸片;以及
成型物,在所述衬底上并且包封所述FC裸片、所述引线结合裸片和所述引线结合件;并且
其中所述衬底包括一个或多个金属化层,所述一个或多个金属化层包括第一金属化层,所述第一金属化层包括:
第一衬底层;
迹线,形成在所述第一衬底层上并且在所述第一金属化层内布线以与所述FC裸片的一个或多个FC互连件电耦合;以及
结合指焊盘,形成在所述迹线上,所述结合指焊盘的形状基本上是圆形的,并且
其中所述引线结合件电连接到所述结合指焊盘,使得所述引线结合裸片通过所述引线结合件、所述结合指焊盘和所述迹线与所述FC裸片电耦合。
2.根据权利要求1所述的IC封装件,其中所述第一金属化层还包括:
焊料掩模,形成在所述迹线上和所述第一衬底层上,
其中所述结合指焊盘形成在焊料掩模开口(SMO)内,所述焊料掩模开口限定所述第一衬底层上方未被所述焊料掩模覆盖的区域。
3.根据权利要求2所述的IC封装件,其中所述结合指焊盘和所述焊料掩膜之间没有间隙。
4.根据权利要求1所述的IC封装件,其中所述迹线从所述结合指焊盘延伸到所述第一金属化层内的所述衬底的边缘。
5.根据权利要求1所述的IC封装件,
其中所述迹线是第一层-1迹线,并且
其中所述第一金属化层还包括:
第二层-1迹线,形成在所述第一衬底层上并且在所述第一金属化层内布线,所述第二层-1迹线与所述第一层-1迹线电耦合并且在所述第一金属化层内从所述衬底的内部延伸到所述衬底的边缘。
6.根据权利要求5所述的IC封装件,
其中所述第一金属化层还包括:
第一层-1过孔,从所述第一层-1迹线穿过所述第一衬底层到所述第一金属化层的下表面形成;以及
第二层-1过孔,从所述第二层-1迹线穿过所述第一衬底层到所述第一金属化层的所述下表面形成,以及
其中所述衬底还包括位于所述第一金属化层下方的第二金属化层,所述第二金属化层包括:
第二衬底层;以及
层-2迹线,形成在所述第二衬底层上并且在所述第二金属化层内布线以与所述第一层-1过孔和所述第二层-1过孔电耦合,使得所述结合指焊盘依次通过所述第一层-1迹线、所述第一层-1过孔、所述层-2迹线和所述第二层-1过孔与所述第二层-1迹线电耦合。
7.根据权利要求1所述的IC封装件,
其中所述迹线是层-1迹线,并且
其中所述衬底还包括位于所述第一金属化层下方的附加金属化层,所述附加金属化层包括:
附加衬底层;以及
附加迹线,形成在所述附加衬底层上并且在所述附加金属化层内布线,所述附加迹线与所述层-1迹线电耦合并且在所述附加金属化层内从所述衬底的内部延伸到所述衬底的边缘。
8.根据权利要求7所述的IC封装件,
其中所述附加金属化层是第三金属化层,所述附加衬底层是第三衬底层,并且所述附加迹线是层-3迹线,
其中所述衬底还包括在所述第一金属化层和所述第三金属化层之间的第二金属化层,
其中所述第一金属化层还包括:
层-1过孔,从所述层-1迹线穿过所述第一衬底层到所述第一金属化层的下表面形成,
其中所述第二金属化层包括:
第二衬底层;
层-2迹线,形成在所述第二衬底层上并且在所述第二金属化层内布线;以及
层-2过孔,从所述层-2迹线穿过所述第二衬底层到所述第二金属化层的下表面形成,以及
其中所述结合指焊盘依次通过所述层-1迹线、所述层-1过孔、所述层-2迹线和所述层-2过孔与所述层-3迹线电耦合。
9.根据权利要求1所述的IC封装件,其中裸片-焊盘距离小于边缘-焊盘距离,所述裸片-焊盘距离是从所述引线结合裸片到所述结合指焊盘的距离并且所述边缘-焊盘距离是从所述衬底的边缘到所述结合指焊盘的距离。
10.根据权利要求1所述的IC封装件,其中所述IC封装件包括位于所述FC裸片上方的多个引线结合裸片,其中所述多个引线结合裸片中的每个引线结合件裸片通过对应的所述引线结合件和所述结合指焊盘电耦合到所述FC裸片。
11.根据权利要求1所述的IC封装件,其中所述迹线由铜(Cu)或铝(Al)形成。
12.根据权利要求1所述的IC封装件,其中所述结合指焊盘是镀覆金属。
13.根据权利要求12所述的IC封装件,其中所述镀覆金属包括镀镍或镀金或两者。
14.根据权利要求1所述的IC封装件,其中所述引线结合件是反向引线结合件,其中一端被球形结合到所述结合指焊盘并且另一端被针脚式结合到所述引线结合裸片。
15.根据权利要求1所述的IC封装件,其中所述FC裸片是基带调制解调器裸片。
16.根据权利要求1所述的IC封装件,其中所述引线结合裸片是存储器裸片。
17.根据权利要求1所述的IC封装件,其中所述IC封装件被并入到选自由以下组成的组的装置中:音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、移动设备、移动电话、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、物联网(IoT)设备、膝上型计算机、服务器和机动车辆中的设备。
18.一种制造集成电路(IC)封装件的方法,所述方法包括:
形成衬底;
在所述衬底上设置倒装芯片(FC)裸片;
将引线结合裸片设置在所述FC裸片上方;
形成引线结合件,所述引线结合件连接到所述引线结合裸片;以及
在所述衬底上形成成型物,所述成型物包封所述FC裸片、所述引线结合裸片和所述引线结合件,
其中所述衬底被形成为包括一个或多个金属化层,所述一个或多个金属化层包括第一金属化层,所述第一金属化层包括:
第一衬底层;
迹线,形成在所述第一衬底层上并且在所述第一金属化层内布线以与所述FC裸片的一个或多个FC互连件电耦合;以及
结合指焊盘,形成在所述迹线上,所述结合指焊盘的形状基本上是圆形的,以及
其中所述引线结合件被形成为电连接到所述结合指焊盘,使得所述引线结合裸片通过所述引线结合件、所述结合指焊盘和所述迹线与所述FC裸片电耦合。
19.根据权利要求18所述的方法,其中所述衬底被形成为使得所述第一金属化层还包括:
焊料掩模,形成在所述迹线上和所述第一衬底层上,
其中所述结合指焊盘形成在焊料掩模开口(SMO)内,所述焊料掩模开口限定所述第一衬底层上方未被所述焊料掩模覆盖的区域。
20.根据权利要求19所述的方法,其中在所述结合指焊盘和所述焊料掩模之间没有间隙。
21.根据权利要求18所述的方法,其中所述衬底被形成为使得所述迹线从所述结合指焊盘延伸到所述第一金属化层内的所述衬底的边缘。
22.根据权利要求18所述的方法,
其中所述迹线是第一层-1迹线,并且
其中所述衬底被形成为使得所述第一金属化层还包括:
第二层-1迹线,形成在所述第一衬底层上并且在所述第一金属化层内布线,所述第二层-1迹线与所述第一层-1迹线电耦合并且在所述第一金属化层内从所述衬底的内部延伸到所述衬底的边缘。
23.根据权利要求22所述的方法,
其中所述衬底被形成为使得所述第一金属化层还包括:
第一层-1过孔,从所述第一层-1迹线穿过所述第一衬底层到所述第一金属化层的下表面形成;以及
第二层-1过孔,从所述第二层-1迹线穿过所述第一衬底层到所述第一金属化层的所述下表面形成,以及
其中所述衬底被形成为还包括位于所述第一金属化层下方的第二金属化层,所述第二金属化层包括:
第二衬底层;以及
层-2迹线,形成在所述第二衬底层上并且在所述第二金属化层内布线以与所述第一层-1过孔和所述第二层-1过孔电耦合,使得所述结合指焊盘依次通过所述第一层-1迹线、所述第一层-1过孔、所述层-2迹线和所述第二层-1过孔与所述第二层-1迹线电耦合。
24.根据权利要求18所述的方法,
其中所述迹线是层-1迹线,并且
其中所述衬底被形成为还包括在所述第一金属化层下方的附加金属化层,所述附加金属化层包括:
附加衬底层;以及
附加迹线,形成在所述附加衬底层上并且在所述附加金属化层内布线,所述附加迹线与所述层-1迹线电耦合并且在所述附加金属化层内从所述衬底的内部延伸到所述衬底的边缘。
25.根据权利要求24所述的方法,
其中所述附加金属化层是第三金属化层,所述附加衬底层是第三衬底层,并且所述附加迹线是层-3迹线,
其中所述衬底被形成为还包括在所述第一金属化层和所述第三金属化层之间的第二金属化层,
其中所述衬底被形成为使得所述第一金属化层还包括:
层-1过孔,从所述层-1迹线穿过所述第一衬底层到所述第一金属化层的下表面形成,
其中所述衬底被形成为使得所述第二金属化层包括:
第二衬底层;
层-2迹线,形成在所述第二衬底层上并且在所述第二金属化层内布线;以及
层-2过孔,从所述层-2迹线穿过所述第二衬底层到所述第二金属化层的下表面形成,以及
其中所述结合指焊盘被形成为依次通过所述层-1迹线、所述层-1过孔、所述层-2迹线和所述层-2过孔与所述层-3迹线电耦合。
26.根据权利要求18所述的方法,其中裸片-焊盘距离小于边缘-焊盘距离,所述裸片-焊盘距离是从所述引线结合裸片到所述结合指焊盘的距离并且所述边缘-焊盘距离是从所述衬底的边缘到所述结合指焊盘的距离。
27.根据权利要求18所述的方法,其中多个引线结合件裸片形成在所述FC裸片上方,其中所述多个引线结合裸片中的每个引线结合件裸片通过对应的所述引线结合件和所述结合指焊盘电耦合到所述FC裸片。
28.根据权利要求18所述的方法,其中所述引线结合件形成为反向引线结合件,其中一端被球形结合到所述结合指焊盘并且另一端被针脚式结合到所述引线结合裸片。
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