JP2023520649A - 表示アクティブエリアの穴の周囲の境界幅の低減 - Google Patents
表示アクティブエリアの穴の周囲の境界幅の低減 Download PDFInfo
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Abstract
Description
Claims (20)
- アクティブエリアに形成された表示画素の第1の行と、
前記アクティブエリア内に形成された表示画素の第2の行と、
前記アクティブエリア内の非アクティブ領域と、
前記第1の行の表示画素に結合された第1の行制御線に制御信号を出力し、前記第2の行の表示画素に結合された第2の行制御線に前記制御信号を出力するように構成されたディスプレイドライバ回路と、を備え、前記第1および第2の行制御線が、前記非アクティブ領域によってルーティングされているセグメントにマージされている、ディスプレイ回路系。 - 前記非アクティブ領域が、穴を含む、請求項1に記載のディスプレイ回路系。
- 前記非アクティブ領域が、貫通穴を含む、請求項2に記載のディスプレイ回路系。
- 前記非アクティブ領域が、光学窓を含む、請求項2に記載のディスプレイ回路系。
- 前記マージされたセグメントが、前記穴の境界の周囲にルーティングされている、請求項2に記載のディスプレイ回路系。
- 前記マージされたセグメントが、前記穴を直接横切ってルーティングされている、請求項2に記載のディスプレイ回路系。
- 前記ディスプレイドライバ回路が、前記制御信号を前記第1および第2の行制御線に同時に出力するようにさらに構成されている、請求項1に記載のディスプレイ回路系。
- 前記マージされたセグメントに結合されており、前記第1および第2の行制御線に対する寄生負荷を増加させるように構成されたダミー回路をさらに備える、
請求項1に記載のディスプレイ回路系。 - 前記マージされたセグメントが、第1のノードと第2のノードとの間に結合されており、前記第1のノードが、前記第1および第2の行制御線に接続されており、前記マージされたセグメントが、前記第2のノードにおいて少なくとも第1および第2の追加の行制御線に分割されている、請求項1に記載のディスプレイ回路系。
- 表示画素の前記第1の行に結合された第3の行制御線に追加の制御信号を出力し、表示画素の前記第2の行に結合された第4の行制御線に前記追加の制御信号を出力するように構成された追加のディスプレイドライバ回路をさらに備え、前記第3および第4の行制御線が、前記非アクティブ領域によってルーティングされている追加のセグメントにマージされる、
請求項1に記載のディスプレイ回路系。 - 前記非アクティブ領域が、前記ディスプレイドライバ回路と前記追加のディスプレイドライバ回路との間に物理的に介在している、請求項10に記載のディスプレイ回路系。
- 前記アクティブエリア内に形成された表示画素の第3の行をさらに備え、前記ディスプレイドライバ回路が、前記制御信号を表示画素の前記第3の行に結合された第3の行制御線に出力するようにさらに構成されており、前記マージされたセグメントもまた、前記第3の行制御線に接続されている、
請求項1に記載のディスプレイ回路系。 - 前記非アクティブ領域が、前記非アクティブ領域の周囲の前記アクティブエリアのサイズを増加させるように最適化された先細形状を有する、請求項1に記載のディスプレイ回路系。
- 前記非アクティブ領域が非対称である、請求項1に記載のディスプレイ回路系。
- ディスプレイであって、
アクティブエリアに形成された表示画素と、
前記アクティブエリアによって少なくとも部分的に囲まれた非アクティブ領域と、
前記非アクティブ領域の第1の側の前記アクティブエリアの第1の部分に形成された前記表示画素の第1のグループに結合された第1のルーティングセグメントと、
前記非アクティブ領域の前記第1の側の前記アクティブエリアの前記第1の部分に形成された前記表示画素の第2のグループに結合された第2のルーティングセグメントであって、前記第1および第2のルーティングセグメントが、短絡セグメントを介してノードにおいて接続されている、第2のルーティングセグメントと、
前記ノードに接続されており、前記非アクティブ領域によってルーティングされているマージされたセグメントと、を備える、ディスプレイ。 - 前記非アクティブ領域の第2の側の前記アクティブエリアの第2の部分に形成された前記表示画素の第3のグループに結合された第3のルーティングセグメントと、
前記非アクティブ領域の前記第2の側の前記アクティブエリアの前記第2の部分に形成された前記表示画素の第4のグループに結合された第4のルーティングセグメントと、をさらに備え、前記第3および第4のルーティングセグメントが、ファンアウトノードにおいて前記マージされたセグメントに接続されており、前記第1のルーティングセグメントおよび前記第3のルーティングセグメントが、表示画素の同じ行に結合されている、
請求項15に記載のディスプレイ。 - 前記第1のルーティングセグメントが、前記第2のルーティングセグメントと平行であり、
表示画素の前記第1のグループおよび表示画素の前記第2のグループは、前記アクティブエリア内の表示画素の隣接または非隣接行に対応している、
請求項15に記載のディスプレイ。 - ディスプレイであって、
アクティブエリア内に形成された画素のアレイと、
前記アクティブエリアによって少なくとも部分的に囲まれた非アクティブ領域であって、前記アクティブエリアと重複しない境界領域を有する、非アクティブ領域と、
前記ディスプレイを横切って第1の方向に延在しており、前記非アクティブ領域の前記境界領域内に延在している第1のルーティング線と、
前記ディスプレイを横切って第2の方向に延在しており、前記非アクティブ領域の前記境界領域内に延在していない第2のルーティング線と、を備える、ディスプレイ。 - 前記第2の方向が、前記第1の方向に垂直である、請求項18に記載のディスプレイ。
- 前記第2のルーティング線が、アノード層、ソース-ドレイン金属ルーティング層、タッチセンサ層、および基板層の上方かつ低温ポリシリコン層の下方に形成された埋め込み金属層からなるグループから選択された層を使用して形成されている、請求項18に記載のディスプレイ。
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