JP2023504000A - 基板接合 - Google Patents
基板接合 Download PDFInfo
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- JP2023504000A JP2023504000A JP2022530817A JP2022530817A JP2023504000A JP 2023504000 A JP2023504000 A JP 2023504000A JP 2022530817 A JP2022530817 A JP 2022530817A JP 2022530817 A JP2022530817 A JP 2022530817A JP 2023504000 A JP2023504000 A JP 2023504000A
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- substrate
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
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- 238000007517 polishing process Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
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- 229910002601 GaN Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 239000010931 gold Substances 0.000 description 1
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Abstract
Description
本開示は、2つの基板の接合に関する。特に、本開示は、III族窒化物を含む基板の接合に関する。
いくつかの電子デバイス、たとえばディスプレイ、を製造する場合、所望の回路、半導体コンポーネント、および電気相互接続部のすべてを設けるために広範囲にわたる材料の堆積が必要となる可能性がある。いくつかの電子デバイスの場合、半導体コンポーネントは、駆動回路および電気相互接続部が設けられ得る基板とは別個の基板上に作製される可能性がある。したがって、電子デバイスは、電子回路が設けられた複数の基板を含み得る。これらの基板は互いに接合されてもよく、これら2つの基板の間に電気接続部が設けられている。
本開示の第1の局面に従うと、接合用の基板を準備する方法が提供される。当該方法は、
i)基板の基板表面に凹部を形成するステップと、
ii)接合可能な誘電体層を基板の基板表面上に形成するステップとを含み、当該接合可能な誘電体層は、当該接合可能な誘電体層のうち当該基板表面とは反対側に接合面を有しており、当該凹部および当該接合可能な誘電体層は、誘電体空隙体積を有する誘電体空隙を規定しており、当該方法はさらに、
iii)当該誘電体空隙体積内で当該基板に電気的に接触するように構成されたプラグを形成するステップを含み、当該プラグは、当該誘電体空隙体積よりも小さいプラグ体積を有し、当該プラグは、当該誘電体空隙から当該接合面を越えて当該接合面に概ね垂直な方向に延在しており、当該方法はさらに、
iv)当該プラグの接触面が当該接合面と同一平面になるように、対向する平面同士の間で当該基板を圧縮することによって当該プラグをコイニングするステップを含む。
i)接合用の第1の基板を準備するステップを含み、当該準備するステップは、
当該第1の基板の第1の基板表面に第1の凹部を形成するステップと、
当該第1の基板の第1の基板表面上に第1の接合可能な誘電体層を形成するステップとを含み、当該第1の接合可能な誘電体層は、当該第1の接合可能な誘電体層のうち当該第1の基板表面とは反対側に第1の接合面を有し、当該第1の凹部および当該第1の接合可能な誘電体層は、第1の誘電体空隙体積を有する第1の誘電体空隙を規定しており、当該準備するステップはさらに、
当該第1の誘電体空隙体積内で当該第1の基板に電気的に接触するように構成された第1のプラグを形成するステップを含み、当該第1のプラグは、当該第1の誘電体空隙体積よりも小さい第1のプラグ体積を有し、当該第1のプラグは、当該第1の誘電体空隙から当該第1の接合面を越えて当該第1の接合面に概ね垂直な方向に延在しており、当該準備するステップはさらに、
対向する平面同士の間で当該第1の基板を圧縮することによって当該第1のプラグをコイニングするステップを含み、当該方法はさらに、
ii)接合用の当該第2の基板を設けるステップを含み、当該第2の基板は、
当該第2の基板の第2の表面上に設けられた第2の接合可能な誘電体層および第2の接触層を含み、当該第2の接触層は、当該第2の接合可能な誘電体層の第2の誘電体表面と同一平面上にあって第2の接合面を形成する第2の接触面を有しており、当該方法はさらに、
iii)当該第1のプラグが第2の接触層と位置合わせされるように、当該第1の基板の当該第1の接合面を当該第2の基板の当該第2の接合面の反対側と位置合わせするステップと、
iv)当該第1の基板の当該第1の接合面を当該第2の基板の当該第2の接合面に接触させ、圧縮力下で当該第1のプラグと当該第2の接触層との間に接合部を形成するステップとを含む。
当該第2の基板の当該第2の基板表面に第2の凹部を形成するステップと、
当該第2の基板の当該第2の基板表面上に当該第2の接合可能な誘電体層を形成するステップとを含み、当該第2の接合可能な誘電体層は、当該第2の接合可能な誘電体層のうち第2の基板表面の反対側に第2の接合面を有し、当該第2の凹部および当該第2の接合可能な誘電体層は、第2の誘電体空隙体積を有する第2の誘電体空隙を規定しており、当該第2の基板を設けるステップはさらに、
当該第2の誘電体空隙体積において当該第2の基板に電気的に接触するように構成された第2のプラグを形成するステップを含み、当該第2のプラグは、当該第2の誘電体空隙体積よりも小さい第2のプラグ体積を有し、当該第2のプラグは、当該第2の誘電体空隙から当該第2の接合面を越えて当該第2の接合面に概ね垂直な方向に延在しており、当該第2の基板を設けるステップはさらに、
当該第2のプラグが、当該第2の接合面と同一平面上にある当該第2の接触面を有する当該第2の接触層を形成するように、対向する平面同士の間で当該第2の基板を圧縮することによって当該第2のプラグをコイニングするステップを含む。
ここで、以下の非限定的な図に関連付けて本開示を説明する。本開示のさらに別の利点は、これら図と併せて検討する際に詳細な説明を参照することによって明らかになる。
本開示の実施形態に従うと、基板接合用の基板10を準備する方法が提供される。
Claims (15)
- 基板接合用の基板を準備する方法であって、
前記基板の基板表面に凹部を形成するステップと、
接合可能な誘電体層を前記基板の前記基板表面上に形成するステップとを含み、前記接合可能な誘電体層は、前記接合可能な誘電体層のうち前記基板表面とは反対側に接合面を有しており、前記凹部および前記接合可能な誘電体層は、誘電体空隙体積を有する誘電体空隙を規定しており、前記方法はさらに、
前記誘電体空隙体積内で前記基板に電気的に接触するように構成されたプラグを形成するステップを含み、前記プラグは、前記誘電体空隙体積よりも小さいプラグ体積を有し、前記プラグは、前記誘電体空隙から前記接合面を越えて前記接合面に概ね垂直な方向に延在しており、前記方法はさらに、
前記プラグの接触面が前記接合面と同一平面になるように、対向する平面同士の間で前記基板を圧縮することによって前記プラグをコイニングするステップを含む、方法。 - 前記プラグは、前記誘電体空隙から前記接合面を越えて5μm以下だけ延在する、請求項1に記載の、基板を準備する方法。
- コイニング後、前記プラグは、前記接合面と同一平面上にあり10μm×10μm未満である断面積を有する、請求項1または2に記載の、接合用の基板を準備する方法。
- 前記誘電体空隙体積の体積は、前記プラグの前記プラグ体積よりも少なくとも10%大きい、先行する請求項のいずれか1項に記載の、接合用の基板を準備する方法。
- 前記接合面に活性化処理を施すステップをさらに含み、任意には、前記接合面は、前記活性化処理の後にOH-イオンを含む溶液に晒される、先行する請求項のいずれか1項に記載の、接合用の基板を準備する方法。
- 前記プラグは貴金属を含む、先行する請求項のいずれか1項に記載の、基板接合用の基板を準備する方法。
- 前記接合可能な誘電体層はケイ素化合物を含み、任意には、前記接合可能な誘電体層は、二酸化ケイ素、窒化ケイ素、酸窒化ケイ素、または炭窒化ケイ素のうち少なくとも1つを含む、先行する請求項のいずれか1項に記載の、基板接合用の基板を準備する方法。
- 前記基板表面上に複数の凹部が形成されており、各凹部の内部にプラグが形成されている、先行する請求項のいずれか1項に記載の、基板接合用の基板を準備する方法。
- 前記基板は、
III族窒化物LEDのアレイ、前記LEDのアレイに電気的に接触するように構成された前記複数のプラグ、または、
CMOS電子デバイスを含み、前記複数のプラグは、前記CMOS電子デバイスに電気的に接触するように構成されている、請求項8に記載の、基板接合用の基板を準備する方法。 - 第1の基板を第2の基板に接合する方法であって、
i)接合用の前記第1の基板を準備するステップを含み、前記準備するステップは、
前記第1の基板の第1の基板表面に第1の凹部を形成するステップと、
前記第1の基板の前記第1の基板表面上に第1の接合可能な誘電体層を形成するステップとを含み、前記第1の接合可能な誘電体層は、前記第1の接合可能な誘電体層のうち前記第1の基板表面とは反対側に第1の接合面を有し、前記第1の凹部および前記第1の接合可能な誘電体層は、第1の誘電体空隙体積を有する第1の誘電体空隙を規定しており、前記準備するステップはさらに、
前記第1の誘電体空隙体積内で前記第1の基板に電気的に接触するように構成された第1のプラグを形成するステップを含み、前記第1のプラグは、前記第1の誘電体空隙体積よりも小さい第1のプラグ体積を有し、前記第1のプラグは、前記第1の誘電体空隙から前記第1の接合面を越えて前記第1の接合面に概ね垂直な方向に延在しており、前記準備するステップはさらに、
対向する平面同士の間で前記第1の基板を圧縮することによって前記第1のプラグをコイニングするステップを含み、前記方法はさらに、
ii)接合用の前記第2の基板を設けるステップを含み、前記第2の基板は、
前記第2の基板の第2の表面上に設けられた第2の接合可能な誘電体層および第2の接触層を含み、前記第2の接触層は、前記第2の接合可能な誘電体層の第2の誘電体表面と同一平面上にあって第2の接合面を形成する第2の接触面を有しており、前記方法はさらに、
iii)前記第1のプラグが前記第2の接触層と位置合わせされるように、前記第1の基板の前記第1の接合面を前記第2の基板の前記第2の接合面の反対側と位置合わせするステップと、
iv)前記第1の基板の前記第1の接合面を前記第2の基板の前記第2の接合面に接触させ、圧縮力下で前記第1のプラグと前記第2の接触層との間に接合部を形成するステップとを含む、方法。 - 前記第1の接合面および/または前記第2の接合面に活性化処理を施し、任意には、前記第1の接合面および/または前記第2の接合面は、前記活性化処理後にOH-イオンを含む溶液に晒される、請求項10に記載の、第1の基板を第2の基板に接合する方法。
- 前記第1の接合面の平面における前記第1のプラグの断面積は前記第2の接触面の表面積よりも小さい、請求項100または11に記載の、第1の基板を第2の基板に接合する方法。
- 接合用の前記第2の基板を設けるステップは、
前記第2の基板の前記第2の基板表面に第2の凹部を形成するステップと、
前記第2の基板の前記第2の基板表面上に前記第2の接合可能な誘電体層を形成するステップとを含み、前記第2の接合可能な誘電体層は、前記第2の接合可能な誘電体層のうち前記第2の基板表面の反対側に前記第2の接合面を有し、前記第2の凹部および前記第2の接合可能な誘電体層は、第2の誘電体空隙体積を有する第2の誘電体空隙を規定しており、前記第2の基板を設けるステップはさらに、
前記第2の誘電体空隙体積内で前記第2の基板に電気的に接触するように構成された第2のプラグを形成するステップを含み、前記第2のプラグは、前記第2の誘電体空隙体積よりも小さい第2のプラグ体積を有し、前記第2のプラグは、前記第2の誘電体空隙から前記第2の接合面を越えて前記第2の接合面に概ね垂直な方向に延在しており、前記第2の基板を設けるステップはさらに、
前記第2のプラグが、前記第2の接合面と同一平面上にある前記第2の接触面を有する前記第2の接触層を形成するように、対向する平面同士の間で前記第2の基板を圧縮することによって、前記第2のプラグをコイニングするステップを含む、請求項10から12のいずれか1項に記載の、第1の基板を第2の基板に接合する方法。 - 前記第1の基板および/または前記第2の基板は、請求項2から9のいずれか1項に記載の方法に従って、基板接合用に準備される、請求項10から13のいずれか1項に記載の、第1の基板を第2の基板に接合する方法。
- 前記第2の接触層は、化学機械研磨プロセスを用いて前記第2の誘電体表面と同一平面にされる、請求項10から12のいずれか1項に記載の、第1の基板を第2の基板に接合する方法。
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