JP2023500629A - FinFET形成のためのキャップ酸化 - Google Patents
FinFET形成のためのキャップ酸化 Download PDFInfo
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- JP2023500629A JP2023500629A JP2022524578A JP2022524578A JP2023500629A JP 2023500629 A JP2023500629 A JP 2023500629A JP 2022524578 A JP2022524578 A JP 2022524578A JP 2022524578 A JP2022524578 A JP 2022524578A JP 2023500629 A JP2023500629 A JP 2023500629A
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- oxide
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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Abstract
Description
[0001] 本出願は、令和1年11月1日に出願された米国特許出願第62/929,332号の優先権の利益を主張し、その内容は、全ての目的のためにその全体が参照により本明細書に組み込まれる。
Claims (15)
- 半導体構造を形成する方法であって、
シリコンゲルマニウムを含む半導体基板の上にシリコン層を形成すること、
前記シリコン層の一部分を前記半導体基板と接触した状態に維持しながら、前記シリコン層の一部分を酸化して犠牲酸化物を形成すること、
前記犠牲酸化物を除去すること、
前記半導体基板と接触する前記シリコン層の前記一部分を酸化して、酸素含有材料を形成すること、及び
前記酸素含有材料の上に重ねて高誘電率誘電材料を形成することを含む、方法。 - 前記除去することは、インシトゥ乾式化学プロセスを含み、第1の処理チャンバ内で実行され、前記方法は更に、前記高誘電率誘電材料を形成する前に、前記半導体基板を前記第1の処理チャンバから第2の処理チャンバに移動させることを含む、請求項1に記載の半導体構造を形成する方法。
- 前記方法は、前記半導体基板を大気に曝露することなしに、1以上の処理チャンバ内で実行される、請求項1に記載の半導体構造を形成する方法。
- 前記シリコン層は、前記シリコンゲルマニウムの上にエピタキシャル形成される、請求項1に記載の半導体構造を形成する方法。
- 前記犠牲酸化物を形成することは、第1の酸化プロセスを含み、前記半導体基板と接触する前記シリコン層の前記一部分を酸化することは、前記第1の酸化プロセスとは異なる第2の酸化プロセスを含む、請求項1に記載の半導体構造を形成する方法。
- 前記半導体基板と接触する前記シリコン層の前記一部分を酸化することは、窒素及び酸素含有前駆体を前記半導体基板に送達することを含み、前記半導体基板と接触する前記シリコン層の前記一部分を酸化することは、約750℃以下の温度で行われる、請求項1に記載の半導体構造を形成する方法。
- 前記高誘電率誘電材料を形成する前に、アンモニア又は酸素含有前駆体を用いて、前記酸素含有材料上に反応性配位子を導入することを更に含む、請求項1に記載の半導体構造を形成する方法。
- 前記高誘電率誘電材料が、ハフニウム、ジルコニウム、シリコン、ランタン、アルミニウム、チタン、及びストロンチウムからなる群から選択される少なくとも1つの元素を含む、請求項1に記載の半導体構造を形成する方法。
- 半導体構造を形成する方法であって、
半導体処理チャンバ内に収容された基板の表面から酸化物を除去することであって、前記基板はシリコンゲルマニウムフィンを含む、酸化物を除去すること、
前記基板の前記表面の上にシリコン層を形成すること、
前記シリコン層の一部分を前記基板と接触した状態に維持しながら、前記シリコン層の一部分を酸化して犠牲酸化物を形成すること、
前記犠牲酸化物を除去すること、
亜酸化窒素を前記基板に送達して、酸素含有材料を形成すること、
前記基板を窒素含有前駆体と接触させることによって、前記酸素含有材料を前処理すること、及び
前処理された前記酸素含有材料の上に重ねて高誘電率誘電材料を形成することを含む、方法。 - 前記除去することは、インシトゥ乾式化学プロセスを含み、第1の処理チャンバ内で実行され、前記方法は更に、前記高誘電率誘電材料を形成する前に、前記基板を前記第1の処理チャンバから第2の処理チャンバに移動させることを含む、請求項9に記載の半導体構造を形成する方法。
- 前記犠牲酸化物を形成することは、亜酸化窒素を前記基板に送達して酸素含有材料を形成することを含み、亜酸化窒素を前記基板に送達して酸素含有材料を形成することは、約750℃以下の温度で行われる、請求項9に記載の半導体構造を形成する方法。
- 前記犠牲酸化物を形成することは、酸素含有前駆体及び水素含有前駆体を前記基板に送達して酸素含有材料を形成することを含む、請求項9に記載の半導体構造を形成する方法。
- 前記酸素含有材料を前処理することにより、前記酸素含有材料上に反応性配位子を形成する、請求項9に記載の半導体構造を形成する方法。
- 前記高誘電率誘電材料を後処理することを更に含む、請求項9に記載の半導体構造を形成する方法。
- 半導体構造を形成する方法であって、
半導体処理チャンバ内に収容された基板の表面から自然酸化物を除去することであって、前記基板はシリコンゲルマニウムを含む、自然酸化物を除去すること、
前記基板の前記表面の上にシリコン層を形成すること、
前記シリコン層の一部分を前記基板と接触した状態に維持しながら、前記シリコン層の一部分を酸化して犠牲酸化物を形成すること、
前記犠牲酸化物の除去すること、
前記基板と接触する前記シリコン層の前記一部分を酸化して、酸素含有材料を形成すること、及び
前記酸素含有材料の上に重ねて高誘電率誘電材料を形成することを含む、方法。
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