JP2023098661A - 半導体構造及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 238000002955 isolation Methods 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000000926 separation method Methods 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- Computer Hardware Design (AREA)
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Abstract
Description
Claims (20)
- 半導体構造であって、半導体構造は、
第1のデバイス領域、及び該第1のデバイス領域に近接する第2のデバイス領域を含む基板と、
前記第1のデバイス領域と前記第2のデバイス領域との間の前記基板内のトレンチ分離構造と、を含み、
前記トレンチ分離構造は、前記第1のデバイス領域内の第1の底面と、前記第2のデバイス領域内の第2の底面とを含み、前記第1の底面は、前記第2の底面と同一平面上にある、
半導体構造。 - 前記トレンチ分離構造は、前記第1のデバイス領域内の第1の上面と、前記第2のデバイス領域内の第2の上面とを含み、前記第1の上面は、前記第2の上面と同一平面上にある、請求項1に記載の半導体構造。
- 前記第1のデバイス領域は中電圧デバイス領域であり、前記第2のデバイス領域は低電圧デバイス領域である、請求項1に記載の半導体構造。
- 前記第1のデバイス領域内の前記基板の上面が、前記第2のデバイス領域内の前記基板の上面よりも低い、請求項1に記載の半導体構造。
- 前記第1のデバイス領域内の前記基板の前記上面上の第1のゲート酸化物層と、
前記第2のデバイス領域内の前記基板の前記上面上の第2のゲート酸化物層と、をさらに含み、
前記第1のゲート酸化物層は前記第2のゲート酸化物層より厚い、請求項4に記載の半導体構造。 - 前記第1のデバイス領域内の前記第1のゲート酸化物層上に配置される第1のゲートと、
前記第2のデバイス領域内の前記第2のゲート酸化物層上に配置される第2のゲートと、をさらに含む、請求項5に記載の半導体構造。 - 前記第1のゲート及び前記第2のゲートは金属ゲートである、請求項6に記載の半導体構造。
- 半導体構造の製造方法であって、当該製造方法は、
第1のデバイス領域、及び該第1のデバイス領域に近接する第2のデバイス領域を含む基板を提供するステップと、
前記第1のデバイス領域と前記第2のデバイス領域との間の前記基板内にトレンチ分離構造を形成するステップと、
前記第1のデバイス領域、前記第2のデバイス領域、及び前記トレンチ分離構造を覆うように、前記基板上にマスク層をコンフォーマルに(conformally)堆積するステップと、
前記マスク層上に第1のレジストパターンを形成するステップであって、該第1のレジストパターンは、前記トレンチ分離構造及び前記第2のデバイス領域を覆う、ステップと、
前記第1のレジストパターンによって覆われていない前記マスク層及びパッド酸化物層を前記第1のデバイス領域から除去して、それにより前記第1のデバイス領域の前記基板の上面を露出させるステップと、
前記第1のレジストパターンを除去するステップと、
前記第1のデバイス領域内の前記基板の前記上面を酸化して、犠牲酸化物層を形成するステップと、
前記犠牲酸化物層を除去して、前記第1のデバイス領域内の前記基板の前記上面を露出させるステップと、
前記マスク層を除去して、前記トレンチ分離構造の上面を露出させるステップと、を含む、
製造方法。 - 前記マスク層は窒化ケイ素層である、請求項8に記載の製造方法。
- 前記マスク層は約200~220オングストロームの厚さを有する、請求項8に記載の製造方法。
- 前記パッド酸化物層は約100~110オングストロームの厚さを有する、請求項8に記載の製造方法。
- 前記マスク層を除去した後に、前記第1のデバイス領域内の前記基板の前記上面に第1のゲート酸化物層を成長させるステップをさらに含む、請求項8に記載の製造方法。
- 前記第1のゲート酸化物層は、約200~220オングストロームの厚さを有する、請求項12に記載の製造方法。
- 前記犠牲酸化物層を形成することによって消費される、前記第1のデバイス領域における前記基板の上面の消費される厚さが、約190~210オングストロームである、請求項8に記載の製造方法。
- 前記基板上に第2のレジストパターンを形成するステップであって、該第2のレジストパターンは、前記第1のデバイス領域内の前記第1のゲート酸化物層を覆うが、前記トレンチ分離構造及び前記第2のデバイス領域は覆わない、ステップと、
前記トレンチ分離構造及び前記第2のデバイス領域をエッチングして、それにより前記第2のデバイス領域の前記基板の上面を露出させるステップと、
前記第2のレジストパターンを除去するステップと、を含む、請求項12に記載の製造方法。 - 前記第2のデバイス領域内の前記基板の前記上面に第2のゲート酸化物層を成長させるステップをさらに含む、請求項15に記載の製造方法。
- 前記トレンチ分離構造は、前記第1のデバイス領域内の第1の上面と、前記第2のデバイス領域内の第2の上面とを含み、前記第1の上面は、前記第2の上面と同一平面上にある、請求項15に記載の製造方法。
- 前記第1のデバイス領域内の前記基板の前記上面は、前記第2のデバイス領域内の前記基板の上面よりも低い、請求項15に記載の製造方法。
- 前記トレンチ分離構造は、前記第1のデバイス領域内の第1の底面と、前記第2のデバイス領域内の第2の底面とを含み、前記第1の底面は、前記第2の底面と同一平面上にある、請求項8に記載の製造方法。
- 前記第1のデバイス領域は中電圧デバイス領域であり、前記第2のデバイス領域は低電圧デバイス領域である、請求項8に記載の製造方法。
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CN202111623111.4A CN116364718A (zh) | 2021-12-28 | 2021-12-28 | 半导体结构及其制造方法 |
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- 2021-12-28 CN CN202111623111.4A patent/CN116364718A/zh active Pending
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