JP2022540627A - 電荷トラッピング層を備えた支持体上に転送された薄層を含む構造物の製造方法 - Google Patents
電荷トラッピング層を備えた支持体上に転送された薄層を含む構造物の製造方法 Download PDFInfo
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- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 85
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- 229940110728 nitrogen / oxygen Drugs 0.000 claims description 12
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- WSMQKESQZFQMFW-UHFFFAOYSA-N 5-methyl-pyrazole-3-carboxylic acid Chemical compound CC1=CC(C(O)=O)=NN1 WSMQKESQZFQMFW-UHFFFAOYSA-N 0.000 claims description 6
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H03H9/02559—Characteristics of substrate, e.g. cutting angles of lithium niobate or lithium-tantalate substrates
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Abstract
Description
-ベース基板上に形成されたトラッピング層を含む支持体を調整し、トラッピング層は1018at/cm3未満の水素濃度を有する、
-水素濃度が1020at/cm3未満の誘電体層、またはトラッピング層への水素の拡散を防止するバリア、または水素拡散係数の低い誘電体層を使用して、支持体をドナー基板に接合する、
-ドナー基板の一部を除去して薄層を形成する。
-製造方法は、構造物(1)を最高温度1000℃未満の温度にさらす。
・トラッピング層は、600℃と950℃との間の堆積温度で堆積され、支持体を調整するステップは、水素が欠乏した雰囲気及び堆積温度と1000℃との間の温度でトラッピング層をアニーリングする第1のステージを含む、
-ベース基板、
-ベース基板上に配置され、水素濃度が1018atm/cm3未満のトラッピング層、
-トラッピング層上に配置された誘電体層、水素濃度が1020atm/cm3未満またはトラッピング層への水素の拡散を防止するバリアを備えているか、水素拡散率が低い誘電体層、
-誘電体層に配置された薄層。
-少なくとも1020at/cm3の水素濃度を含み、この層と接触して配置された誘電体層、
-1018at/cm3以下の水素濃度を含み、1μmの多結晶シリコンのトラッピング層、
500℃で1時間の熱処理を行い、熱処理終了時においてトラッピング層で1018at/cm3未満の水素濃度の測定に導く。
-ベース基板6、
-ベース基板6上に配置され、水素濃度が1018atm/cm3未満のトラッピング層3、
-トラッピング層3上に配置され、有利にはこの層と接触している誘電体層4。誘電体層4は、水素濃度が1020at/cm3未満であるか、またはトラッピング層3への水素の拡散を防止するバリアを含むか、または任意の水素濃度を有するが、水素拡散係数は非常に低い。
-薄層5は、誘電体層4上に配置され、好ましくはこの層と接触している。この薄層5は、シリコンのような半導体材料、強誘電体材料等の絶縁体、または統合された半導体部品を含む層から構成されることができる。
Claims (21)
- 電荷トラッピング層(3)を備えた支持体(2)上に転写された薄層(5)を含む構造(1)を製造するための方法であって、
ベース基板(6)上に形成されたトラッピング層(3)を含む支持体(2)を調整するステップであって、前記トラッピング層(3)の水素濃度が1018at/cm3未満であるステップと、
前記支持体(2)を、水素濃度が1020at/cm3未満であるか、前記トラッピング層(3)への水素の拡散を防止するバリアを含むか、または低い水素拡散率を有する誘電体層(4)によって、ドナー基板に接合するステップと、
前記ドナー基板の一部を除去して薄層(5)を形成するステップと、を含み、
構造(1)を最高温度1000℃未満の温度にさらす製造方法。 - 前記トラッピング層(3)は、600℃と950℃との間で堆積され、支持体(2)を調整するステップは、水素が欠乏した雰囲気中、堆積温度と1000℃との間で前記トラッピング層(3)をアニールする第1の段階を含む、請求項1に記載の製造方法。
- 前記トラッピング層の堆積は、LPCVD法で実施する、請求項2に記載の製造方法。
- 前記トラッピング層(3)は、950℃と1100℃との間の温度で堆積することによって形成される、請求項1に記載の製造方法。
- 前記トラッピング層(3)の堆積は、エピタキシーフレーム内で実施される、請求項4に記載の製造方法。
- 前記誘電体層(4)は、1020at/cm3を超える水素濃度を有する材料を堆積させ、続いて、水素が欠乏した雰囲気中での第2のアニール段階を適用することによって生成される、請求項1から5のいずれか一項に記載の製造方法。
- 前記第2のアニーリング段階は、中性雰囲気中で少なくとも1時間、800℃と900℃との間である、請求項6に記載の製造方法。
- 前記誘電体層(4)は、前記第1のアニールの適用前に、1020at/cm3を超える水素濃度を有する材料を前記トラッピング層(3)上に堆積させることによって製造される、請求項2または3に記載の製造方法。
- 前記誘電体層(4)は、800℃と1000℃との間の温度でのトラッピング層(3)の熱酸化によって生成される、請求項1から5のいずれか一項に記載の製造方法。
- 前記誘電体層(4)が前記バリアを含み、前記バリアが前記トラッピング層(3)と直接接触する、請求項1から5のいずれか一項に記載の製造方法。
- 前記バリアは、SiNまたはAlNの層で構成される、請求項10に記載の製造方法。
- 低水素拡散率を有する前記誘電体層(4)は、0.01または0.05以上の窒素/酸素比の窒素を有する酸化物を含む、請求項1から5のいずれか一項に記載の製造方法。
- 低窒素拡散率を有する前記誘電体層(4)は、0.01と0.25との間、または0.05と0.1との間の窒素/酸素比の窒素を有するシリコン酸化物を含む、請求項1から5のいずれか一項に記載の製造方法。
- 前記接合するステップの以前に、前記ドナー基板内に脆化面を形成するステップを含み、前記除去するステップが、前記ドナー基板を前記脆化面において破砕することによって実施される、請求項1から13のいずれか一項に記載の製造方法。
- 前記薄層(5)は、圧電性及び/または強誘電性材料で構成される、請求項14に記載の製造方法。
- 前記薄層(5)は、タンタル酸リチウムまたはニオブ酸リチウムでできている、請求項15に記載の製造方法。
- 高温、例えば600℃または1000℃を超える温度にさらすことができない構造(1)であって、
ベース基板(6)、
前記ベース基板(6)上に配置され、水素濃度が1018at/cm3未満のトラッピング層(3)と、
前記トラッピング層(3)上に配置された誘電体層(4)であって、水素濃度が1020at/cm3未満であるか、またはトラッピング層への水素の拡散を防止するバリアを含むか、または低い水素拡散率を有する前記誘電体層(4)と、
前記誘電体層(4)上に配置された薄層(5)と、
を含む、構造(1)。 - 前記薄層(5)は、永久分極を有する強誘電体材料で構成され、キュリー温度が600℃と1000℃との間である、請求項17に記載の構造(1)。
- 前記誘電体層(4)は、前記トラッピング層(3)及び前記薄層(5)と接触する、請求項17または18に記載の構造(1)。
- 前記誘電体層(4)は、低い水素拡散率を有し、窒素/酸素比が0.01以上または0.05以上の窒素を有する酸化物を含む、請求項17から19のいずれか一項に記載の構造(1)。
- 前記誘電体層(4)は、低い水素拡散率を有し、窒素/酸素比が0.01と0.25との間、または0.05と0.1との間の窒素を有するシリコン酸化物を含む、請求項17から19のいずれか一項に記載の構造(1)。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1907859 | 2019-07-12 | ||
FR1907859A FR3098642B1 (fr) | 2019-07-12 | 2019-07-12 | procédé de fabrication d'une structure comprenant une couche mince reportée sur un support muni d’une couche de piégeage de charges |
PCT/EP2020/058462 WO2021008742A1 (fr) | 2019-07-12 | 2020-03-26 | Procede de fabrication d'une structure comprenant une couche mince reportee sur un support muni d'une couche de piegeage de charges |
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JP2022540627A true JP2022540627A (ja) | 2022-09-16 |
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JP2022501248A Pending JP2022540627A (ja) | 2019-07-12 | 2020-03-26 | 電荷トラッピング層を備えた支持体上に転送された薄層を含む構造物の製造方法 |
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US (1) | US20220247374A1 (ja) |
EP (2) | EP4060715A1 (ja) |
JP (1) | JP2022540627A (ja) |
KR (1) | KR20220032100A (ja) |
CN (1) | CN114127893A (ja) |
FI (1) | FI3997728T3 (ja) |
FR (1) | FR3098642B1 (ja) |
TW (1) | TWI830891B (ja) |
WO (1) | WO2021008742A1 (ja) |
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FR3137493A1 (fr) | 2022-06-29 | 2024-01-05 | Soitec | Procede de fabrication d’une structure comportant une couche barriere a la diffusion d’especes atomiques |
FR3137490A1 (fr) | 2022-07-04 | 2024-01-05 | Soitec | Procede de fabrication d’une structure comportant une couche barriere a la diffusion d’especes atomiques |
FR3141590A1 (fr) * | 2022-10-26 | 2024-05-03 | Soitec | Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI) |
FR3141591A1 (fr) * | 2022-10-26 | 2024-05-03 | Soitec | Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI) |
FR3141592A1 (fr) * | 2022-10-26 | 2024-05-03 | Soitec | Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI) |
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EP1087041B1 (en) | 1999-03-16 | 2009-01-07 | Shin-Etsu Handotai Co., Ltd | Production method for silicon wafer and silicon wafer |
FR2838865B1 (fr) | 2002-04-23 | 2005-10-14 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee |
FR2860341B1 (fr) | 2003-09-26 | 2005-12-30 | Soitec Silicon On Insulator | Procede de fabrication de structure multicouche a pertes diminuees |
FR2933233B1 (fr) | 2008-06-30 | 2010-11-26 | Soitec Silicon On Insulator | Substrat de haute resistivite bon marche et procede de fabrication associe |
FR2953640B1 (fr) | 2009-12-04 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante |
FR2985812B1 (fr) | 2012-01-16 | 2014-02-07 | Soitec Silicon On Insulator | Procede et dispositif de test de substrats semi-conducteurs pour applications radiofrequences |
US9768056B2 (en) | 2013-10-31 | 2017-09-19 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition |
US9899499B2 (en) * | 2014-09-04 | 2018-02-20 | Sunedison Semiconductor Limited (Uen201334164H) | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss |
WO2016081367A1 (en) * | 2014-11-18 | 2016-05-26 | Sunedison Semiconductor Limited | HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION |
FR3029682B1 (fr) * | 2014-12-04 | 2017-12-29 | Soitec Silicon On Insulator | Substrat semi-conducteur haute resistivite et son procede de fabrication |
CN107533953B (zh) * | 2015-03-03 | 2021-05-11 | 环球晶圆股份有限公司 | 具有可控膜应力的在硅衬底上沉积电荷捕获多晶硅膜的方法 |
US10468294B2 (en) * | 2016-02-19 | 2019-11-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface |
FR3053532B1 (fr) * | 2016-06-30 | 2018-11-16 | Soitec | Structure hybride pour dispositif a ondes acoustiques de surface |
WO2018106535A1 (en) * | 2016-12-05 | 2018-06-14 | Sunedison Semiconductor Limited | High resistivity silicon-on-insulator structure and method of manufacture thereof |
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2019
- 2019-07-12 FR FR1907859A patent/FR3098642B1/fr active Active
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2020
- 2020-03-26 CN CN202080049468.3A patent/CN114127893A/zh active Pending
- 2020-03-26 EP EP22172838.9A patent/EP4060715A1/fr active Pending
- 2020-03-26 US US17/597,581 patent/US20220247374A1/en active Pending
- 2020-03-26 WO PCT/EP2020/058462 patent/WO2021008742A1/fr unknown
- 2020-03-26 KR KR1020227004773A patent/KR20220032100A/ko not_active Application Discontinuation
- 2020-03-26 EP EP20712993.3A patent/EP3997728B1/fr active Active
- 2020-03-26 TW TW109110269A patent/TWI830891B/zh active
- 2020-03-26 FI FIEP20712993.3T patent/FI3997728T3/fi active
- 2020-03-26 JP JP2022501248A patent/JP2022540627A/ja active Pending
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CN114127893A (zh) | 2022-03-01 |
WO2021008742A1 (fr) | 2021-01-21 |
EP3997728B1 (fr) | 2023-02-22 |
FR3098642B1 (fr) | 2021-06-11 |
EP4060715A1 (fr) | 2022-09-21 |
TWI830891B (zh) | 2024-02-01 |
EP3997728A1 (fr) | 2022-05-18 |
KR20220032100A (ko) | 2022-03-15 |
TW202117801A (zh) | 2021-05-01 |
US20220247374A1 (en) | 2022-08-04 |
FR3098642A1 (fr) | 2021-01-15 |
FI3997728T3 (fi) | 2023-04-27 |
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