JP2022537125A5 - - Google Patents

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Publication number
JP2022537125A5
JP2022537125A5 JP2021572848A JP2021572848A JP2022537125A5 JP 2022537125 A5 JP2022537125 A5 JP 2022537125A5 JP 2021572848 A JP2021572848 A JP 2021572848A JP 2021572848 A JP2021572848 A JP 2021572848A JP 2022537125 A5 JP2022537125 A5 JP 2022537125A5
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JP
Japan
Prior art keywords
substrate
hard mask
filler material
forming
self
Prior art date
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Granted
Application number
JP2021572848A
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English (en)
Japanese (ja)
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JP7492307B2 (ja
JP2022537125A (ja
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Priority claimed from PCT/US2020/036778 external-priority patent/WO2020251927A1/en
Publication of JP2022537125A publication Critical patent/JP2022537125A/ja
Publication of JP2022537125A5 publication Critical patent/JP2022537125A5/ja
Application granted granted Critical
Publication of JP7492307B2 publication Critical patent/JP7492307B2/ja
Active legal-status Critical Current
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JP2021572848A 2019-06-12 2020-06-09 半導体デバイスの平坦化 Active JP7492307B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201962860359P 2019-06-12 2019-06-12
US62/860,359 2019-06-12
PCT/US2020/036778 WO2020251927A1 (en) 2019-06-12 2020-06-09 Planarization of semiconductor devices

Publications (3)

Publication Number Publication Date
JP2022537125A JP2022537125A (ja) 2022-08-24
JP2022537125A5 true JP2022537125A5 (https=) 2023-04-07
JP7492307B2 JP7492307B2 (ja) 2024-05-29

Family

ID=73744894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021572848A Active JP7492307B2 (ja) 2019-06-12 2020-06-09 半導体デバイスの平坦化

Country Status (6)

Country Link
US (1) US11456185B2 (https=)
JP (1) JP7492307B2 (https=)
KR (1) KR102819046B1 (https=)
CN (1) CN114127895B (https=)
TW (1) TWI845699B (https=)
WO (1) WO2020251927A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114609868A (zh) * 2022-05-12 2022-06-10 合肥晶合集成电路股份有限公司 一种光阻缺陷的验证方法
CN114815493A (zh) * 2022-05-27 2022-07-29 上海传芯半导体有限公司 Euv光掩模基版、euv光掩模版及其制造方法、衬底回收方法

Family Cites Families (28)

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US5851899A (en) * 1996-08-08 1998-12-22 Siemens Aktiengesellschaft Gapfill and planarization process for shallow trench isolation
US8629019B2 (en) * 2002-09-24 2014-01-14 Vishay-Siliconix Method of forming self aligned contacts for a power MOSFET
US6939796B2 (en) * 2003-03-14 2005-09-06 Lam Research Corporation System, method and apparatus for improved global dual-damascene planarization
US20040183220A1 (en) * 2003-03-18 2004-09-23 Avinash Dalmia Ultra thin layer coating using self-assembled molecules as a separating layer for diffraction grating application
US7985677B2 (en) * 2004-11-30 2011-07-26 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
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KR100816749B1 (ko) * 2006-07-12 2008-03-27 삼성전자주식회사 소자분리막, 상기 소자분리막을 구비하는 비휘발성 메모리소자, 그리고 상기 소자분리막 및 비휘발성 메모리 소자형성 방법들
US9761262B2 (en) * 2008-07-02 2017-09-12 Seagate Technology Llc Planarization methodology for topographically challenged media surface
KR101053647B1 (ko) * 2009-12-29 2011-08-02 주식회사 하이닉스반도체 반도체 장치 제조 방법
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