TWI845699B - 半導體裝置的平坦化 - Google Patents

半導體裝置的平坦化 Download PDF

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Publication number
TWI845699B
TWI845699B TW109119139A TW109119139A TWI845699B TW I845699 B TWI845699 B TW I845699B TW 109119139 A TW109119139 A TW 109119139A TW 109119139 A TW109119139 A TW 109119139A TW I845699 B TWI845699 B TW I845699B
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TW
Taiwan
Prior art keywords
substrate
hard mask
depositing
spin
surface treatment
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TW109119139A
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English (en)
Chinese (zh)
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TW202113977A (zh
Inventor
萊恩 伯恩斯
馬克 桑末薇拉
科里 萊姆利
Original Assignee
日商東京威力科創股份有限公司
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Publication of TW202113977A publication Critical patent/TW202113977A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/04—Planarisation of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

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  • Formation Of Insulating Films (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
TW109119139A 2019-06-12 2020-06-08 半導體裝置的平坦化 TWI845699B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201962860359P 2019-06-12 2019-06-12
US62/860,359 2019-06-12

Publications (2)

Publication Number Publication Date
TW202113977A TW202113977A (zh) 2021-04-01
TWI845699B true TWI845699B (zh) 2024-06-21

Family

ID=73744894

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109119139A TWI845699B (zh) 2019-06-12 2020-06-08 半導體裝置的平坦化

Country Status (6)

Country Link
US (1) US11456185B2 (https=)
JP (1) JP7492307B2 (https=)
KR (1) KR102819046B1 (https=)
CN (1) CN114127895B (https=)
TW (1) TWI845699B (https=)
WO (1) WO2020251927A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114609868A (zh) * 2022-05-12 2022-06-10 合肥晶合集成电路股份有限公司 一种光阻缺陷的验证方法
CN114815493A (zh) * 2022-05-27 2022-07-29 上海传芯半导体有限公司 Euv光掩模基版、euv光掩模版及其制造方法、衬底回收方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040183220A1 (en) * 2003-03-18 2004-09-23 Avinash Dalmia Ultra thin layer coating using self-assembled molecules as a separating layer for diffraction grating application
US20060115983A1 (en) * 2004-11-30 2006-06-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
WO2018182637A1 (en) * 2017-03-30 2018-10-04 Intel Corporation Bottom-up fill using blocking layers and adhesion promoters

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4576834A (en) * 1985-05-20 1986-03-18 Ncr Corporation Method for forming trench isolation structures
EP0597603A3 (en) * 1992-11-13 1998-03-11 Digital Equipment Corporation Trench isolation planarization using a hard mask
US5851899A (en) * 1996-08-08 1998-12-22 Siemens Aktiengesellschaft Gapfill and planarization process for shallow trench isolation
US8629019B2 (en) * 2002-09-24 2014-01-14 Vishay-Siliconix Method of forming self aligned contacts for a power MOSFET
US6939796B2 (en) * 2003-03-14 2005-09-06 Lam Research Corporation System, method and apparatus for improved global dual-damascene planarization
JP4845491B2 (ja) * 2004-11-30 2011-12-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
KR100816749B1 (ko) * 2006-07-12 2008-03-27 삼성전자주식회사 소자분리막, 상기 소자분리막을 구비하는 비휘발성 메모리소자, 그리고 상기 소자분리막 및 비휘발성 메모리 소자형성 방법들
US9761262B2 (en) * 2008-07-02 2017-09-12 Seagate Technology Llc Planarization methodology for topographically challenged media surface
KR101053647B1 (ko) * 2009-12-29 2011-08-02 주식회사 하이닉스반도체 반도체 장치 제조 방법
US8415252B2 (en) * 2010-01-07 2013-04-09 International Business Machines Corporation Selective copper encapsulation layer deposition
US8466034B2 (en) * 2010-03-29 2013-06-18 GlobalFoundries, Inc. Method of manufacturing a finned semiconductor device structure
CN102237297A (zh) * 2010-04-29 2011-11-09 武汉新芯集成电路制造有限公司 金属互连结构的制作方法及平坦化工艺
US8513129B2 (en) * 2010-05-28 2013-08-20 Applied Materials, Inc. Planarizing etch hardmask to increase pattern density and aspect ratio
CN102479701B (zh) * 2010-11-30 2015-06-24 中国科学院微电子研究所 化学机械平坦化方法和后金属栅的制作方法
US8476168B2 (en) * 2011-01-26 2013-07-02 International Business Machines Corporation Non-conformal hardmask deposition for through silicon etch
WO2012118847A2 (en) * 2011-02-28 2012-09-07 Inpria Corportion Solution processible hardmarks for high resolusion lithography
US8703004B2 (en) * 2011-11-14 2014-04-22 Kabushiki Kaisha Toshiba Method for chemical planarization and chemical planarization apparatus
US9349604B2 (en) * 2013-10-20 2016-05-24 Tokyo Electron Limited Use of topography to direct assembly of block copolymers in grapho-epitaxial applications
US9236446B2 (en) * 2014-03-13 2016-01-12 Taiwan Semiconductor Manufacturing Co., Ltd. Barc-assisted process for planar recessing or removing of variable-height layers
US10338466B2 (en) * 2015-04-13 2019-07-02 Tokyo Electron Limited System and method for planarizing a substrate
US9570302B1 (en) * 2016-02-10 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method of patterning a material layer
US9991133B2 (en) * 2016-08-11 2018-06-05 Tokyo Electron Limited Method for etch-based planarization of a substrate
US10290804B2 (en) * 2017-01-23 2019-05-14 Sandisk Technologies Llc Nanoparticle-based resistive memory device and methods for manufacturing the same
US10998221B2 (en) * 2017-07-14 2021-05-04 Micron Technology, Inc. Semiconductor constructions having fluorocarbon material
US10586734B2 (en) * 2017-11-20 2020-03-10 Tokyo Electron Limited Method of selective film deposition for forming fully self-aligned vias

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040183220A1 (en) * 2003-03-18 2004-09-23 Avinash Dalmia Ultra thin layer coating using self-assembled molecules as a separating layer for diffraction grating application
US20060115983A1 (en) * 2004-11-30 2006-06-01 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
WO2018182637A1 (en) * 2017-03-30 2018-10-04 Intel Corporation Bottom-up fill using blocking layers and adhesion promoters

Also Published As

Publication number Publication date
KR102819046B1 (ko) 2025-06-10
JP7492307B2 (ja) 2024-05-29
US20200395224A1 (en) 2020-12-17
TW202113977A (zh) 2021-04-01
CN114127895A (zh) 2022-03-01
WO2020251927A1 (en) 2020-12-17
JP2022537125A (ja) 2022-08-24
US11456185B2 (en) 2022-09-27
KR20220020834A (ko) 2022-02-21
CN114127895B (zh) 2026-02-06

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