WO2018182637A1

WO2018182637A1 - Bottom-up fill using blocking layers and adhesion promoters

Info

Publication number: WO2018182637A1
Application number: PCT/US2017/025127
Authority: WO
Inventors: Rami HOURANI; Scott B. Clendenning; Grant M. Kloster; Aranzazu MAESTRE CARO; Florian Gstrein; Akm Shaestagir CHOWDHURY; Tayseer MAHDI
Original assignee: Intel Corporation
Priority date: 2017-03-30
Filing date: 2017-03-30
Publication date: 2018-10-04

Abstract

A device including a substrate formed of a material. The device includes a plurality of recessed features in a surface of the substrate, wherein the plurality of recessed features have an aspect ratio between 3:1-10:1, inclusive. The device includes a fill in the plurality of recessed features, wherein the fill is a second material that is different than the material of the substrate and wherein the fill covers sidewalls and bottom surfaces of the plurality of recessed features.

Description

BOTTOM-UP FILL USING BLOCKING LAYERS AND ADHESION PROMOTERS

Background

[0001] Integrated circuits (IC) use trench isolation to prevent electric current leakage between adjacent semiconductor device components. The trenches are filled with a conductive or dielectric material to prevent electromigration.

Brief Description of the Drawings

[0002] The present disclosure described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, features illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some features may be exaggerated relative to other features for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements.

[0003] Figure 1 illustrates a process of providing a substrate with recessed features, according to implementations .

[0004] Figure 2 illustrates a process of depositing a blocking layer on the substrate, according to implementations .

[0005] Figure 3 illustrates a process of depositing a fill in the recessed features of a substrate, according to implementations.

[0006] Figure 4 shows a process of providing a substrate with recessed features, according to implementations .

[0007] Figure 5 illustrates a process of depositing a blocking layer on the substrate, according to implementations .

[0008] Figure 6 illustrates a process of depositing a fill in the recessed features of a substrate, according to implementations.

[0009] Figure 7 illustrates a process of providing a substrate with recessed features, according to implementations .

[0010] Figure 8 illustrates a process of depositing a blocking layer on the substrate, according to implementations .

[0011] Figure 9 shows a process of depositing an adhesion promoter on the bottom portions of the recessed features of the substrate, according to implementations.

[0012] Figure 10 shows a process of depositing a fill in the bottom portions of the recessed features of the substrate, according to implementations. [0013] Figure 11 illustrates a process of removing the blocking layer from the substrate and recessed features and depositing an adhesion promoter, according to implementations.

[0014] Figure 12 illustrates a process of depositing a fill in the recessed features of a substrate, according to implementations.

[0015] Figure 13 illustrates a cross sectional view of a recessed feature of the substrate, according to implementations.

[0016] Figure 14 is a flow diagram of a fabrication process for the filling of recessed features in a substrate, according to implementations.

[0017] Figure 15 is a flow diagram of a fabrication process for the filling of recessed features in a substrate, according to implementations.

[0018] Figure 16 is a computing device built in accordance with implementations of the present disclosure.

Detailed Description

[0019] In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations .

[0020] The feature size of integrated circuits (IC) has continued to shrink as performance and cost demands have pushed designers to design integrated circuits with an increasing number of devices per unit area. Semiconductor manufacturing processes are continually developed and employed to enable the manufacture of smaller and smaller features on a substrate of an IC. A feature may be an element or physical structure of an integrated circuit, such as a trench or gap (also referred to as "recessed feature" hereafter) on the surface of the substrate. The recessed features may be filled with a conductive or dielectric material (also referred to as "fill" hereafter) to prevent electromigration. An adhesion promotion layer (also referred to as "adhesion promoter" hereafter) may be applied to surfaces of the recessed features to promote conformal coverage of the surfaces of the recessed features by the fill. As the width of the trenches or gaps decreases, the depth of the trenches or gaps remains relatively the same. This results in trenches or gaps having increasing ratios of depth to width (also referred to as "aspect ratio" hereafter).

[0021] As the aspect ratio of recessed features increase, techniques of filling the recessed features and annealing/reflowing the fill or electrodeposition of the fill may be ineffective.

Additionally, as critical dimensions of IC's continue to decrease, the use of traditional adhesion promotion layers become less effective as the adhesion promotion layers are too thick to occupy a significant percentage of the recessed feature to be filled. As the aspect ratio increases, it becomes increasingly difficult to ensure the fill in the bottom portion of the recessed feature is free of voids or gaps. If the fill contains any voids or gaps, there may be electromigration or arcing, degrading the performance of the IC or the IC may fail.

[0022] The present disclosure addresses the above-mentioned and other deficiencies by depositing a blocking layer on an upper portion of the sidewalls of the recessed features and the surface of the substrate. The blocking layer may render the upper portion of the sidewalls and the surface of the substrate hydrophobic. The blocking layer may prevent the deposition of a fill on the hydrophobic surface and sidewalls, which may repel the fill causing it to deposit in the bottom portion of the recessed features. Repelling the fill to the bottom portion of the recessed features allows for the filling of recessed features having high aspect ratios without voids or gaps in the fill. In some implementations, an adhesion promoter may be deposited in the recessed features prior to depositing the fill, where the adhesion promoter is also repelled into the bottom portion of the recessed features by the hydrophobic surface and sidewalls.

[0023] It may be noted that for purposes of illustration, rather than limitation, that aspects of the present disclosure describe processes and features of filling a substrate having recessed features. It may be noted that aspects of the present disclosure may be applied to features, components, layers, etc. of an IC other than a substrate.

[0024] In one implementation, a device includes a substrate including a material, multiple recessed features in a surface of the substrate and a fill in the multiple recessed features. The multiple recessed features have an aspect ratio between 3: 1-10: 1, inclusive. The fill in the multiple recessed features includes a second material that is different than the material of the substrate and covers sidewalls and bottom surfaces of the multiple recessed features.

[0025] In another implementation, the surface of the substrate and a top portion of the sidewalls of the multiple recessed features near the surface of the substrate have 0.1-10% fluorine, inclusive. In implementations, the fill is a conductive material. In other implementations, the fill is a dielectric material. [0026] In implementations, a top portion of the sidewalls of the multiple recessed features near the surface of the substrate has a width that is greater than a bottom portion of the sidewalls near the bottom surfaces of the multiple recessed features. In one implementation, the top portion of the sidewalls of the multiple recessed features have a surface roughness of 0.5-5 nanometers, inclusive. In another implementation, a bottom portion of the sidewalls near the bottom surfaces of the multiple recessed features and the bottom surfaces of the multiple recessed features include an adhesion promoter.

[0027] In implementations, a device includes a substrate including a first material, multiple recessed features in a surface of the substrate and a fill in the multiple recessed features. The multiple recessed features include bottom surfaces including a second material that is different than the first material. The fill in the multiple recessed features includes a third material that is different than the first material and the second material and covers the sidewalls and the bottom surfaces of the multiple recessed features.

[0028] In one implementation, the surface of the substrate and a top portion of the sidewalls of the multiple recessed features near the surface of the substrate include self-assembled

monolayers. In another implementation, the surface of the substrate and a top portion of the sidewalls of the plurality of recessed features near the surface of the substrate include 0.1-10% fluorine, inclusive. In a further implementation, the percentage of fluorine is greatest on the surface of the substrate and decreases from a top of the top portion of the sidewalls of the multiple recessed features to a bottom of the top portion of the sidewalls of the multiple recessed features. In some implementations, the fill is a dielectric material. In implementations, a top portion of the sidewalls of the multiple recessed features near the surface of the substrate have a width that is greater than a bottom portion of the sidewalls near the bottom surfaces of the multiple recessed features. In another implementation, the first material is a dielectric material.

[0029] In implementations, a method includes providing a substrate having a surface including multiple recessed features. The method also includes depositing a blocking layer on the surface of the substrate and a portion of sidewalls of the multiple recessed features. The method includes depositing a fill in the multiple recessed features. The fill may be repelled by the surface and the portion of the sidewalls having the blocking layer.

[0030] In one implementation, depositing the blocking layer on the surface of the substrate and the portion of the sidewalls of the multiple recessed features includes selectively fluorinating the surface of the substrate and the portion of the sidewalls of the multiple recessed features using an angular CF₄ plasma treatment. In another implementation, depositing the blocking layer on the surface of the substrate and the portion of the sidewalls of the multiple recessed features includes depositing self-assembled monolayers on the surface of the substrate and the portion of the sidewalls.

[0031] In implementations, the method further includes depositing an adhesion promoter on a bottom portion of the multiple recessed features. The adhesion promoter may be repelled by the portion of the surface and the portion of the sidewalls having the blocking layer.

[0032] In one implementation, the method further includes removing the blocking layer from the surface and the portion of the sidewalls of the multiple recessed features. The method also includes depositing the adhesion promoter on the portion of the sidewalls of the multiple recessed features. The method includes depositing the fill in the multiple recessed features. The fill covers the portion of the sidewalls of the multiple recessed features having the deposited adhesion promoter. In implementations, removing the blocking layer from the surface and the portion of the sidewalls of the multiple recessed features includes at least one of a hydrogen plasma, oxygen plasma or wet etch process.

[0033] Figures 1-3 illustrate a process for filling recessed features of a substrate, according to implementations. Fabrication processes 100 through 300 include substrate 110 at various stages of the fabrication process, according to one exemplary implementation. It may be noted that fabrication processes 100-300 are shown for purposes of illustration, rather than limitation. Fabrication processes 100-300 may be performed in any order, include any number of processes, and include additional, the same, or fewer processes. It may also be noted that for purposes of illustration, rather than limitation, materials are described for the various layers or structures illustrated in fabrication processes 100-300. Other materials, other than or in addition to the materials described with respect to Figures 1-3, may also be used in other implementations.

[0034] Figure 1 shows a process 100 of providing a substrate with recessed features, according to implementations. In one implementation, the substrate 110 may include a body having a surface that may be a dielectric material. In another implementation, the substrate 110 may include a body having a surface that may be a metal or metal oxide. The surface of the substrate 110 may include recessed features 130. The recessed features 130 may have a width 140 that is the distance between the sidewalls of the recessed features 130. The recessed features 130 may have a depth 150 that is the distance between the top surface of the substrate 110 and the bottom surface of the recessed features 130. The aspect ratio of the recessed features 130 may be the ratio of the depth 150 to the width 140 of the recessed features 130. For example, if the recessed features 130 had a depth 150 of 60 nanometers (nm) and a width 140 of 20 nm, then the recessed features 130 may have an aspect ratio of 3: 1 (e.g., 9:3). In one implementation, the recessed features 130 may have an aspect ratio between 3: 1-10: 1, inclusively. In one implementation, the recessed features 130 may have a depth 150 between 60-200 nm, inclusively. The recessed features 130 may have a bottom surface 120 that is formed of a material that is different from the material of substrate 110. In one implementation, the bottom surface 120 may be made of metal, composites, ceramics, or any other suitable material that is different from the material of substrate 110.

[0035] Figure 2 illustrates a process 200 of depositing a blocking layer on the substrate. A blocking layer 210 may be deposited on the top surface of the substrate 110 and the sidewalls of the recessed features 130. In one implementation, the blocking layer 210 may be formed from self-assembled monolayers (SAMs) that are organic molecular assemblies formed on surfaces by absorption and are organized into ordered domains. A chemically selective reaction may occur that allows the SAMs to react with the material of the body (e.g., the surface and sidewalls of recessed features 130) but not react with the bottom surfaces 120 of the recessed features 130. The SAMs may form a passivation layer, rendering the surface of the substrate 110 and the sidewalls of the recessed features 130 hydrophobic, blocking the deposition of a fill to ensure the fill is deposited in the desired location (e.g., the bottom surface 120). The type of SAMs used for the blocking layer 210 may correspond to the material of the fill, which will be discussed in more detail at Figure 3. In one implementation, the SAMs may be silane based SAMs and the fill may be a dielectric material. SAMs that attach preferentially to dielectric surfaces may be assembled in a solution. In another implementation, the SAMs may be deposited using a spin coating process. The SAMs may be applied to the center of the substrate 1 10 and the substrate 110 may be spun to spread the SAMs by centrifugal force. In yet another implementation, the SAMs may be deposited using a vapor phase deposition process where SAMs in a vapor phase are condensed to form a thin film. Examples of SAMs may include molecules with small or long (C 1-C22) alkyl chains or fluorinated chains and head groups that may include alkoxysilanes, aminosilanes and chlorosilanes. In another implementation, the SAMs may be thiol based SAMs and the dielectric material may be a metal or metal oxide. SAMs that attach preferentially to metals or metal oxides may be assembled in the solution, spin coating or vapor phase deposition using molecules with head groups such as alkenes, alkynes, amines, phosphines, thiols, phosphonic acids or carboxylic acids that selectively combine with metals. Other examples of chemical compounds that may be used as passivants include

octadecylphosphonic acid or octadecylthiol. In some implementations, the blocking layer 210 may react with both metals and dielectric material.

[0036] In another implementation, the blocking layer 210 may be applied to the surface of the substrate 110 and the sidewalls of the recessed features 130 using plasmas to form a coating of fluorine-containing groups on the surface and sidewalls. The plasma may be deposited using an angular plasma exposure that allows the coating to be applied to a desired depth in the recessed features 130. In one implementation, the plasma may be made with fluorine rich gases such as carbon tetrafluoride (CF₄), difluoromethane (CF₂H₂) or a mixture of both gases. In another implementation, the CF₄ or CF₂H₂ may be mixed with other gases such as CH4, silane, or other similar gases. The coating formed by the plasma may render the surface of the substrate 110 and the sidewalls of the recessed features 130 hydrophobic, blocking the deposition of a fill to ensure the fill may be deposited in the desired location (e.g., the bottom surface 120). In a further implementation, a combination of plasmas and SAMs may be used. The surface of the substrate 110 and the sidewalls of the recessed features 130 may be exposed to plasma, which allow hydrophobic SAMs to be grafted to the surface and sidewalls exposed to the plasma. The grafted hydrophobic SAMs may then prevent the deposition of a fill, as previously described.

[0037] Figure 3 illustrates a process 300 of depositing a fill in the recessed features of a substrate. A fill 310 may be deposited in the recessed features 130 of the substrate 110. In one implementation, the fill 310 may be deposited using a spin coating process. The fill 310 may be applied to the center of the substrate 110 and the substrate 110 may be spun to spread the fill 110 by centrifugal force. In another implementation, the fill 310 may be deposited using atomic layer deposition (ALD). The substrate 110 may be exposed to ALD precursors that react to surfaces of the substrate that are not covered by the blocking layer 210 (e.g., bottom surface 120). In a further implementation, the fill 310 may be deposited using chemical vapor deposition (CVD). The substrate 110 may be exposed to one or more volatile precursors that may react to surfaces of the substrate that are not covered by the blocking layer 210 (e.g., the bottom surface 120). The blocking layer 210 may prevent the deposition of the fill 310 on the surface of the substrate 110 and the sidewalls of the recessed features 130. Therefore, the blocking layer 210 may promote the deposition of the fill 310 on the bottom surface 120 of the recessed features 130. Once the fill 310 has covered the bottom surface 120 of the recessed features 130, the fill 310 may fill the remaining volume of the recessed features 130. This may result in the fill 310 covering the sidewalls and bottom surfaces of the recessed features 130, where the fill 310 does not contain voids or gaps. In one implementation, the fill 310 may be a dielectric material. In another implementation, the fill 310 may be a conductive material. Examples of conductive materials may include, but are not limited to, copper (Cu), cobalt (Co), nickel (Ni), ruthenium (Ru), tungsten (W), molybdenum (Mo), alloys (e.g., Co-Ni, Co-Ru, Ni-Ru, Co-W, Ni-W, etc.), conductive metal oxides or any suitable material that is different from the material of the substrate 110. [0038] Figures 4-6 illustrate a process for filling recessed features of a substrate, according to implementations. Fabrication processes 400 through 600 include substrate 410 at various stages of the fabrication process, according to one exemplary implementation. It may be noted that fabrication processes 400-600 are shown for purposes of illustration, rather than limitation. Fabrication processes 400-600 may be performed in any order, include any number of processes, and include additional, the same, or fewer processes. It may also be noted that for purposes of illustration, rather than limitation, materials are described for the various layers or structures illustrated in fabrication processes 400-600. Other materials, other than or in addition to the materials described with respect to Figures 4-6, may also be used in other implementations.

[0039] Figure 4 shows a process 400 of providing a substrate with recessed features, according to implementations. The substrate 410 may include a body having a surface that may be a dielectric material. The surface of the substrate 410 may include recessed features 420 having surfaces that are the same material as the substrate 410. The recessed features 420 may have a width 430 that is the distance between the sidewalls of the recessed features 420. The recessed features 420 may have a depth 440 that is the distance between the top surface of the substrate 410 and the bottom surface of the recessed features 420. The aspect ratio of the recessed features 430 may be the ratio of the depth 440 to the width 430 of the recessed features 420. In one implementation, the recessed features 420 may have an aspect ratio between 3: 1-10: 1, inclusively.

[0040] Figure 5 illustrates a process 500 of depositing a blocking layer on the substrate. A blocking layer 510 may be deposited on the top surface of the substrate 410 and the sidewalls of the recessed features 420. In one implementation, the blocking layer 510 may be applied to the surface of the substrate 410 and the sidewalls of the recessed features 420 using plasmas to form a coating of fluorine-containing groups on the surface and sidewalls. The plasma may be deposited using an angular plasma exposure that allows the coating to be applied to a desired depth in the recessed features 420. In one implementation, the plasma may be made with fluorine rich gases such as CF₄, CF₂H₂ or a mixture of both gases. In another implementation, the CF₄ or CF₂H₂ may be mixed with other gases such as CH₄ silane, or other similar gases. The coating formed by the plasma may render the surface of the substrate 410 and a portion of the sidewalls of the recessed features 420 hydrophobic, blocking the deposition of a fill to ensure the fill may be deposited in the desired location (e.g., the bottom surface of recessed features 420). In another implementation, a combination of plasmas and SAMs may be used. The surface of the substrate 410 and the sidewalls of the recessed features 420 may be exposed to plasma, which allow hydrophobic SAMs to be grafted to the surface and sidewalls that were exposed to the plasma. The grafted hydrophobic SAMs may then block the deposition of a fill, as previously described.

[0041] Figure 6 illustrates a process 600 of depositing a fill in the recessed features of a substrate. A fill 610 may be deposited in the recessed features 420 of the substrate 410. In one implementation, the fill 610 may be deposited using a spin coating process. In another implementation, the fill 610 may be deposited using an ALD process. In a further

implementation, the fill 610 may be deposited using a CVD process. The blocking layer 510 may prevent the deposition of the fill 610 on the surface of the substrate 410 and the sidewalls of the recessed features 420. Therefore, the blocking layer 510 may promote the deposition of the fill 610 on the bottom surface of the recessed features 420. Once the fill 610 has covered the bottom surface of the recessed features 420, the fill 610 may be deposited to fill the remaining volume of the recessed features 420. This may result in the fill 610 covering the sidewalls and bottom surfaces of the recessed features 420, where the fill 610 does not contain voids or gaps. In one implementation, the fill 610 may be a dielectric material. In another implementation, the fill 610 may be a conductive material. Examples of conductive materials may include, but are not limited to, copper, cobalt, nickel, ruthenium, tungsten, molybdenum, conductive metal oxides or any suitable material that is different from the material of substrate 410.

[0042] Figures 7-12 illustrate a process for filling recessed features of a substrate, according to implementations. Fabrication processes 700 through 1200 include substrate 710 at various stages of the fabrication process, according to one exemplary implementation. It may be noted that fabrication processes 700-1200 are shown for purposes of illustration, rather than limitation. Fabrication processes 700-1200 may be performed in any order, include any number of processes, and include additional, the same, or fewer processes. It may also be noted that for purposes of illustration, rather than limitation, materials are described for the various layers or structures illustrated in fabrication processes 700-1200. Other materials, other than or in addition to the materials described with respect to Figures 7-12, may also be used in other

implementations .

[0043] Figure 7 shows a process 700 of providing a substrate with recessed features, according to implementations. The substrate 710 may correspond to the substrate 410 of Figure 4. The substrate 710 may include a body having a surface that may be a dielectric material. The surface of the substrate 710 may include recessed features 720 having surfaces that are the same material as the substrate 710. The recessed features 720 may have a width 730 that is the distance between the sidewalls of the recessed features 720. The recessed features 720 may have a depth 740 that is the distance between the top surface of the substrate 710 and the bottom surface of the recessed features 720. The aspect ratio of the recessed features 730 may be the ratio of the depth 740 to the width 730 of the recessed features 720. In one implementation, the recessed features 720 may have an aspect ratio between 3: 1-10: 1, inclusively.

[0044] Figure 8 illustrates a process 800 of depositing a blocking layer on the substrate. A blocking layer 810 may be deposited on the top surface of the substrate 710 and the sidewalls of the recessed features 720. In one implementation, the blocking layer 810 may be applied to the surface of the substrate 710 and a portion of the sidewalls of the recessed features 720 using plasmas to form a hydrophobic coating of fluorine-containing groups on the surface and sidewalls. The plasma may be deposited using an angular plasma exposure process that allows the coating to be applied to a desired depth in the recessed features 720. In one implementation, the plasma may be made with fluorine rich gases such as CF₄ or CF₂H₂ or a mixture of both gases. In another implementation, the CF₄ or CF₂H₂ may be mixed with other gases such as CH₄, silane or other similar gases. The coating formed by the plasma may render the surface of the substrate 710 and the sidewalls of the recessed features 720 hydrophobic, blocking the deposition of a fill and/or adhesion promoter to ensure the fill and/or adhesion promoter may be deposited in the desired location (e.g., the bottom surface of recessed features 720). In another

implementation, a combination of plasmas and SAMs may be used. The surface of the substrate 710 and the sidewalls of the recessed features 720 may be exposed to plasma, which allow hydrophobic SAMs to be grafted to the surface and sidewalls that were exposed to the plasma. The grafted hydrophobic SAMs may then block the deposition of a fill and/or adhesion promoter, as previously described. In some implementations, adhesion promoters may be grafted to the hydrophobic sidewalls and surfaces covered by the blocking layer 810.

[0045] Figure 9 shows a process 900 of depositing an adhesion promoter on the bottom portions of the recessed features of the substrate. The bottom portion may refer to an area of the sidewalls near the bottom surface of a recessed feature 720 and the bottom surface of the recessed feature 720. An adhesion promoter 910 may be deposited in the recessed features 720 of the substrate 710 and may increase the adhesion of a fill to the surfaces of the recessed features 720. The blocking layer 810 may prevent the deposition of the adhesion promoter 910 on the surface of the substrate 710 so that the adhesion promoter 910 may be deposited on the bottom portion of the recessed features 720. In one implementation, the adhesion promoter 910 may be deposited on a dielectric material and may be formed of silanes. Examples of silanes include, but are not limited to, amine, pyridyl, epoxy, phosphine or thiol terminated alkoxysilanes, aminosilanes and/or chloro silanes. In another implementation, the adhesion promoter 910 may be deposited on a metal or metal oxide and may be formed of amine, pyridyl, epoxy, phosphine or thiol terminated alkenes, alkynes, amines, phosphines, thiols, phosphoric acids or carboxylic acids SAMs. In one implementation, the adhesion promoter 910 may be deposited using a spin coating process. In another implementation, the adhesion promoter 910 may be deposited using ALD. The substrate 710 may be exposed to ALD precursors that react to surfaces of the substrate that are not covered by the blocking layer 810 (e.g., the bottom portions of recessed features 720), which may form a layer of adhesion promoter 910 on the bottom portions of recessed features 720. In a further implementation, the adhesion promoter 910 may be deposited using CVD. The substrate 710 may be exposed to one or more volatile precursors that may react to surfaces of the substrate that are not covered by the blocking layer 810 (e.g., the bottom portions of recessed features 720), which may form a layer of adhesion promoter 910 on the bottom portions of recessed features 720.

[0046] Figure 10 shows a process 1000 of depositing a fill in the bottom portions of the recessed features of the substrate. A fill 1010 may be deposited in the bottom portions of recessed features 720 of the substrate 710 that correspond to the surfaces covered in the adhesion promoter 910. In one implementation, the fill 1010 may be deposited using a spin coating process. In another implementation, the fill 1010 may be deposited using an ALD process. In a further

implementation, the fill 1010 may be deposited using a CVD process. The blocking layer 810 may prevent the deposition of the fill 1010 on the surface of the substrate 710 and the sidewalls of the recessed features 720. Therefore, the blocking layer 810 and the adhesion layer 910 may promote the deposition of the fill 1010 on the bottom portions of the recessed features 720. This may result in the fill 1010 covering the bottom portions of the recessed features 720 without having voids or gaps within the fill 1010. In one implementation, the fill 1010 may be a dielectric material. In another implementation, the fill 1010 may be a conductive material. Examples of conductive materials may include, but are not limited to, copper, cobalt, nickel, ruthenium, tungsten, molybdenum, conductive metal oxides or any suitable material that is different from the material of substrate 710.

[0047] Figure 11 illustrates a process 1100 of removing the blocking layer from the substrate and recessed features and depositing an adhesion promoter. The blocking layer 810 (not shown) of Figures 7-10 may be removed from the surface of the substrate 710 and surfaces of the recessed features 720 that are not covered by the fill 1010. Removing the blocking layer 810 may allow adhesion promoter 1110 to be deposited on the surfaces of the recessed features 720 that are not covered by the fill 1010. In one implementation, the blocking layer 810 may be removed using a plasma etching process, such as hydrogen or oxygen plasma. A masking material may be applied to the upper surface of the fill 1010 and adhesion promoter 910 that resists the plasma. The substrate 710 may be exposed to the plasma to remove the blocking layer 810, and the masking material may then be removed from the upper surface of the fill 1010 and adhesion promoter 910. In another implementation, the blocking layer 810 may be removed using an etching process. A masking material may be applied to the upper surface of the fill 1010 and adhesion promoter 910 that resists an etching chemical. The substrate 710 may be exposed to the etching chemical to remove the blocking layer 810, and the masking material may then be removed from the upper surface of the fill 1010 and adhesion promoter 910. In implementations where the blocking layer 810 reacts with both metals and dielectric materials, additional operations may be required to remove the blocking layer 810 from the surfaces of the substrate 710 and recessed features 720 using thermal annealing, dry etching or wet etching.

[0048] Once the blocking layer 810 has been removed from the surfaces of the substrate 710 and the recessed features 720, an adhesion promoter 1110 may be deposited on at least a portion of the surfaces of the recessed features 720 that are not covered by the fill 1010. In one

implementation, the adhesion promoter 1110 may be the same material as adhesion promoter 910. In one implementation, the adhesion promoter 1110 may be deposited using a spin coating process. In another implementation, the adhesion promoter 1110 may be deposited using ALD. In a further implementation, the adhesion promoter 1110 may be deposited using CVD. The adhesion promoter 1110 may increase the adhesion between a fill and the surfaces of the recessed features 720.

[0049] Figure 12 illustrates a process 1200 of depositing a fill in the recessed features of a substrate. A fill 1210 may be deposited in the recessed features 720 of the substrate 710. The adhesion promoter 1110 may increase the adhesion of the fill 1210 on the surface of the sidewalls of the recessed features 720. Therefore, the adhesion promoter 1110 may encourage the fill 1110 to cover the sidewalls of the recessed features. This may result in the fill 1210 filling a portion of the recessed features 720 without having voids or gaps within the fill 1210. In one implementation, the fill 1210 may be a dielectric material. In another implementation, the fill 1210 may be a conductive material. Examples of conductive materials may include, but are not limited to, copper, cobalt, nickel, ruthenium, tungsten, molybdenum, conductive metal oxides or any suitable material that is different from the material of substrate 710. Although Figures 11 and 12 illustrate the adhesion promoter 1110 and the fill 1210 being deposited to completely fill the volume of the recessed features 720, in some implementations the adhesion promoter 1110 and the fill 1210 may be deposited to fill a portion of the volume of the recessed features 720. Processes 1100 and 1200 may then be repeated multiple times until the volume of recessed features 720 are completely filled. [0050] In other implementations, the adhesion promoter 1110 may be deposited to completely cover the sidewalls of the recessed features 720 and a portion of the adhesion promoter 1110 may be removed using a plasma or etching process. The fill 1210 may be deposited to fill a portion of the volume of the recessed features 720 having surfaces where the adhesion promoter 1110 was not removed by the plasma or etching process. This process may be repeated to incrementally fill the recessed features 720 with fill 1210 until the volume of the recessed features 720 are completely filled.

[0051] Figure 13 illustrates a cross sectional view of a recessed feature 1300 of the substrate, according to implementations. The recessed feature 1300 may correspond to recessed features 130, 420, 720 of Figures 1, 4 and 7. The recessed feature 1300 may include a top portion 1310 near the surface of the substrate. In one implementation, the top portion 1310 may have a surface roughness resulting from the plasma or etching process as discussed in previous

implementations. In one implementation, the depth of the top portion 1310 may be dependent on the angle of tooling that drives plasma onto the top portion 1310 during an angular plasma process. The surface roughness may be quantified as deviations from the normal vector of a real surface (e.g., sidewalls of the recessed feature 1300) in its ideal form. In one implementation, the surface roughness may be between 0.5-5 nm, inclusively. In some implementations, the top surface of the substrate 1350 and the top portion 1310 may include a percentage of fluorine that may result from the hydrophobic coating of fluorine-containing groups described in Figures 2, 5 and 8. For example, the top surface of the substrate 1350 and the sidewalls of the top portion 1310 may have a percentage of fluorine between 0.1-10%, inclusive. In one implementation, the percentage of fluorine may decrease from the top surface of the substrate 1350 to the bottom of the top portion 1310. For example, the percentage of fluorine at the top surface of the substrate 1350 and at the top portion 1310 near the top surface 1350 (e.g. 1-5 nm from top surface 1350) may be 10% and the percentage of fluorine near the bottom of the top portion 1310 may be 0.1%. The recessed feature 1300 may include a bottom portion 1320 near the bottom surface of the recessed feature 1300. In some implementations, the surfaces in the bottom portion 1320 may be covered by the adhesion promoter described in Figure 9. The concentration of the adhesion promoter may be highest on the bottom surface of the recessed feature 1300. The concentration of the adhesion promoter may decrease from the bottom surface of the recessed feature to the top of the bottom portion 1320. In one implementation, the concentration of adhesion promoter may be dependent on the amount of hydroxy (OH) groups available for bonding with the adhesion promoter following the plasma or etching process. The concentration of the adhesion promoter may be inversely proportional to the concentration of fluorine, where areas having the highest concentration of fluorine will have the lowest concentration of adhesion promoter. For example, areas having the highest concentration of fluorine (e.g. top surface 1350) may have a 0-1% concentration of adhesion promoter and areas having the lowest concentration of fluorine (e.g., bottom surface of recessed feature) may have a 80-90% concentration of adhesion promoter. The recessed feature 1300 may include a first width 1330 that is the distance between the sidewalls at the top of the recessed feature 1300. The recessed feature 1300 may further include a second width 1340 that is the distance between the sidewalls near the bottom of the recessed feature 1300. In implementations having a surface roughness in the top portion 1310, the first width 1330 may be greater than the second width 1340 due to the removal of surface material in the top portion 1310 by the plasma or etching process. In one implementation, the first width may be 0.5-5 nm greater than the second width 1340, inclusively

[0052] Figure 14 is a flow diagram of a fabrication process for the filling of recessed features in a substrate, according to implementations. It may be noted that elements of Figures 1-13 may be described below to help illustrate method 1400. Method 1400 may be performed as one or more operations. It may be noted that method 1400 may be performed in any order and may include the same, more or fewer operations. It may be noted that method 1400 may be performed by one or more pieces of semiconductor fabrication equipment or fabrication tools.

[0053] Method 1400 begins at operation 1410 by providing a substrate having recessed features. In one implementation, the substrate may include multiple materials, as illustrated in Figure 1. In another implementation, the substrate may be a single material, as illustrated in Figures 4 and 7. At operation 1420, a blocking layer may be deposited on the surface of the substrate and at least a portion of the sidewalls of the recessed features. The blocking layer may be deposited using angular plasma, the deposition of SAMs or a combination of plasma and SAMs as described in previous implementations. At operation 1430, a fill may be deposited in the recessed features of the substrate. The fill may be repelled by the surfaces covered in the blocking layer, encouraging the deposition of the fill on surfaces not having the blocking layer. In one implementation, the fill may be a conductive material. In another implementation, the fill may be a dielectric material.

[0054] Figure 15 is a flow diagram of a fabrication process for the filling of recessed features in a substrate, according to implementations. It may be noted that elements of Figures 1-13 may be described below to help illustrate method 1500. Method 1500 may be performed as one or more operations. It may be noted that method 1500 may be performed in any order and may include the same, more or fewer operations. It may be noted that method 1500 may be performed by one or more pieces of semiconductor fabrication equipment or fabrication tools. [0055] At operation 1510, a substrate having recessed features is provided. At operation 1520, a blocking layer may be deposited on the surface of the substrate and at least a portion of the sidewalls of the recessed features. At operation 1530, an adhesion promoter may be deposited on a bottom portion of the recessed features. The blocking layer deposited at block 1520 may prevent the deposition of the adhesion promoter on the surface of the substrate and the portion of the sidewalls covered in the blocking layer. At operation 1540, a fill may be deposited in the bottom portion of the recessed features. The fill may be deposited in the bottom portion of the recessed features whose surfaces are covered in the adhesion promoter deposited at operation 1530. At operation 1550, the blocking layer deposited at operation 1520 may be removed from the surface of the substrate and the portion of the sidewalls of the recessed features. In one implementation, the blocking material may be removed by exposure to plasma. In another implementation, the blocking material may be removed by an etching process. In some implementations, only a portion of the blocking layer may be removed from the surface and sidewalls of the recessed features. At operation 1560, an adhesion promoter may be deposited on a portion of the sidewalls of the recessed features. In one implementation, the adhesion promoter may be the same material as the adhesion promoter deposited at operation 1530. At operation 1570, a fill may be deposited in the recessed features. The fill may be deposited to fill a portion of the recessed features corresponding to the portion of the sidewalls covered in the adhesion promoter deposited at operation 1560. In implementations where only a portion of the blocking layer is removed, operations 1550-1570 may be repeated to incrementally fill the recessed features of the substrate.

[0056] Figure 16 is a computing device built in accordance with implementations of the present disclosure. The computing device 1600 may include a number of components. In one implementation, the components are attached to one or more motherboards. In an alternate implementation, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as an SoC used for mobile devices. In implementations, the components in the computing device 1600 include, but are not limited to, an integrated circuit die 1602 and at least one communications logic unit 1608. In some implementations the communications logic unit 1608 is fabricated within the integrated circuit die 1602 while in other implementations the communications logic unit 1608 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 1602. The integrated circuit die 1602 may include a CPU 1604 as well as on-die memory 1606, often used as cache memory that can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM). It may be noted that in implementations integrated circuit die 1602 may include fewer elements (e.g., without processor 1604 and/or on-die memory 1606) or additional elements other than processor 1604 and on-die memory 1606. In one example, integrated circuit die 1602 may include a substrate 110 as described herein. In another example, integrated circuit die 1602 may include some or all the elements described herein, as well as include additional elements.

[0057] Computing device 1600 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1610 (e.g., DRAM), non-volatile memory 1612 (e.g., ROM or flash memory), a graphics processing unit 1614 (GPU), a digital signal processor 1616, a crypto processor 1642 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 1620, at least one antenna 1622 (in some implementations two or more antenna may be used), a display or a touchscreen display 1624 (e.g., that may include integrated circuit die 1602) , a touchscreen controller 1626, a battery 1628 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 1627, a compass (not shown), a motion coprocessor or sensors 1632 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 1634, a camera 1636, user input devices 1638 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1640 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 1600 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 1600 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 1600 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and

radiating electromagnetic waves in air or space.

[0058] The communications logic unit 1608 enables wireless communications for the transfer of data to and from the computing device 1600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some implementations they might not. The communications logic unit 1608 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1600 may include a plurality of communications logic units 1608. For instance, a first communications logic unit 1608 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 1608 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0059] The processor 1604 (also referred to "processing device" herein) of the computing device 1600 includes one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure. The term "processor" or "processing device" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processor 1604 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processor 1604 may be complex instruction set computing (CISC)

microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLrW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor 1604 may also be one or more special- purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like.

[0060] The communications logic unit 1608 may also include one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.

[0061] In further implementations, another component housed within the computing device 1600 may contain one or more devices, such as transistors, RF filters, or LEDs, that are formed in accordance with implementations of the present disclosure.

[0062] In various implementations, the computing device 1600 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an

entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1600 may be any other electronic device that processes data. [0063] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0064] Various operations are described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

[0065] The terms "over," "above" "under," "between," and "on" as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer deposited above or over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer deposited between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature deposited between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

[0066] The words "example" or "exemplary" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example' or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs.

Rather, use of the words "example" or "exemplary" is intended to present concepts in a concrete fashion. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless specified otherwise, or clear from context, "X includes A or B" is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances. In addition, the articles "a" and "an" as used in this application and the appended claims may generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term "an

implementation" or "one implementation" or "an implementation" or "one implementation" throughout is not intended to mean the same implementation or implementation unless described as such. The terms "first," "second," "third," "fourth," etc. as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation.

Claims

CLAIMS What is claimed is:

1. A computing device comprising:

a substrate comprised of a material;

a plurality of recessed features in a surface of the substrate, wherein the plurality of recessed features have an aspect ratio between 3: 1-10: 1, inclusive; and

a fill in the plurality of recessed features, wherein the fill comprises a second material that is different than the material of the substrate, wherein the fill covers sidewalls and bottom surfaces of the plurality of recessed features.

2. The computing device of claim 1, wherein the surface of the substrate and a top portion of the sidewalls of the plurality of recessed features near the surface of the substrate comprise 0.1-10% fluorine, inclusive.

3. The computing device of claim 1, wherein the fill comprises a conductive material.

4. The computing device of claim 1, wherein the fill comprises a dielectric material.

5. The computing device of claim 1, wherein a top portion of the sidewalls of the plurality of recessed features near the surface of the substrate has a width that is greater than a bottom portion of the sidewalls near the bottom surfaces of the plurality of recessed features.

6. The computing device of claim 5, wherein the top portion of the sidewalls of the plurality of recessed features have a surface roughness of 0.5-5 nanometers, inclusive.

7. The computing device of claim 1, wherein a bottom portion of the sidewalls near the bottom surfaces of the plurality of recessed features and the bottom surfaces of the plurality of recessed features comprise an adhesion promoter.

8. A computing device comprising:

a substrate comprised of a first material; a plurality of recessed features in a surface of the substrate, wherein the plurality of recessed features comprise bottom surfaces comprised of a second material that is different than the first material; and

a fill in the plurality of recessed features, wherein the fill comprises a third material that is different than the first material and the second material, wherein the fill covers sidewalls and the bottom surfaces of the plurality of recessed features.

9. The computing device of claim 8, wherein the surface of the substrate and a top portion of the sidewalls of the plurality of recessed features near the surface of the substrate comprise self- assembled monolayers.

10. The computing device of claim 8, wherein the surface of the substrate and a top portion of the sidewalls of the plurality of recessed features near the surface of the substrate comprise 0.1- 10% fluorine, inclusive.

11. The computing device of claim 10, wherein the percentage of fluorine is greatest on the surface of the substrate and decreases from a top of the top portion of the sidewalls of the plurality of recessed features to a bottom of the top portion of the sidewalls of the plurality of recessed features.

12. The computing device of claim 8, wherein the fill comprises a dielectric material.

13. The computing device of claim 8, wherein a top portion of the sidewalls of the plurality of recessed features near the surface of the substrate have a width that is greater than a bottom portion of the sidewalls near the bottom surfaces of the plurality of recessed features.

14. The computing device of claim 8, wherein the first material comprises a dielectric material.

15. A method of filling a plurality of recessed features comprising:

providing a substrate having a surface comprising the plurality of recessed features;

depositing a blocking layer on the surface of the substrate and a portion of sidewalls of the plurality of recessed features; and

depositing a fill in the plurality of recessed features, wherein the fill is repelled by the surface and the portion of the sidewalls having the blocking layer.

16. The method of claim 15, wherein depositing the blocking layer on the surface of the substrate and the portion of the sidewalls of the plurality of recessed features comprises:

selectively fluorinating the surface of the substrate and the portion of the sidewalls of the plurality of recessed features using an angular CF₄ plasma treatment.

17. The method of claim 15, wherein depositing the blocking layer on the surface of the substrate and the portion of the sidewalls of the plurality of recessed features comprises depositing self-assembled monolayers on the surface of the substrate and the portion of the sidewalls.

18. The method of claim 15, further comprising:

depositing an adhesion promoter on a bottom portion of the plurality of recessed features, wherein the adhesion promoter is repelled by the portion of the surface and the portion of the sidewalls having the blocking layer.

19. The method of claim 18, further comprising:

removing the blocking layer from the surface and the portion of the sidewalls of the plurality of recessed features;

depositing the adhesion promoter on the portion of the sidewalls of the plurality of recessed features; and

depositing the fill in the plurality of recessed features, wherein the fill covers the portion of the sidewalls of the plurality of recessed features having the deposited adhesion promoter.

20. The method of claim 19, wherein removing the blocking layer from the surface and the portion of the sidewalls of the plurality of recessed features comprises at least one of a hydrogen plasma, oxygen plasma or wet etch process.