WO2019005109A1 - Transistor with reinforced airgap spacers - Google Patents

Transistor with reinforced airgap spacers Download PDF

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Publication number
WO2019005109A1
WO2019005109A1 PCT/US2017/040306 US2017040306W WO2019005109A1 WO 2019005109 A1 WO2019005109 A1 WO 2019005109A1 US 2017040306 W US2017040306 W US 2017040306W WO 2019005109 A1 WO2019005109 A1 WO 2019005109A1
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WO
WIPO (PCT)
Prior art keywords
spacer
reinforced
semiconductive substrate
airgap
dielectric
Prior art date
Application number
PCT/US2017/040306
Other languages
French (fr)
Inventor
Marko Radosavljevic
Han Wui Then
Sansaptak DASGUPTA
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to PCT/US2017/040306 priority Critical patent/WO2019005109A1/en
Publication of WO2019005109A1 publication Critical patent/WO2019005109A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate

Definitions

  • Embodiments of the present description relate to the field of integrated circuit devices, and, more particularly, to the fabrication of integrated circuit transistors.
  • FIG. 1 illustrates a side cross sectional view of an integrated circuit transistor, as known in the art.
  • FIG. 2 illustrates a side cross sectional view of an integrated circuit transistor having reinforced airgap spacers, according to an embodiment of the present description.
  • FIGs. 3-9 illustrate cross sectional views of a process of fabricating an integrated circuit transistor having at least one reinforced airgap spacer, according to one embodiment of the present description.
  • FIG. 10 illustrates a computing device in accordance with one implementation of the present description.
  • over, “to”, “between” and “on” as used herein may refer to a relative position of one layer or component with respect to other layers or components.
  • One layer/component “over” or “on” another layer/component or bonded “to” another layer/component may be directly in contact with the other layer/component or may have one or more intervening layers/components.
  • One layer/component “between” layers/components may be directly in contact with the layers/components or may have one or more intervening layers/components.
  • Embodiments of the present description include an integrated circuit transistor which has a reinforced airgap spacer formed as a gate sidewall spacer and methods of fabricating the same.
  • the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the integrated circuit transistor.
  • FIG. 1 illustrates a cross-sectional view of an integrated circuit transistor 100 of one embodiment of the present description.
  • the integrated circuit transistor 100 may be formed by fabricating a transistor gate 120 formed on a semiconductive substrate 110.
  • the transistor gate 120 may include a transistor gate electrode 122 with a transistor gate dielectric 124 disposed between the transistor gate electrode 122 and the semiconductive substrate 1 10 and may further include a dielectric hard mask 126 capping the transistor gate electrode 122.
  • the transistor gate 120 may further include reinforced airgap spacers (illustrated as a first reinforced airgap spacer 130i and a second reinforced airgap spacer 1302) formed adjacent respective opposing sidewalls (illustrated as a first gate sidewall 128i and an opposing second gate sidewall 1282) of the transistor gate 120.
  • a first supporting dielectric structure 140i and a second supporting dielectric structure 1402 may be formed abutting each of the reinforced airgap spacers 130i and 1302, respectively, such that the reinforced airgap spacers 130i and 1302 are positioned between their respective supporting dielectric structures 140i and 1402, and the transistor gate 120.
  • a source region 152 and a drain region 154 may be formed in or on the semiconductor substrate 1 10, such as by ion implantation of appropriate dopants, on opposing sides of the transistor gate 120.
  • At least one interlayer dielectric material layer (illustrated as a first interlay er dielectric material layer 162 and a second interlay er dielectric material layer 164) may be disposed over the semiconductive substrate 110, and a source contact 172 and a drain contact 174 may be formed through the interlay er dielectric material layers 162, 164 to electrically connect with the source region 152 and the drain region 154, respectively.
  • the semiconductive substrate 110 formed from any suitable material.
  • the semiconductive substrate 110 may be a bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon- germanium or a III-V compound semiconductor material.
  • the semiconductive substrate 110 may comprise a silicon-on-insulator substrate (SOI), wherein an upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy -nitride, disposed on the bulk substrate.
  • SOI silicon-on-insulator substrate
  • the semiconductor substrate 110 may be formed directly from a bulk substrate and local oxidation is used to form electrically insulative portions in place of the above described upper insulator layer.
  • the semiconductor substrate 110 may also be other types of substrates, such as germanium, gallium arsenide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and the like, any of which may be combined with silicon.
  • the transistor gate electrode 122 may include any appropriate conductive material.
  • the transistor gate electrode 122 may comprise a metal, including, but not limited to, pure metal and alloys of titanium, tungsten, tantalum, aluminum, copper, ruthenium, cobalt, chromium, iron, palladium, molybdenum, manganese, vanadium, gold, silver, and niobium.
  • conductive metal carbides such as titanium carbide, zirconium carbide, tantalum carbide, tungsten carbide, and tungsten carbide, may also be used.
  • the transistor gate electrode 122 may also be made from a metal nitride, such as titanium nitride and tantalum nitride, or a conductive metal oxide, such as ruthenium oxide.
  • the transistor gate electrode 122 may also include alloys with rare earths, such as terbium and dysprosium, or noble metals such as platinum.
  • the transistor gate dielectric 124 may be formed from any well-known gate dielectric material, including but not limited to silicon dioxide (SiC ), silicon oxynitride (SiOxNy), silicon nitride (S13N4), and high-k dielectric materials, wherein the dielectric constant may comprise a value greater than about 4, such as hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, tantalum silicon oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • silicon dioxide SiC
  • SiOxNy silicon nitride
  • Si13N4 silicon nitride
  • high-k dielectric materials wherein the dielectric constant may comprise a value greater than about 4, such as hafnium oxide, hafnium silicon oxide,
  • the interlay er dielectric material layers 162, 164 may be any appropriate dielectric material, including, but not limited to, silicon dioxide, silicon nitride, and the like, and may be formed from a low-k (dielectric constant, k, such as 1.0-2.2) material.
  • the supporting dielectric structures 140i and 1402 may be any appropriate dielectric material, including, but not limited to, ceramic materials, such as aluminum nitride.
  • FIG. 2 illustrates a cross-sectional view of one of the reinforced airgap spacers of
  • the reinforced airgap spacer 130 may comprise a dielectric material shell 132 substantially surrounding a void 134, wherein the void may be filled with any substantially inert gas or gaseous substance, including by not limited to air. It is understood that the definition of the term "airgap" as used herein includes any void filled with any substantially inert gas or gaseous substance.
  • FIGs. 3-8 illustrate one embodiment for the fabrication of the integrated circuit transistor 100 of FIG. 1. It is understood that although the present description illustrates a specific transistor configuration, the embodiments of the present description may be applied to any transistor configuration, both non-planar and planar.
  • the transistor gate 120 may be formed on the semiconductive substrate 110.
  • the transistor gate 120 may be a sacrificial gate (shown), which would be removed and replaced in subsequent processing with the transistor gate electrode 122 (see FIG. 1) with the gate dielectric 124 (see FIG. 1) disposed between the transistor gate electrode 122 and the semiconductive substrate 110, as will be understood to those skilled in the art.
  • the transistor gate 120 could include the gate dielectric (not shown) and the gate electrode (not shown) at this point.
  • the functions and fabrication processes for the gate electrode and the gate dielectric are well known in the art and for the sake of conciseness and clarity will not be discussed herein.
  • a spacer material layer 136 may be conformally deposited over the transistor gate 120 and the semiconductive substrate 110.
  • the spacer material layer 136 may be made of any appropriate dielectric material, such as silicon nitride (e.g. S13N4), silicon oxynitride (e.g. SiON), silicon oxycarbonitride (e.g. SiOCN), or silicon carbonitride (e.g. SiCN).
  • the spacer material layer 136 may be deposited by any appropriate technique, including, but not limited to atomic layer deposition (“ALD”), chemical vapor deposition (“CVD”), such as plasma enhanced chemical vapor deposition (“PECVD”) and metal-organic chemical vapor deposition (“MOCVD”), and physical vapor deposition (“PVD”).
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • MOCVD metal-organic chemical vapor deposition
  • PVD physical vapor deposition
  • the spacer material layer 136 may be etched (shown with arrows 138), such as by a directional etch in a direction substantially parallel with the first gate sidewall 128i and the second gate sidewall 1282 of the transistor gate 120 with an appropriate etchant, to formed an intermediate first gate spacer 182 abutting the first gate sidewall 128i of the transistor gate 120 and an intermediate second gate spacer 184 abutting the second gate sidewall 1282 of the transistor gate 120, as well as expose portions of the semiconductive substrate 110.
  • a supporting dielectric material layer 142 may be conformally deposited over the transistor gate 120, the intermediate first gate spacer 182, the intermediate second gate spacer 184, and the exposed portions of the semiconductive substrate 110.
  • the supporting dielectric material layer 142 may be any appropriate dielectric material, including, but not limited to, ceramic materials, such as aluminum nitride.
  • the spacer material layer 170 may be deposited by any appropriate technique, including, but not limited to atomic layer deposition ("ALD”), chemical vapor deposition (“CVD”), such as plasma enhanced chemical vapor deposition (“PECVD”) and metal-organic chemical vapor deposition
  • the supporting dielectric material layer 142 may be an aluminum nitride layer deposited at a temperature of about 1000 degrees Celsius.
  • the supporting dielectric material layer 142 may be etched (shown with arrows 144), such as by a directional etch in a direction substantially parallel with the first gate sidewall 128i and the second gate sidewall 1282 of the transistor gate 120 with an appropriate etchant, to form the structural dielectric the first supporting dielectric structure 140i abutting the first gate sidewall 128i of the transistor gate 120 and the second supporting dielectric structure 1402 abutting the second gate sidewall 1282 of the transistor gate 120, as well as expose portions of the semiconductive substrate 110.
  • the formation of supporting dielectric material layer 142 results in a hardening of the dielectric near its periphery, which results in a differential in the etching rates between dielectric material in a center area 186 (demarked with a dashed line) of the intermediate first gate spacer 182 and the intermediate second gate spacer 184, and the exterior area 188 of the intermediate first gate spacer 182 and the intermediate second spacer 184.
  • the center areas 186 of the intermediate first gate spacer 182 and the intermediate second gate spacer 184 may then be etched, such as with a wet etch, to remove the dielectric material in the center area 186 (see FIG.
  • the void 134 may be filled with a gas. In a specific embodiment, the void 134 may be filled with air.
  • the source region 152, the drain region 154, the interlay er dielectric material layers 162 and 164, the source contact 172, and the drain contact 174, as shown in FIG. 1, may be formed along with a replacement gate process to fabricate the integrated circuit transistor 100, as shown in FIG. 1.
  • the processes for forming these structures as well known in the art and for the sake of conciseness and clarity will not be discussed herein.
  • first supporting dielectric structure 140i and the second supporting dielectric structure 1402 may be removed during processes to form a first additional airgap spacer 190i and a second additional airgap spacer 1902, as shown in FIG. 9.
  • FIG. 10 illustrates a computing device 200 in accordance with one implementation of the present description.
  • the computing device 200 houses a board 202.
  • the board may include a number of integrated circuit components, including but not limited to a
  • processor 204 at least one communication chip 206A, 206B, volatile memory 208, (e.g., DRAM), non-volatile memory 210 (e.g., ROM), flash memory 212, a graphics processor or CPU 214, a digital signal processor (not shown), a crypto processor (not shown), a chipset 216, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory 208 e.g., DRAM
  • non-volatile memory 210 e.g., ROM
  • flash memory 212 e.g.,
  • the communication chip enables wireless communications for the transfer of data to and from the computing device.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing device may include a plurality of communication chips.
  • a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • processor may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • any of the integrated components within the computing device 200 having integrated circuit transistors may include reinforced airgap spacers positioned between a gate electrode and at least one of a source contact and a drain contact, which may significantly reduce capacitive coupling between the gate electrode and at least one of the source contact and the drain contact, thereby reducing circuit delay compared to integrated circuit transistors having spacers formed from solid or semi-solid dielectric materials, as described herein.
  • the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.
  • the computing device may be any other electronic device that processes data. It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGs. 1 -10. The subject matter may be applied to other integrated circuit transistor configurations, as will be understood to those skilled in the art.
  • Example 1 is a integrated circuit transistor, comprising a semiconductive substrate, a transistor gate formed on the semiconductive substrate, and at least one reinforced airgap spacer formed on the semiconductive substrate and abutting the transistor gate, wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
  • Example 2 the subject matter of Example 1 can optionally include at least one supporting dielectric structure formed on the semiconductive substrate, wherein the at least one supporting dielectric structure abuts the at least one reinforced airgap spacer.
  • Example 3 the subject matter of Example 2 can optionally include the at least one supporting dielectric structure comprising a ceramic material.
  • Example 4 the subject matter of Example 3 can optionally include the ceramic material comprising aluminum nitride.
  • Example 5 the subject matter of any of Examples 1 to 4 can optionally include the reinforced airgap spacer having a gas disposed within the void.
  • Example 6 the subject matter of Example 5 can optionally include the gas comprising air.
  • Example 7 the subject matter of any of Examples 1 to 4 can optionally include at least one additional airgap spacer abutting the at least one reinforced airgap spacer.
  • Example 8 the subject matter of any of Examples 1 to 4 can optionally include a source region and a drain region formed in the semiconductive substrate, at least one interlayer dielectric disposed over the semiconductive substrate, a source contact extending through the at least one interlayer dielectric and electrically contacting the source region, a drain contact extending through the at least one interlayer dielectric and electrically contacting the source region, wherein the transistor gate is positioned between the source contact and the drain contact, and wherein the reinforced airgap spacer is positioned between the transistor gate and at least one of the source contact and the drain contact.
  • Example 9 is a method of fabricating an integrated circuit transistor comprising: forming a semiconductive substrate; forming a transistor gate on the semiconductive substrate; and forming at least one reinforced airgap spacer, wherein the at least one reinforced airgap spacer abuts the transistor gate, and wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
  • Example 10 the subject matter of Example 9 can optionally include forming the airgap spacer comprising depositing a spacer material layer comprising a dielectric material over the transistor gate and exposed portions of the semiconductive substrate; etching the dielectric spacer material layer to form at least one intermediate gate spacer; altering the etch rate of the dielectric material in a center area of the intermediate gate spacer and the dielectric material in an exterior area of the intermediate gate spacer; and etching the at least one intermediate gate spacer to remove the dielectric material in the center area.
  • Example 11 the subject matter of Example 10 can optionally include altering the etch rate of the dielectric material in a center area of the intermediate gate spacer and the dielectric material in an exterior area of the intermediate gate spacer comprising depositing a supporting dielectric material layer over the transistor gate, the at least one intermediate gate spacer, and exposed portions of the semiconductive substrate.
  • Example 12 the subject matter of Example 1 1 can optionally include etching the supporting dielectric material layer to form at least one supporting dielectric structure on the semiconductive substrate, wherein the at least one supporting dielectric structure abuts the at least one reinforced airgap spacer.
  • Example 13 the subject matter of Example 1 1 can optionally include forming the supporting dielectric material layer comprises forming the supporting dielectric material layer structure from a ceramic material.
  • Example 14 the subject matter of Example 13 can optionally include forming the supporting dielectric material layer structure from a ceramic material comprises forming the supporting dielectric material layer structure from aluminum nitride.
  • Example 15 the subject matter of Example 14 can optionally include forming the supporting dielectric material layer structure from aluminum nitride comprises depositing aluminum nitride at temperature of about 1000 degrees Celsius.
  • Example 16 the subject matter of Example 12 can optionally include forming at least one additional airgap spacer abutting the at least one reinforced airgap spacer.
  • Example 17 the subject matter of Example 18 can optionally include forming the at least one additional airgap spacer comprising removing the at least one supporting dielectric structure.
  • Example 18 the subject matter of Example 9 can optionally include the at least one reinforced airgap spacer including a gas disposed within the void.
  • Example 19 the subject matter of Example 16 can optionally include the gas comprising air.
  • Example 20 the subject matter of any of Examples 9 to 19 can optionally include forming a source region and a drain region formed in the semiconductive substrate, forming at least one interlay er dielectric over the semiconductive substrate, forming a source contact extending through the at least one interlayer dielectric and electrically contacting the source region, forming a drain contact extending through the at least one interlayer dielectric and electrically contacting the source region, wherein the transistor gate is positioned between the source contact and the drain contact, and wherein the reinforced airgap spacer is positioned between the transistor gate and at least one of the source contact and the drain contact
  • Example 21 is an electronic system, comprising: a board; and an integrated circuit component attached to the board, wherein the integrated circuit component includes a microelectronic transistor comprising a semiconductive substrate; a transistor gate formed on the semiconductive substrate; and at least one reinforced airgap spacer formed on the semiconductive substrate and abutting the transistor gate, wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
  • the integrated circuit component includes a microelectronic transistor comprising a semiconductive substrate; a transistor gate formed on the semiconductive substrate; and at least one reinforced airgap spacer formed on the semiconductive substrate and abutting the transistor gate, wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
  • Example 22 the subject matter of Example 21 can optionally include at least one supporting dielectric structure formed on the semiconductive substrate, wherein the at least one supporting dielectric structure abuts the at least one reinforced airgap spacer.
  • Example 23 the subject matter of Example 22 can optionally include the at least one supporting dielectric structure comprising a ceramic material.
  • Example 24 the subject matter of Example 23 can optionally include the ceramic material comprising aluminum nitride.
  • Example 25 the subject matter of any of Examples 21 to 24 can optionally include the reinforced airgap spacer having a gas disposed within the void.
  • Example 26 the subject matter of Example 25 can optionally include the gas comprising air.
  • Example 27 the subject matter of any of Examples 21 to 24 can optionally include at least one additional airgap spacer abutting the at least one reinforced airgap spacer.
  • Example 28 the subject matter of any of Examples 21 to 24 can optionally include a source region and a drain region formed in the semiconductive substrate, at least one interlayer dielectric disposed over the semiconductive substrate, a source contact extending through the at least one interlayer dielectric and electrically contacting the source region, a drain contact extending through the at least one interlayer dielectric and electrically contacting the source region, wherein the transistor gate is positioned between the source contact and the drain contact, and wherein the reinforced airgap spacer is positioned between the transistor gate and at least one of the source contact and the drain contact.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

An integrated circuit transistor may be fabricated having a reinforced airgap spacer formed as a gate sidewall spacer, such that the reinforced airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the integrated circuit transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the reinforced airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the integrated circuit transistor.

Description

TRANSISTOR WITH REINFORCED AIRGAP SPACERS
TECHNICAL FIELD
Embodiments of the present description relate to the field of integrated circuit devices, and, more particularly, to the fabrication of integrated circuit transistors.
BACKGROUND
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the semiconductor industry for the fabrication of integrated circuit devices. To achieve these goals, transistors within the integrated circuit devices must scale down, i.e. become smaller. The reduction in the size of the transistors within the integrated circuit devices has resulted in difficulties with regard to the performance and efficiency of the transistors. One such difficulty is capacitive coupling between a gate electrode and a source contact and/or a drain contact of the transistor, which may increase circuit delay. This capacitive coupling is generally mitigated by gate sidewall spacers positioned between the transistor gate electrode and the source/drain contacts. However, integrated circuit transistors are becoming so small that the solid or semi-solid dielectric materials used to form the gate sidewall spacers do not have a low enough dielectronic constant to prevent capacitive coupling. One solution is to replace the gate sidewall spacers with gaps filled with a gaseous substrate (known as an "airgap spacer"), which has a significantly lower dielectric constant than that of solid or semi-solid dielectric materials. However, as such airgap spacers have no structure integrity in and of themselves, they are prone to collapsing. Thus, there has been a need to improve the design, materials used, and/or in their fabrication processes for forming airgap spacers.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The present disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
FIG. 1 illustrates a side cross sectional view of an integrated circuit transistor, as known in the art.
FIG. 2 illustrates a side cross sectional view of an integrated circuit transistor having reinforced airgap spacers, according to an embodiment of the present description.
FIGs. 3-9 illustrate cross sectional views of a process of fabricating an integrated circuit transistor having at least one reinforced airgap spacer, according to one embodiment of the present description.
FIG. 10 illustrates a computing device in accordance with one implementation of the present description.
DESCRIPTION OF EMBODIMENTS
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.
The terms "over", "to", "between" and "on" as used herein may refer to a relative position of one layer or component with respect to other layers or components. One layer/component "over" or "on" another layer/component or bonded "to" another layer/component may be directly in contact with the other layer/component or may have one or more intervening layers/components. One layer/component "between" layers/components may be directly in contact with the layers/components or may have one or more intervening layers/components.
Embodiments of the present description include an integrated circuit transistor which has a reinforced airgap spacer formed as a gate sidewall spacer and methods of fabricating the same. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the integrated circuit transistor.
FIG. 1 illustrates a cross-sectional view of an integrated circuit transistor 100 of one embodiment of the present description. The integrated circuit transistor 100 may be formed by fabricating a transistor gate 120 formed on a semiconductive substrate 110. The transistor gate 120 may include a transistor gate electrode 122 with a transistor gate dielectric 124 disposed between the transistor gate electrode 122 and the semiconductive substrate 1 10 and may further include a dielectric hard mask 126 capping the transistor gate electrode 122. The transistor gate 120 may further include reinforced airgap spacers (illustrated as a first reinforced airgap spacer 130i and a second reinforced airgap spacer 1302) formed adjacent respective opposing sidewalls (illustrated as a first gate sidewall 128i and an opposing second gate sidewall 1282) of the transistor gate 120. A first supporting dielectric structure 140i and a second supporting dielectric structure 1402 may be formed abutting each of the reinforced airgap spacers 130i and 1302, respectively, such that the reinforced airgap spacers 130i and 1302 are positioned between their respective supporting dielectric structures 140i and 1402, and the transistor gate 120. A source region 152 and a drain region 154 may be formed in or on the semiconductor substrate 1 10, such as by ion implantation of appropriate dopants, on opposing sides of the transistor gate 120. At least one interlayer dielectric material layer (illustrated as a first interlay er dielectric material layer 162 and a second interlay er dielectric material layer 164) may be disposed over the semiconductive substrate 110, and a source contact 172 and a drain contact 174 may be formed through the interlay er dielectric material layers 162, 164 to electrically connect with the source region 152 and the drain region 154, respectively.
The semiconductive substrate 110 formed from any suitable material. In one embodiment, the semiconductive substrate 110 may be a bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon- germanium or a III-V compound semiconductor material. In other embodiments, the semiconductive substrate 110 may comprise a silicon-on-insulator substrate (SOI), wherein an upper insulator layer composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy -nitride, disposed on the bulk substrate.
Alternatively, the semiconductor substrate 110 may be formed directly from a bulk substrate and local oxidation is used to form electrically insulative portions in place of the above described upper insulator layer. The semiconductor substrate 110 may also be other types of substrates, such as germanium, gallium arsenide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, and the like, any of which may be combined with silicon.
The transistor gate electrode 122 may include any appropriate conductive material. In one embodiment, the transistor gate electrode 122 may comprise a metal, including, but not limited to, pure metal and alloys of titanium, tungsten, tantalum, aluminum, copper, ruthenium, cobalt, chromium, iron, palladium, molybdenum, manganese, vanadium, gold, silver, and niobium. Less conductive metal carbides, such as titanium carbide, zirconium carbide, tantalum carbide, tungsten carbide, and tungsten carbide, may also be used. The transistor gate electrode 122 may also be made from a metal nitride, such as titanium nitride and tantalum nitride, or a conductive metal oxide, such as ruthenium oxide. The transistor gate electrode 122 may also include alloys with rare earths, such as terbium and dysprosium, or noble metals such as platinum.
The transistor gate dielectric 124 may be formed from any well-known gate dielectric material, including but not limited to silicon dioxide (SiC ), silicon oxynitride (SiOxNy), silicon nitride (S13N4), and high-k dielectric materials, wherein the dielectric constant may comprise a value greater than about 4, such as hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, tantalum silicon oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
The interlay er dielectric material layers 162, 164 may be any appropriate dielectric material, including, but not limited to, silicon dioxide, silicon nitride, and the like, and may be formed from a low-k (dielectric constant, k, such as 1.0-2.2) material. The supporting dielectric structures 140i and 1402 may be any appropriate dielectric material, including, but not limited to, ceramic materials, such as aluminum nitride.
FIG. 2 illustrates a cross-sectional view of one of the reinforced airgap spacers of
FIG. 1, labeled as reinforced airgap spacer 130, according to one embodiment of the present description. As illustrated in FIG. 2, the reinforced airgap spacer 130 may comprise a dielectric material shell 132 substantially surrounding a void 134, wherein the void may be filled with any substantially inert gas or gaseous substance, including by not limited to air. It is understood that the definition of the term "airgap" as used herein includes any void filled with any substantially inert gas or gaseous substance.
FIGs. 3-8 illustrate one embodiment for the fabrication of the integrated circuit transistor 100 of FIG. 1. It is understood that although the present description illustrates a specific transistor configuration, the embodiments of the present description may be applied to any transistor configuration, both non-planar and planar.
As shown in FIG. 3, the transistor gate 120 may be formed on the semiconductive substrate 110. The transistor gate 120 may be a sacrificial gate (shown), which would be removed and replaced in subsequent processing with the transistor gate electrode 122 (see FIG. 1) with the gate dielectric 124 (see FIG. 1) disposed between the transistor gate electrode 122 and the semiconductive substrate 110, as will be understood to those skilled in the art. Thus, the transistor gate 120 could include the gate dielectric (not shown) and the gate electrode (not shown) at this point. The functions and fabrication processes for the gate electrode and the gate dielectric are well known in the art and for the sake of conciseness and clarity will not be discussed herein.
As shown in FIG. 4, a spacer material layer 136 may be conformally deposited over the transistor gate 120 and the semiconductive substrate 110. The spacer material layer 136 may be made of any appropriate dielectric material, such as silicon nitride (e.g. S13N4), silicon oxynitride (e.g. SiON), silicon oxycarbonitride (e.g. SiOCN), or silicon carbonitride (e.g. SiCN). The spacer material layer 136 may be deposited by any appropriate technique, including, but not limited to atomic layer deposition ("ALD"), chemical vapor deposition ("CVD"), such as plasma enhanced chemical vapor deposition ("PECVD") and metal-organic chemical vapor deposition ("MOCVD"), and physical vapor deposition ("PVD").
As shown in FIG. 5, the spacer material layer 136 (see FIG. 4) may be etched (shown with arrows 138), such as by a directional etch in a direction substantially parallel with the first gate sidewall 128i and the second gate sidewall 1282 of the transistor gate 120 with an appropriate etchant, to formed an intermediate first gate spacer 182 abutting the first gate sidewall 128i of the transistor gate 120 and an intermediate second gate spacer 184 abutting the second gate sidewall 1282 of the transistor gate 120, as well as expose portions of the semiconductive substrate 110.
As shown in FIG. 6, a supporting dielectric material layer 142 may be conformally deposited over the transistor gate 120, the intermediate first gate spacer 182, the intermediate second gate spacer 184, and the exposed portions of the semiconductive substrate 110. The supporting dielectric material layer 142 may be any appropriate dielectric material, including, but not limited to, ceramic materials, such as aluminum nitride. The spacer material layer 170 may be deposited by any appropriate technique, including, but not limited to atomic layer deposition ("ALD"), chemical vapor deposition ("CVD"), such as plasma enhanced chemical vapor deposition ("PECVD") and metal-organic chemical vapor deposition
("MOCVD"), and physical vapor deposition ("PVD"). In one embodiment, the supporting dielectric material layer 142 may be an aluminum nitride layer deposited at a temperature of about 1000 degrees Celsius.
As shown in FIG. 7, the supporting dielectric material layer 142 may be etched (shown with arrows 144), such as by a directional etch in a direction substantially parallel with the first gate sidewall 128i and the second gate sidewall 1282 of the transistor gate 120 with an appropriate etchant, to form the structural dielectric the first supporting dielectric structure 140i abutting the first gate sidewall 128i of the transistor gate 120 and the second supporting dielectric structure 1402 abutting the second gate sidewall 1282 of the transistor gate 120, as well as expose portions of the semiconductive substrate 110.
As shown in FIGs. 6 and 7, the formation of supporting dielectric material layer 142 results in a hardening of the dielectric near its periphery, which results in a differential in the etching rates between dielectric material in a center area 186 (demarked with a dashed line) of the intermediate first gate spacer 182 and the intermediate second gate spacer 184, and the exterior area 188 of the intermediate first gate spacer 182 and the intermediate second spacer 184. As shown in FIG. 8, the center areas 186 of the intermediate first gate spacer 182 and the intermediate second gate spacer 184 (see FIG. 7) may then be etched, such as with a wet etch, to remove the dielectric material in the center area 186 (see FIG. 7), which results in the reinforced airgap spacers 130i and 1302, or, in specific, the removal of the dielectric material forms the void 134 of the reinforced airgap space 130 of FIG. 2 and remaining dielectric material forms the dielectric material shell 132 of FIG. 2, which substantially surrounds the void 134. In one embodiment, the void 134 may be filled with a gas. In a specific embodiment, the void 134 may be filled with air.
The source region 152, the drain region 154, the interlay er dielectric material layers 162 and 164, the source contact 172, and the drain contact 174, as shown in FIG. 1, may be formed along with a replacement gate process to fabricate the integrated circuit transistor 100, as shown in FIG. 1. The processes for forming these structures as well known in the art and for the sake of conciseness and clarity will not be discussed herein.
In a further embodiment, the first supporting dielectric structure 140i and the second supporting dielectric structure 1402 may be removed during processes to form a first additional airgap spacer 190i and a second additional airgap spacer 1902, as shown in FIG. 9.
FIG. 10 illustrates a computing device 200 in accordance with one implementation of the present description. The computing device 200 houses a board 202. The board may include a number of integrated circuit components, including but not limited to a
processor 204, at least one communication chip 206A, 206B, volatile memory 208, (e.g., DRAM), non-volatile memory 210 (e.g., ROM), flash memory 212, a graphics processor or CPU 214, a digital signal processor (not shown), a crypto processor (not shown), a chipset 216, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the integrated circuit components may be physically and electrically coupled to the board 202. In some implementations, at least one of the integrated circuit components may be a part of the processor 204.
The communication chip enables wireless communications for the transfer of data to and from the computing device. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
Any of the integrated components within the computing device 200 having integrated circuit transistors may include reinforced airgap spacers positioned between a gate electrode and at least one of a source contact and a drain contact, which may significantly reduce capacitive coupling between the gate electrode and at least one of the source contact and the drain contact, thereby reducing circuit delay compared to integrated circuit transistors having spacers formed from solid or semi-solid dielectric materials, as described herein.
In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data. It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGs. 1 -10. The subject matter may be applied to other integrated circuit transistor configurations, as will be understood to those skilled in the art.
The following examples pertain to further embodiments, wherein Example 1 is a integrated circuit transistor, comprising a semiconductive substrate, a transistor gate formed on the semiconductive substrate, and at least one reinforced airgap spacer formed on the semiconductive substrate and abutting the transistor gate, wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
In Example 2, the subject matter of Example 1 can optionally include at least one supporting dielectric structure formed on the semiconductive substrate, wherein the at least one supporting dielectric structure abuts the at least one reinforced airgap spacer.
In Example 3, the subject matter of Example 2 can optionally include the at least one supporting dielectric structure comprising a ceramic material.
In Example 4, the subject matter of Example 3 can optionally include the ceramic material comprising aluminum nitride.
In Example 5, the subject matter of any of Examples 1 to 4 can optionally include the reinforced airgap spacer having a gas disposed within the void.
In Example 6, the subject matter of Example 5 can optionally include the gas comprising air.
In Example 7, the subject matter of any of Examples 1 to 4 can optionally include at least one additional airgap spacer abutting the at least one reinforced airgap spacer.
In Example 8, the subject matter of any of Examples 1 to 4 can optionally include a source region and a drain region formed in the semiconductive substrate, at least one interlayer dielectric disposed over the semiconductive substrate, a source contact extending through the at least one interlayer dielectric and electrically contacting the source region, a drain contact extending through the at least one interlayer dielectric and electrically contacting the source region, wherein the transistor gate is positioned between the source contact and the drain contact, and wherein the reinforced airgap spacer is positioned between the transistor gate and at least one of the source contact and the drain contact.
The following examples pertain to further embodiments, wherein Example 9 is a method of fabricating an integrated circuit transistor comprising: forming a semiconductive substrate; forming a transistor gate on the semiconductive substrate; and forming at least one reinforced airgap spacer, wherein the at least one reinforced airgap spacer abuts the transistor gate, and wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
In Example 10, the subject matter of Example 9 can optionally include forming the airgap spacer comprising depositing a spacer material layer comprising a dielectric material over the transistor gate and exposed portions of the semiconductive substrate; etching the dielectric spacer material layer to form at least one intermediate gate spacer; altering the etch rate of the dielectric material in a center area of the intermediate gate spacer and the dielectric material in an exterior area of the intermediate gate spacer; and etching the at least one intermediate gate spacer to remove the dielectric material in the center area.
In Example 11 , the subject matter of Example 10 can optionally include altering the etch rate of the dielectric material in a center area of the intermediate gate spacer and the dielectric material in an exterior area of the intermediate gate spacer comprising depositing a supporting dielectric material layer over the transistor gate, the at least one intermediate gate spacer, and exposed portions of the semiconductive substrate.
In Example 12, the subject matter of Example 1 1 can optionally include etching the supporting dielectric material layer to form at least one supporting dielectric structure on the semiconductive substrate, wherein the at least one supporting dielectric structure abuts the at least one reinforced airgap spacer.
In Example 13, the subject matter of Example 1 1 can optionally include forming the supporting dielectric material layer comprises forming the supporting dielectric material layer structure from a ceramic material.
In Example 14, the subject matter of Example 13 can optionally include forming the supporting dielectric material layer structure from a ceramic material comprises forming the supporting dielectric material layer structure from aluminum nitride.
In Example 15, the subject matter of Example 14 can optionally include forming the supporting dielectric material layer structure from aluminum nitride comprises depositing aluminum nitride at temperature of about 1000 degrees Celsius.
In Example 16, the subject matter of Example 12 can optionally include forming at least one additional airgap spacer abutting the at least one reinforced airgap spacer. In Example 17, the subject matter of Example 18 can optionally include forming the at least one additional airgap spacer comprising removing the at least one supporting dielectric structure.
In Example 18, the subject matter of Example 9 can optionally include the at least one reinforced airgap spacer including a gas disposed within the void.
In Example 19, the subject matter of Example 16 can optionally include the gas comprising air.
In Example 20, the subject matter of any of Examples 9 to 19 can optionally include forming a source region and a drain region formed in the semiconductive substrate, forming at least one interlay er dielectric over the semiconductive substrate, forming a source contact extending through the at least one interlayer dielectric and electrically contacting the source region, forming a drain contact extending through the at least one interlayer dielectric and electrically contacting the source region, wherein the transistor gate is positioned between the source contact and the drain contact, and wherein the reinforced airgap spacer is positioned between the transistor gate and at least one of the source contact and the drain contact
The following examples pertain to further embodiments, wherein Example 21 is an electronic system, comprising: a board; and an integrated circuit component attached to the board, wherein the integrated circuit component includes a microelectronic transistor comprising a semiconductive substrate; a transistor gate formed on the semiconductive substrate; and at least one reinforced airgap spacer formed on the semiconductive substrate and abutting the transistor gate, wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
In Example 22, the subject matter of Example 21 can optionally include at least one supporting dielectric structure formed on the semiconductive substrate, wherein the at least one supporting dielectric structure abuts the at least one reinforced airgap spacer.
In Example 23, the subject matter of Example 22 can optionally include the at least one supporting dielectric structure comprising a ceramic material.
In Example 24, the subject matter of Example 23 can optionally include the ceramic material comprising aluminum nitride.
In Example 25, the subject matter of any of Examples 21 to 24 can optionally include the reinforced airgap spacer having a gas disposed within the void. In Example 26, the subject matter of Example 25 can optionally include the gas comprising air.
In Example 27, the subject matter of any of Examples 21 to 24 can optionally include at least one additional airgap spacer abutting the at least one reinforced airgap spacer.
In Example 28, the subject matter of any of Examples 21 to 24 can optionally include a source region and a drain region formed in the semiconductive substrate, at least one interlayer dielectric disposed over the semiconductive substrate, a source contact extending through the at least one interlayer dielectric and electrically contacting the source region, a drain contact extending through the at least one interlayer dielectric and electrically contacting the source region, wherein the transistor gate is positioned between the source contact and the drain contact, and wherein the reinforced airgap spacer is positioned between the transistor gate and at least one of the source contact and the drain contact.
Having thus described in detail embodiments of the present description, it is understood that the present description defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims

CLAIMS What is claimed is:
1. An integrated circuit transistor, comprising:
a semiconductive substrate;
a transistor gate formed on the semiconductive substrate; and
at least one reinforced airgap spacer formed on the semiconductive substrate and abutting the transistor gate, wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
2. The integrated circuit transistor of claim 1 , further comprising at least one supporting dielectric structure formed on the semiconductive substrate, wherein the at least one supporting dielectric structure abuts the at least one reinforced airgap spacer.
3. The integrated circuit transistor of claim 2, wherein the at least one supporting dielectric structure comprises a ceramic material.
4. The integrated circuit transistor of claim 3, wherein the ceramic material comprises aluminum nitride.
5. The integrated circuit transistor of any of claims 1 to 4, wherein the at least one reinforced airgap spacer includes a gas disposed within the void.
6. The integrated circuit transistor of any of claims 1 to 4, further comprising at least one additional airgap spacer abutting the at least one reinforced airgap spacer.
7. The integrated circuit transistor of any of claims 1 to 4, further comprising
a source region and a drain region formed in the semiconductive substrate;
at least one interlay er dielectric disposed over the semiconductive substrate;
a source contact extending through the at least one interlayer dielectric and electrically contacting the source region; a drain contact extending through the at least one interlay er dielectric and electrically contacting the source region;
wherein the transistor gate is positioned between the source contact and the drain contact; and
wherein the at least one reinforced airgap spacer is positioned between the transistor gate and at least one of the source contact and the drain contact.
8. A method of fabricating an integrated circuit transistor comprising:
forming a semiconductive substrate;
forming a transistor gate on the semiconductive substrate; and
forming at least one reinforced airgap spacer on the semiconductive substrate, wherein the at least one reinforced airgap spacer abuts the transistor gate, and wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
9. The method of claim 8, wherein forming the at least reinforced airgap spacer comprises:
depositing a spacer material layer comprising a dielectric material over the transistor gate and exposed portions of the semiconductive substrate;
etching the dielectric spacer material layer to form at least one intermediate gate spacer;
altering the etch rate of the dielectric material in a center area of the intermediate gate spacer and the dielectric material in an exterior area of the intermediate gate spacer; and etching the at least one intermediate gate spacer to remove the dielectric material in the center area.
10. The method of claim 9, wherein altering the etch rate of the dielectric material in a center area of the intermediate gate spacer and the dielectric material in an exterior area of the intermediate gate spacer comprises depositing a supporting dielectric material layer over the transistor gate, the at least one intermediate gate spacer, and exposed portions of the semiconductive substrate.
11. The method of claim 10, further comprising etching the supporting dielectric material layer to form at least one supporting dielectric structure on the semiconductive substrate, wherein the at least one supporting dielectric structure abuts the at least one reinforced airgap spacer.
12. The method of claim 10, wherein forming the supporting dielectric material layer comprises forming the supporting dielectric material layer structure from a ceramic material.
13. The method of claim 12, wherein forming the supporting dielectric material layer structure from a ceramic material comprises forming the supporting dielectric material layer structure from aluminum nitride.
14. The method of claim 13, wherein forming the supporting dielectric material layer structure from aluminum nitride comprises depositing aluminum nitride at temperature of about 1000 degrees Celsius.
15. The method of claim 11 , further comprising forming at least one additional airgap spacer abutting the at least one reinforced airgap spacer.
16. The method of claim 15, wherein forming the at least one additional airgap spacer comprises removing the at least one supporting dielectric structure.
17. The method of claim 8, wherein the at least one reinforced airgap spacer includes a gas disposed within the void.
18. The method of any of claims 8 to 17, further comprising
forming a source region and a drain region formed in the semiconductive substrate; forming at least one interlayer dielectric over the semiconductive substrate;
forming a source contact extending through the at least one interlayer dielectric and electrically contacting the source region;
forming a drain contact extending through the at least one interlayer dielectric and electrically contacting the source region; wherein the transistor gate is positioned between the source contact and the drain contact; and
wherein the at least one reinforced airgap spacer is positioned between the transistor gate and at least one of the source contact and the drain contact.
19. An electronic system, comprising:
a board; and
an integrated circuit component attached to the board, wherein the integrated circuit component includes an integrated circuit transistor comprising:
a semiconductive substrate;
a transistor gate formed on the semiconductive substrate; and at least one reinforced airgap spacer formed on the semiconductive substrate and abutting the transistor gate, wherein the at least one reinforced airgap spacer comprises a dielectric material shell substantially surrounding a void.
20. The electronic system of claim 19, further comprising at least one supporting dielectric structure formed on the semiconductive substrate, wherein the at least one supporting dielectric structure abuts the at least one reinforced airgap spacer.
21. The electronic system of claim 20, wherein the at least one supporting dielectric structure comprises a ceramic material.
22. The electronic system of claim 21, wherein the ceramic material comprises aluminum nitride.
23. The electronic system of any of claims 19 to 22, wherein the at least one reinforced airgap spacer includes a gas disposed within the void.
24. The electronic system of any of claims 19 to 22, further comprising at least one additional airgap spacer abutting the at least one reinforced airgap spacer.
25. The electronic system of any of claims 19 to 22, further comprising a source region and a drain region formed in the semiconductive substrate;
at least one interlay er dielectric disposed over the semiconductive substrate;
a source contact extending through the at least one interlayer dielectric and electrically contacting the source region;
a drain contact extending through the at least one interlayer dielectric and electrically contacting the source region;
wherein the transistor gate is positioned between the source contact and the drain contact; and
wherein the at least one reinforced airgap spacer is positioned between the transistor gate and at least one of the source contact and the drain contact.
PCT/US2017/040306 2017-06-30 2017-06-30 Transistor with reinforced airgap spacers WO2019005109A1 (en)

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