TWI569314B - A vertical vacuum sealed carbon nanotube transistor and method for preparing the same - Google Patents

Description

Vertical vacuum sealed nano carbon tube field effect transistor and manufacturing method thereof

The present invention relates to the field of semiconductor manufacturing, and in particular to a vertical vacuum sealed carbon nanotube field effect transistor and a method of fabricating the same.

Conventional gold oxide half field effect transistors (MOSFETs) fabricate components on a single crystal germanium substrate material. Under the urging of Moore’s Law, the channel length of conventional transistor MOSFETs is shrinking and component size is shrinking. This miniaturization increases transistor density, increases wafer integration, and other fixed factors and switching speeds, while reducing power consumption and increasing wafer performance. In the future, as the technical requirements continue to increase, and the germanium wafers can no longer be made smaller, it is necessary to find new wafer fabrication materials, and carbon nanotube transistors are a good choice. By replacing the channel material of a conventional bulk MOSFET structure with a single carbon nanotube or carbon nanotube array, the limitations can be overcome to some extent and the component dimensions can be further reduced.

In an ideal fully enclosed gate structure, the size of the Carbon Nano Tube Field Effect Transistor (CNTFET) with auto-aligned gate has been reduced to 20 nm. The uniformity of the gate surrounding the carbon nanotube channel has been consolidated, and such a system Cheng also did not cause damage to the carbon nanotubes.

Nanotube wafers can greatly enhance the capabilities of high-performance computers, enable faster data analysis, increase power and battery life for mobile devices and the Internet of Things, and allow cloud data centers to provide more efficient and cost-effective services.

However, as the size of the component continues to decrease, the increased contact resistance becomes the biggest obstacle to the performance improvement of the nanotube field effect transistor. For any advanced transistor technology, the increased contact resistance due to the reduced size of the transistor becomes a major performance bottleneck. Up to now, the reduction in component size has led to an increase in contact resistance, resulting in a decrease in component performance corresponding to contact resistance, which is based on the challenges faced by tantalum and carbon nanotube field effect transistor technology.

It is an object of the present invention to provide a vertical vacuum sealed carbon nanotube field effect transistor and a method of manufacturing the same that overcome the above problems.

In order to achieve the above object, the present invention provides a method for fabricating a vertical vacuum sealed carbon nanotube field effect transistor, comprising the steps of: providing a semiconductor substrate on which a first single damascene structure is formed, A single damascene structure includes a dielectric layer formed in the dielectric layer, the dielectric layer exposing the conductive layer; forming nanoparticle on a surface of the conductive layer; Forming a plurality of spaced carbon nanotubes on the conductive layer; forming a gate dielectric layer on the surface of the dielectric layer, the conductive layer and the carbon nanotube; Forming a metal gate on a surface of the gate dielectric layer, a portion of the portion of the carbon nanotube protruding from a surface of the metal gate; forming a second single mosaic structure on the surface of the metal gate The top of the carbon nanotube is connected to the conductive layer in the second single inlay structure.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the forming step of the first single damascene structure comprises: sequentially forming a tantalum nitride layer and a dielectric layer on the semiconductor substrate An electrical layer; etching the dielectric layer to form a recess, etching stops at the tantalum nitride layer; filling the conductive layer in the recess.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, a barrier layer is formed in the groove before forming the conductive layer in the groove. A conductive layer is formed on the surface of the barrier layer.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the barrier layer is TaN or Ta.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the forming step of the second single mosaic structure includes: sequentially forming a tantalum nitride layer on the surface of the metal gate and a dielectric layer, a surface of the tantalum nitride layer being flush with a top of the protruding carbon nanotube; etching the dielectric layer to form a recess, and etching stops at the tantalum nitride layer, the recess The top of the carbon nanotube is exposed; a conductive layer is filled in the recess, the conductive layer being connected to the top of the carbon nanotube.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, a barrier layer is formed in the groove before forming the conductive layer in the groove. The barrier layer is formed under vacuum, and the conductive layer is formed on the surface of the barrier layer.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the barrier layer is TaN, Mo or Ta.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the dielectric layer is cerium oxide.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the step of forming nano particles and a carbon nanotube on the conductive layer includes: forming a surface of the dielectric layer a mask layer exposing the conductive layer; forming a nanoparticle on the surface of the conductive layer with the mask layer as a mask; forming a nano surface on the surface of the conductive layer after forming the nanoparticle Carbon tube; using a stripping technique to remove the mask layer.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the material of the mask layer is BARC or amorphous carbon.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the nano particle material is Co or Mo.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the gate dielectric layer is made of HfO ₂ or Al ₂ O ₃ .

Further, in the vertical vacuum sealing of the carbon nanotube field effect transistor In the manufacturing method, the step of forming the metal gate includes: forming a metal gate on a surface of the gate dielectric layer, the metal gate covering a top portion of the carbon nanotube; using a chemical mechanical polishing process The metal gate is ground to expose the top of the carbon nanotube; the metal gate is etched back by an etch back process to extend a portion of the carbon nanotube from the top of the metal gate surface.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, after forming the second single mosaic structure, high temperature annealing treatment is performed in an H ₂ or N ₂ environment to make the nano The conductive layers at both ends of the carbon nanotube have arcuate projections.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the high temperature annealing temperature ranges from 600 degrees Celsius to 1200 degrees Celsius.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the time range of the high temperature annealing is 10 seconds to 120 minutes.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the degree of vacuum in the carbon nanotube is 0.01 Torr to 50 Torr.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the length of the carbon nanotube is in the range of 2 nm to 100 nm, and the size of the carbon nanotube cross section is 1 nm. ~5nm.

Further, in the manufacturing method of the vertical vacuum sealed carbon nanotube field effect transistor, the material of the conductive layer includes Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, diamond or a combination of the above materials.

In the present invention, a vertical vacuum sealed carbon nanotube field effect transistor is also proposed, which is prepared by the method for manufacturing a vertical vacuum sealed carbon nanotube field effect transistor as described above, including: a semiconductor substrate, a first single damascene structure, a carbon nanotube, a gate dielectric layer, a metal gate, and a second single damascene structure, wherein the first single damascene structure is formed on the semiconductor substrate, the first The surface of the conductive layer in the single mosaic structure is formed with nano particles, and the two ends of the carbon nanotube are respectively connected to the conductive layer in the first single mosaic structure and the conductive layer in the second single mosaic structure. The gate dielectric layer is formed on a surface of the carbon nanotube and the dielectric layer, the metal gate is formed on a surface of the gate dielectric layer, and is located in the first single mosaic structure and the second Between single mosaic structures.

Compared with the prior art, the beneficial effects of the present invention are mainly embodied in: forming nano particles as a catalyst on the surface of the conductive layer, and then forming a carbon nanotube, the gate dielectric layer is in contact with the source drain, and the carbon nanotube is sealed. In a vacuum environment, the subsequent operation of the carbon nanotube field effect transistor can reduce the component operating voltage, improve component life and other properties.

10‧‧‧Semiconductor substrate

20‧‧‧矽 nitride layer

30‧‧‧Dielectric layer

40‧‧‧Block

41‧‧‧ Conductive layer

42‧‧‧Nano granules

50‧‧‧ mask layer

60‧‧‧Nano Carbon Tube

70‧‧‧gate dielectric layer

80‧‧‧Metal gate

1 is a flow chart showing a method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to an embodiment of the present invention; and FIGS. 2 to 14 are vertical vacuum sealing carbon nanotube fields according to an embodiment of the present invention; FIG. 15 is a cross-sectional view along the channel direction according to an embodiment of the present invention; and FIG. 16 is a cross-sectional view perpendicular to the channel direction according to an embodiment of the present invention; Vertical vacuum sealed carbon nanotube field effect electric power according to an embodiment of the invention Schematic diagram of the energy band of the crystal.

The vertical vacuum sealed carbon nanotube field effect transistor of the present invention and its manufacturing method will be described in more detail below with reference to the schematic drawings, wherein a preferred embodiment of the present invention is shown, and it should be understood that those skilled in the art can modify the description herein. The present invention, while still achieving the advantageous effects of the present invention. Therefore, the following description is to be understood as a broad understanding of the invention.

In the interest of clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not described in detail, as they may obscure the invention in unnecessary detail. It should be understood that in the development of any actual embodiment, a large number of implementation details must be made to achieve a particular goal of the developer, such as changing from one embodiment to another in accordance with the limitations of the system or related business. Additionally, such development work should be considered complex and time consuming, but is only routine work for those skilled in the art.

The invention is more specifically described in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the description and appended claims. It should be noted that the drawings are in a very simplified form and both use non-precise proportions, and are only for convenience and clarity to assist the purpose of the embodiments of the present invention.

Referring to FIG. 1 , in the embodiment, a method for manufacturing a vertical vacuum sealed carbon nanotube field effect transistor is provided, comprising the steps of: S100: providing a semiconductor substrate, and forming a first single on the semiconductor substrate a mosaic structure, the first single damascene structure comprising a dielectric layer and a conductive layer, the conductive layer being formed in the dielectric layer, the dielectric layer exposing the conductive layer; S200: forming nano particles on the surface of the conductive layer; S300: forming a plurality of spaced carbon nanotubes on the conductive layer; S400: forming on the surface of the dielectric layer, the conductive layer, and the carbon nanotube a gate dielectric layer; S500: forming a metal gate on a surface of the gate dielectric layer, a portion of the portion of the carbon nanotube protruding from a surface of the metal gate; S600: forming a surface on the surface of the metal gate The second single mosaic structure has a top portion of the carbon nanotube connected to the conductive layer in the second single mosaic structure.

Specifically, referring to FIG. 2 to FIG. 3, the step of forming the first single damascene structure comprises: sequentially forming a tantalum nitride layer 20 and a dielectric layer 30 on the semiconductor substrate 10; etching the dielectric layer The electrical layer 30 is formed with a recess, and etching stops at the tantalum nitride layer 20; the conductive layer 41 is filled in the recess.

Before forming the conductive layer 41 in the recess, a barrier layer 40 is formed in the recess, and the conductive layer 41 is formed on the surface of the barrier layer 40, wherein the material of the conductive layer 41 The material of the dielectric layer 30 may be cerium oxide. To prevent copper from diffusing into the dielectric layer 30, it is generally required to form a conductive barrier layer 40 between the two, wherein the barrier layer 40 may be Ta or TaN. Or a combination of both.

Referring to FIGS. 4-7, the step of forming the nanoparticle 42 and the carbon nanotube 60 on the conductive layer 41 includes: forming a mask layer 50 on the surface of the dielectric layer 30 to expose the a conductive layer 41; forming a nano particle on the surface of the conductive layer 41 with the mask layer 50 as a mask After forming the nanoparticle 42, a carbon nanotube 60 is formed on the surface of the conductive layer 41; the mask layer 50 is removed by lift-off.

The mask layer 50 is made of a material such as a bottom anti-reflective layer (BARC) or an amorphous carbon. The nano-particles 42 are made of Co or Mo, and the formed nano-particles 42 can act as a catalyst to reduce contact. resistance. The carbon nanotubes 60 have a length ranging from 2 nm to 100 nm, and the carbon nanotubes 60 have a cross-sectional dimension ranging from 1 nm to 5 nm.

Referring to FIG. 8, a gate dielectric layer 70 is formed on the surface of the dielectric layer 30, the conductive layer 41, and the carbon nanotube 60. The gate dielectric layer 70 is made of HfO ₂ or Al ₂ O ₃ .

Referring to FIGS. 9-11, the step of forming the metal gate 80 includes forming a metal gate 80 on the surface of the gate dielectric layer 70, and the metal gate 80 covers the carbon nanotube 60. The top, as shown in Fig. 9; the metal gate 80 is ground by a chemical mechanical polishing process to expose the top of the carbon nanotube 60, as shown in Fig. 10; using an etch back process The metal gate 80 is etched back so that a portion of the top of the carbon nanotube 60 protrudes beyond the surface of the metal gate 80 as shown in FIG.

Next, referring to FIG. 12 to FIG. 14, the forming process of the second single damascene structure includes: sequentially forming a tantalum nitride layer 20 and a dielectric layer 30 on the surface of the metal gate 80, the nitriding The surface of the germanium layer 20 is flush with the top of the protruding carbon nanotubes 60; the dielectric layer 30 is etched to form a recess, and etching stops at the tantalum nitride layer 20, the groove exposes the top of the carbon nanotube 60, and the top of the carbon nanotube 60 may be cleaned; the conductive layer 41 is filled in the groove, and the conductive layer 41 is The tops of the carbon nanotubes 60 are connected.

Similarly, since the material of the conductive layer 41 is copper and the material of the dielectric layer 30 is ceria, in order to prevent the diffusion of copper, it is necessary to form a barrier layer 40 between the conductive layer 41 and the dielectric layer 30, wherein the barrier layer The material of 40 may be TaN or Ta, doped with Co or Mo, and the inclusion of Co or Mo in the barrier layer 40 of the second single damascene structure can also reduce the contact resistance. The barrier layer 40 is formed under vacuum conditions such that the degree of vacuum in the carbon nanotubes 60 ranges from 0.01 Torr to 50 Torr.

The material of the conductive layer 41 includes Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, diamond or a combination of the above materials. Wherein, the first single mosaic structure and the second single mosaic structure can be used as the source drain of the component.

After forming the second single damascene structure, high temperature annealing treatment is performed in an H ₂ or N ₂ environment, so that the conductive layer 41 or the barrier layer 41 at both ends of the carbon nanotubes 60 has curved protrusions, and the high temperature annealing The temperature range is from 600 to 1200 degrees Celsius, and the annealing time range is from 10 seconds to 120 minutes. Please refer to Figure 15. After high temperature annealing, the conductive layer 41 or the barrier layer 41 can be on both ends of the carbon nanotube 60. An arcuate projection is formed so that the opening speed of the passage can be increased. The cross-sectional structure inside the carbon nanotube 60 can be referred to FIG.

In another aspect of the embodiment, a vertical vacuum sealed carbon nanotube field effect transistor is also proposed, which is prepared by the method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor as described above, including :Semiconductor substrate, first single inlay structure, carbon nanotube, thyristor An electric layer, a metal gate, and a second single inlay structure, wherein the first single damascene structure is formed on the semiconductor substrate, and a surface of the conductive layer in the first single inlay structure is formed with nano particles The two ends of the carbon nanotube are respectively connected to the conductive layer in the first single mosaic structure and the conductive layer in the second single mosaic structure, and the gate dielectric layer is formed on the carbon nanotube And a surface of the dielectric layer, the metal gate is formed on a surface of the gate dielectric layer and located between the first single mosaic structure and the second single mosaic structure.

In addition, the energy band diagram of the formed vertical vacuum-sealed carbon nanotube field-effect transistor can be referred to FIG. 17, and it can be seen that the formed vertical vacuum-sealed carbon nanotube field-effect transistor has an electron or a hole from the opening. The energy migration distance from the source to the drain is shorter, which makes the performance of the entire component better.

In summary, in the vertical vacuum sealed carbon nanotube field effect transistor and the manufacturing method thereof provided by the embodiments of the present invention, nano particles are formed on the surface of the conductive layer as a catalyst, and then a carbon nanotube, a gate dielectric layer is formed. In contact with the source bungee, the carbon nanotubes are sealed in a vacuum environment, which can reduce the operating voltage of the components and improve the service life and other properties of the components after the subsequent formation of the carbon nanotube field effect transistors.

The above is only a preferred embodiment of the present invention and does not impose any limitation on the present invention. Any changes in the technical solutions and technical contents disclosed in the present invention may be made by those skilled in the art without departing from the technical scope of the present invention. The content is still within the scope of protection of the present invention.

S100~S600‧‧‧Steps

Claims (20)

A method for manufacturing a vertical vacuum sealed carbon nanotube field effect transistor, comprising the steps of: providing a semiconductor substrate on which a first single damascene structure is formed, the first single damascene structure comprising a dielectric layer And a conductive layer formed in the dielectric layer, the dielectric layer exposing the conductive layer; forming nano particles on a surface of the conductive layer; forming a plurality of spaces on the conductive layer Arranging carbon nanotubes; forming a gate dielectric layer on the surface of the dielectric layer, the conductive layer and the carbon nanotube; forming a metal gate on the surface of the gate dielectric layer, a portion of the top of the carbon nanotube Extending the surface of the metal gate; forming a second single mosaic structure on the surface of the metal gate, the top of the carbon nanotube being connected to the conductive layer in the second single mosaic structure. The method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to claim 1, wherein the forming of the first single damascene structure comprises: sequentially forming a tantalum nitride layer and a dielectric layer on the semiconductor substrate An electrical layer; etching the dielectric layer to form a recess, etching stops at the tantalum nitride layer; filling the conductive layer in the recess. A method of fabricating a vertical vacuum sealed carbon nanotube field effect transistor according to claim 2, wherein a barrier layer is formed in said recess before said conductive layer is formed in said recess. A conductive layer is formed on the surface of the barrier layer. A method of fabricating a vertical vacuum sealed carbon nanotube field effect transistor according to claim 3, wherein said barrier layer is TaN or Ta. The method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to claim 1, wherein the forming of the second single damascene structure comprises: sequentially forming a tantalum nitride layer on the surface of the metal gate and a dielectric layer, a surface of the tantalum nitride layer being flush with a top of the protruding carbon nanotube; etching the dielectric layer to form a recess, and etching stops at the tantalum nitride layer, the recess The top of the carbon nanotube is exposed; a conductive layer is filled in the recess, the conductive layer being connected to the top of the carbon nanotube. A method of fabricating a vertical vacuum sealed carbon nanotube field effect transistor according to claim 5, wherein a barrier layer is formed in said recess before said conductive layer is formed in said recess. The barrier layer is formed under vacuum, and the conductive layer is formed on the surface of the barrier layer. A method of fabricating a vertical vacuum sealed carbon nanotube field effect transistor according to claim 6, wherein said barrier layer is TaN or Ta, doped with Co or Mo. A method of fabricating a vertical vacuum sealed carbon nanotube field effect transistor according to claim 1, wherein said dielectric layer is hafnium oxide. A method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to claim 1, wherein the step of forming nanoparticle and carbon nanotubes on said conductive layer comprises: forming a surface of said dielectric layer a mask layer exposing the conductive layer; forming a nanoparticle on the surface of the conductive layer with the mask layer as a mask; forming a nano surface on the surface of the conductive layer after forming the nanoparticle Carbon tube; using a stripping technique to remove the mask layer. The method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to claim 9, wherein the mask layer is made of a bottom anti-reflective layer (BARC) or amorphous carbon. The method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to claim 9, wherein the nanoparticle material is Co or Mo. The method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to claim 1, wherein the gate dielectric layer is made of HfO ₂ or Al ₂ O ₃ . A method of fabricating a vertical vacuum sealed carbon nanotube field effect transistor according to claim 1, wherein said step of forming said metal gate comprises: forming a metal gate on a surface of said gate dielectric layer, said metal gate The top of the carbon nanotube is covered by a pole; the metal gate is ground by a chemical mechanical polishing process to expose the top of the carbon nanotube; and the metal gate is etched back by an etch back process a portion of the carbon nanotube is projected over the surface of the metal gate. The method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to claim 1, wherein after forming the second single mosaic structure, high temperature annealing treatment is performed in an H ₂ or N ₂ environment to cause the nano The conductive layers at both ends of the carbon nanotube have arcuate projections. A method of fabricating a vertical vacuum sealed carbon nanotube field effect transistor according to claim 14, wherein said high temperature annealing has a temperature in the range of 600 to 1200 degrees Celsius. A method of fabricating a vertical vacuum sealed carbon nanotube field effect transistor according to claim 14, wherein said high temperature annealing has a time range of from 10 seconds to 120 minutes. A method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to claim 1, wherein the degree of vacuum in said carbon nanotube ranges from 0.01 Torr to 50 Torr. The manufacturer of the vertical vacuum sealed carbon nanotube field effect transistor according to claim 1 The method wherein the carbon nanotubes have a length ranging from 2 nm to 100 nm, and the carbon nanotube cross-section has a size ranging from 1 nm to 5 nm. The method of manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to claim 1, wherein the material of the conductive layer comprises Zr, V, Nb, Ta, Cr, Mo, W, Fe, Co, Pd, Cu, Al, Ga, In, Ti, TiN, TaN, diamond or a combination of the above materials. A vertical vacuum sealed carbon nanotube field effect transistor prepared by the method for manufacturing a vertical vacuum sealed carbon nanotube field effect transistor according to any one of claims 1 to 19, comprising: a semiconductor substrate, a single damascene structure, a carbon nanotube, a gate dielectric layer, a metal gate, and a second single damascene structure, wherein the first single damascene structure is formed on the semiconductor substrate, the first single The surface of the conductive layer in the mosaic structure is formed with nano particles, and the two ends of the carbon nanotube are respectively connected to the conductive layer in the first single mosaic structure and the conductive layer in the second single mosaic structure. a gate dielectric layer is formed on a surface of the carbon nanotube and the dielectric layer, the metal gate is formed on a surface of the gate dielectric layer, and is located in the first single mosaic structure and the second single Between mosaic structures.