JP2022529994A5 - - Google Patents
Info
- Publication number
- JP2022529994A5 JP2022529994A5 JP2021562345A JP2021562345A JP2022529994A5 JP 2022529994 A5 JP2022529994 A5 JP 2022529994A5 JP 2021562345 A JP2021562345 A JP 2021562345A JP 2021562345 A JP2021562345 A JP 2021562345A JP 2022529994 A5 JP2022529994 A5 JP 2022529994A5
- Authority
- JP
- Japan
- Prior art keywords
- die
- memory
- memory controller
- package substrate
- chip structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2025066561A JP2025114585A (ja) | 2019-04-23 | 2025-04-15 | プログラマブル集積回路を有するダイ上に積層されたメモリダイを含むマルチチップ構造 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/392,170 US11282824B2 (en) | 2019-04-23 | 2019-04-23 | Multi-chip structure including a memory die stacked on die having programmable integrated circuit |
| US16/392,170 | 2019-04-23 | ||
| PCT/US2020/026032 WO2020219242A1 (en) | 2019-04-23 | 2020-03-31 | Multi-chip structure including a memory die stacked on a die having a programmable integrated circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025066561A Division JP2025114585A (ja) | 2019-04-23 | 2025-04-15 | プログラマブル集積回路を有するダイ上に積層されたメモリダイを含むマルチチップ構造 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2022529994A JP2022529994A (ja) | 2022-06-27 |
| JP2022529994A5 true JP2022529994A5 (https=) | 2023-12-05 |
| JP7668745B2 JP7668745B2 (ja) | 2025-04-25 |
Family
ID=70476331
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021562345A Active JP7668745B2 (ja) | 2019-04-23 | 2020-03-31 | プログラマブル集積回路を有するダイ上に積層されたメモリダイを含むマルチチップ構造 |
| JP2025066561A Pending JP2025114585A (ja) | 2019-04-23 | 2025-04-15 | プログラマブル集積回路を有するダイ上に積層されたメモリダイを含むマルチチップ構造 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2025066561A Pending JP2025114585A (ja) | 2019-04-23 | 2025-04-15 | プログラマブル集積回路を有するダイ上に積層されたメモリダイを含むマルチチップ構造 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US11282824B2 (https=) |
| EP (1) | EP3925001A1 (https=) |
| JP (2) | JP7668745B2 (https=) |
| KR (2) | KR20250077466A (https=) |
| CN (2) | CN121751653A (https=) |
| TW (1) | TWI836054B (https=) |
| WO (1) | WO2020219242A1 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020145231A (ja) | 2019-03-04 | 2020-09-10 | キオクシア株式会社 | 半導体装置およびその製造方法 |
| US11282824B2 (en) * | 2019-04-23 | 2022-03-22 | Xilinx, Inc. | Multi-chip structure including a memory die stacked on die having programmable integrated circuit |
| CN113517271A (zh) * | 2021-05-20 | 2021-10-19 | 浙江毫微米科技有限公司 | 一种带有堆叠存储器的集成电路结构 |
| US11715731B2 (en) * | 2021-08-29 | 2023-08-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
| CN113722268B (zh) * | 2021-09-02 | 2024-07-19 | 西安紫光国芯半导体有限公司 | 一种存算一体的堆叠芯片 |
| CN113793632B (zh) * | 2021-09-02 | 2024-05-28 | 西安紫光国芯半导体有限公司 | 非易失可编程芯片 |
| CN113745197B (zh) * | 2021-09-03 | 2024-08-30 | 西安紫光国芯半导体股份有限公司 | 一种三维异质集成的可编程阵列芯片结构和电子器件 |
| US12489061B2 (en) | 2022-06-27 | 2025-12-02 | Texas Instruments Incorporated | Semiconductor device with multiple dies |
| US12505068B2 (en) | 2023-06-28 | 2025-12-23 | Xilinx, Inc. | Tiled compute and programmable logic array |
| CN117222234B (zh) * | 2023-11-07 | 2024-02-23 | 北京奎芯集成电路设计有限公司 | 一种基于UCIe接口的半导体器件 |
| CN118409997B (zh) * | 2024-04-29 | 2025-04-15 | 清华大学 | 多芯片集成封装高密度算力模组的装置 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8356138B1 (en) | 2007-08-20 | 2013-01-15 | Xilinx, Inc. | Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP) |
| US7899983B2 (en) * | 2007-08-31 | 2011-03-01 | International Business Machines Corporation | Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module |
| US7701251B1 (en) | 2008-03-06 | 2010-04-20 | Xilinx, Inc. | Methods and apparatus for implementing a stacked memory programmable integrated circuit system in package |
| TW201225249A (en) * | 2010-12-08 | 2012-06-16 | Ind Tech Res Inst | Stacked structure and stacked method for three-dimensional integrated circuit |
| KR20120119960A (ko) | 2011-04-21 | 2012-11-01 | 삼성전자주식회사 | 마이크로 범프 연결성을 테스트할 수 있는 반도체 장치 |
| CN104205234B (zh) * | 2012-03-30 | 2017-07-11 | 英特尔公司 | 用于存储器电路测试引擎的通用数据加扰器 |
| DE112012006161B4 (de) * | 2012-03-30 | 2020-09-17 | Intel Corporation | Integrierter Selbsttest für Stapelspeicherarchitektur |
| US8737108B2 (en) * | 2012-09-25 | 2014-05-27 | Intel Corporation | 3D memory configurable for performance and power |
| US9065722B2 (en) | 2012-12-23 | 2015-06-23 | Advanced Micro Devices, Inc. | Die-stacked device with partitioned multi-hop network |
| US9135185B2 (en) | 2012-12-23 | 2015-09-15 | Advanced Micro Devices, Inc. | Die-stacked memory device providing data translation |
| US9286948B2 (en) | 2013-07-15 | 2016-03-15 | Advanced Micro Devices, Inc. | Query operations for stacked-die memory device |
| KR20230151553A (ko) * | 2016-06-27 | 2023-11-01 | 애플 인크. | 조합된 높은 밀도, 낮은 대역폭 및 낮은 밀도, 높은 대역폭 메모리들을 갖는 메모리 시스템 |
| JP2018074065A (ja) * | 2016-11-01 | 2018-05-10 | 富士通株式会社 | 半導体装置 |
| KR102624199B1 (ko) | 2016-11-17 | 2024-01-15 | 에스케이하이닉스 주식회사 | 관통 실리콘 비아 기술을 적용한 반도체 패키지 |
| KR102650497B1 (ko) * | 2017-02-28 | 2024-03-25 | 에스케이하이닉스 주식회사 | 적층형 반도체 장치 |
| US20190067034A1 (en) * | 2017-08-24 | 2019-02-28 | Micron Technology, Inc. | Hybrid additive structure stackable memory die using wire bond |
| US11282824B2 (en) * | 2019-04-23 | 2022-03-22 | Xilinx, Inc. | Multi-chip structure including a memory die stacked on die having programmable integrated circuit |
-
2019
- 2019-04-23 US US16/392,170 patent/US11282824B2/en active Active
-
2020
- 2020-03-31 JP JP2021562345A patent/JP7668745B2/ja active Active
- 2020-03-31 CN CN202511852682.3A patent/CN121751653A/zh active Pending
- 2020-03-31 KR KR1020257007052A patent/KR20250077466A/ko active Pending
- 2020-03-31 CN CN202080030688.1A patent/CN113767471B/zh active Active
- 2020-03-31 KR KR1020217037840A patent/KR102778388B1/ko active Active
- 2020-03-31 EP EP20722717.4A patent/EP3925001A1/en active Pending
- 2020-03-31 WO PCT/US2020/026032 patent/WO2020219242A1/en not_active Ceased
- 2020-04-09 TW TW109111972A patent/TWI836054B/zh active
-
2022
- 2022-03-11 US US17/693,256 patent/US11670630B2/en active Active
-
2025
- 2025-04-15 JP JP2025066561A patent/JP2025114585A/ja active Pending
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