CN111357105A - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN111357105A
CN111357105A CN201780096913.XA CN201780096913A CN111357105A CN 111357105 A CN111357105 A CN 111357105A CN 201780096913 A CN201780096913 A CN 201780096913A CN 111357105 A CN111357105 A CN 111357105A
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ram
logic chip
semiconductor module
interposer
unit
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越川康二
奥津文武
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Ultramemory Inc
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Ultramemory Inc
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Abstract

本发明提供一种能够提升MPU和DRAM间的带宽(bandwidth)的半导体模块。本发明涉及的半导体模块(1)具有：逻辑芯片(20)；RAM部(40)，其为层叠型RAM模块；隔片(60)，其沿所述RAM部(40)的层叠方向重叠配置；中介层(10)，其电连接于各所述逻辑芯片(20)和所述RAM部(40)；连接部(50)，其将所述逻辑芯片(20)与所述RAM部(40)之间能够通信地连接，所述逻辑芯片(20)与所述隔片(60)在与所述RAM部(40)的层叠方向交叉的方向上邻接配置，所述RAM部(40)载置于所述中介层(10)，并且一端部与所述逻辑芯片(20)的一端部在层叠方向重叠配置，所述连接部(50)将所述RAM部(40)的一端部与所述逻辑芯片(20)的一端部连接。

Description

半导体模块
技术领域
本发明涉及一种半导体模块。
背景技术
以往，作为存储装置已知有DRAM(Dynamic Random Access Memory：动态随机访问存储器)等易失性存储器(RAM)。DRAM追求能够应对运算装置(以下称逻辑芯片)的高性能化以及数据量的增大的大容量化。因此，逐渐追求基于存储器(存储器单元阵列、存储器芯片)的微细化和单元的平面增设而得到的大容量化。另一方面，由于微细化带来的对于噪声的脆弱性、晶片面积的增加等，此类大容量化已达极限。
因此，近年来开发了层叠多个平面的存储器来进行三维化(3D化)而实现大容量化的技术。另外，提出了通过重叠配置逻辑芯片和RAM来减小逻辑芯片和RAM的设置面积的半导体模块(例如参考专利文献1和2)。
现有技术文献
专利文献
专利文献1：日本特表2014-512691号公报；
专利文献2：日本特开2010-232659号公报。
发明内容
发明要解决的课题
然而，由于逻辑芯片的高性能化和数据量的增大，在要求大容量化的同时还要求逻辑芯片和RAM间的通信速度的提升。因此，期望能够提供一种能够提升逻辑芯片和RAM间的带宽(bandwidth)的半导体模块。
本发明的目的在于提供一种能够提升逻辑芯片和RAM间的带宽(bandwidth)的半导体模块。
用于解决课题的方案
本发明涉及一种半导体模块，其具有：逻辑芯片；RAM部，其为层叠型RAM模块；隔片，其沿所述RAM部的层叠方向重叠配置；中介层，其电连接于各所述逻辑芯片和所述RAM部；连接部，其将所述逻辑芯片与所述RAM部之间能够通信地连接，所述逻辑芯片和所述隔片在与所述RAM部的层叠方向交叉的方向邻接配置，所述RAM部载置于所述中介层，一端部与所述逻辑芯片的一端部在层叠方向重叠配置，所述连接部将所述RAM部的一端部和所述逻辑芯片的一端部能够通信地连接。
另外，优选的是，所述RAM部及所述隔片夹着所述逻辑芯片成对设置，所述连接部针对每个RAM部设置。
另外，优选的是，所述隔片与所述逻辑芯片的厚度大致相等。
另外，优选的是，所述隔片比所述逻辑芯片的厚度厚。
另外，优选的是，所述隔片的端部中与所述逻辑芯片相向侧的相反侧的端部配置为，在与所述RAM部的层叠方向交叉的方向上比所述RAM部突出。
另外，优选的是，半导体模块还具有多个导电柱，所述导电柱将所述中介层和所述逻辑芯片之间以能够通信的方式连接，各所述导电柱比所述RAM部在层叠方向的厚度长。
另外，优选的是，所述逻辑芯片相对于一个所述中介层设置有多个，一对所述RAM部和一对所述隔片针对每个所述逻辑芯片设置。
发明效果
根据本发明，能够提供一种能够提升逻辑芯片与RAM间的带宽(bandwidth)的半导体模块。
附图说明
图1是表示本发明的一个实施方式涉及的半导体模块，是去除了隔片及支承体的概要俯视图。
图2是一个实施方式的半导体模块的概要侧视图。
图3是表示在制作一个实施方式的半导体模块时的MPU的概要侧视图。
图4是表示在制作一个实施方式的半导体模块时在MPU设置了连接部的概要侧视图。
图5是表示在制作一个实施方式的半导体模块时在MPU设置了导电柱的概要侧视图。
图6是表示在制作一个实施方式的半导体模块时的RAM部的概要侧视图。
图7是表示在制作一个实施方式的半导体模块时在RAM部设置了连接部的概要侧视图。
图8是表示在制作一个实施方式的半导体模块时在RAM部设置了微凸点的概要侧视图。
图9是表示在制作一个实施方式的半导体模块时的支承体的概要侧视图。
图10是表示在制作一个实施方式的半导体模块时在支承体设置了MPU的概要侧视图。
图11是表示在制作一个实施方式的半导体模块时在支承体设置了隔片的概要侧视图。
图12是表示在制作一个实施方式的半导体模块时在支承体设置了RAM部的概要侧视图。
图13是表示本发明的变形例涉及的半导体模块，是去除了隔片及支承体的概要俯视图。
具体实施方式
以下，参照图1～图13对本发明涉及的半导体模块的一个实施方式进行说明。
一个实施方式涉及的半导体模块例如是在中介层上配置了运算装置(以下称逻辑芯片)和层叠型RAM的SIP(system in a package：系统级封装)。半导体模块配置在其它的中介层或封装基板上，并使用微凸点、焊锡凸点等电连接。半导体模块是从其他的中介层获得电源并能够在与其他中介层之间发送接收数据的装置。另外，在以下的一个实施方式中，将MPU作为逻辑芯片的一例进行说明。
如图1和2所示，本实施方式涉及的半导体模块1包括：中介层10、MPU20、导电柱30、RAM部40、连接部50、隔片60和支承体70。
如图1和2所示，中介层10是俯视观察时呈矩形的板状体，在其内部形成有电路。中介层10电连接于后述的各MPU20及RAM部40。中介层10配置在其他中介层(未图示)或封装基板(未图示)上，其一个面(下表面)例如使用微凸点(未图示)、焊锡凸点(未图示)等电连接于其他中介层或封装基板。另外，以下，将中介层10的厚度方向作为层叠方向C进行说明。另外，在层叠方向C中，将载置MPU20和RAM部40的面侧作为上方进行说明。另外，在层叠方向C中，将与上方相反侧的方向作为下方进行说明。
MPU20是俯视观察时的呈矩形的板状体。如图1和图2所示，MPU20在下表面侧配置有作为电源端子、通信端子以及接地端子发挥功能的电路面(未图示)。MPU20的电路面配置成与中介层10的上表面相向。
导电柱30配置有多个。导电柱30以能够通信的方式将中介层10与MPU20之间连接。具体地，导电柱30的一端连接到中介层10，另一端侧连接到MPU20的电路面。每个导电柱30比后述的RAM部40在层叠方向C的厚度长。
RAM部40由分别为俯视观察时呈矩形的层叠型RAM模块构成。如图2所示，RAM部40载置于中介层10的上表面。RAM部40的一端部隔着后述的连接部50与MPU20的一端部在层叠方向C上重叠配置。具体地，RAM部40的一端部以介于MPU20的一端部与中介层10之间的方式配置。RAM部40的与中介层10的上表面相向的下表面使用微凸点M与中介层10电连接。RAM部40并不特别限定，可以在与层叠方向C交叉的方向上以夹着MPU20的方式成对设置。具体地，在本实施方式中，没有特别限定，可以配置四个RAM部40，可以在MPU20的一边和其相反侧的一边沿着每个边设置每两个地RAM部40。由此，将夹着MPU20的一对RAM部40之间的距离设置为比MPU20的一边与其相反侧的一边的长度短。
RAM部40是层叠存储器电路(未图示)而形成的。具体地，RAM部40是在上表面具有存储器电路的俯视观察时呈矩形的板状体的晶片(未图示)在层叠方向C上层叠而形成的。晶片是内部形成有电路的Si基板，层叠的晶片各自与相邻的晶片电连接。将层叠的晶片之间连接的电源端子以及接地端子例如由无凸点TSV形成，信号线由TCI(ThruChipInterface：贯穿芯片接口)形成。此外，“电连接”不限于直接连接，还包括如TCI那样间接地(例如使用磁场)连接。
连接部50是连接MPU20和RAM部40的通信接口。连接部50例如由TCI、Cu焊盘等构成。连接部50将RAM部40与MPU20之间连接以此能够通信。连接部50连接于RAM部40的面中与被中介层10载置的面(下表面)相反的面(上表面)的一端部。另外，连接部50连接在MPU20的相向于中介层10的面(下表面)的一端部。具体地，连接部50连接于RAM部40的上表面中相向于MPU20的部分以及MPU20的下表面中相向于RAM部40的部分。连接部50配置在各个RAM部40。例如，在本实施方式中，连接部50配置在各四个RAM部40和MPU20之间。此外，连接部50不限于物理连接MPU20和RAM部40的连接部，也包括使用无线(例如TCI)将两者连接以此能够通信的连接部。
隔片60载置在RAM部40的上表面。隔片60例如构成为俯视观察时呈矩形。隔片60例如由硅构成。隔片60的厚度构成为与MPU20的厚度大致相等，或者构成为比MPU20的厚度厚。更优选地，采用从中介层10的上表面到隔片60的上表面的高度与从中介层10的上表面到通过导电柱30连接到中介层10的MPU20的上表面的高度大致相同或相同的结构。隔片60相对于MPU20在与RAM部40的层叠方向C交叉的方向邻接配置。在本实施方式中，隔片60以夹住MPU20的侧面的方式与MPU20邻接配置。隔片60的端部中与MPU20相向侧的相反侧的端部配置为，在与RAM部40的层叠方向C交叉的方向上比RAM部40突出。具体地，隔片60的端部中与MPU20相向侧的相反侧的端部配置为，在与朝向MPU20侧的相反侧的方向上比RAM部40突出。
此外，当在MPU20和RAM部40之间不需要间隙时，隔片60的厚度构成为与MPU20的厚度大致相等。在该情况下，连接部50被安装在RAM部40和MPU20。例如，在MPU20和RAM部40通过TCI、Cu混合键合(hybrid bonding)技术而连接的情况下，连接部50作为配置在RAM部40和MPU20的内部的线圈(未图示)、在RAM部40的上部表面和MPU20的下部表面露出的Cu焊盘(未图示)，安装在RAM部40和MPU20。
支承体70例如由硅构成。支承体70例如形成为主视观察时大致矩形。支承体70载置于隔片60的上表面和MPU20的上表面。支承体70以能够在主视观察时覆盖隔片60及MPU20的大小形成。
接着，对半导体模块1的工作进行说明。
首先，从中介层10向MPU20供给电源。另外，从中介层10向RAM部40供给电源。另外，MPU20与中介层10接地。RAM部40与中介层10接地。此外，可以经由连接部50从MPU20向RAM部40供给电源和接地。
当在RAM部40存储数据时，首先，数据从中介层10经由导电柱30发送到MPU20。MPU20将基于发送的数据进行运算的运算结果作为存储信号发送到RAM部40。即，从MPU20发送的存储信号通过MPU20的电路面和连接部50被发送至RAM部40。RAM部40基于存储信号中包含的地址来存储存储信号中包含的数据。
另一方面，当从RAM部40读取数据时，首先，读取信号从中介层10经由导电柱30发送到MPU20。即，从MPU20发送的读取信号通过MPU20的电路面和连接部50被发送至RAM部40。
RAM部40基于读取信号中包含的地址从该地址来读取数据。RAM部40将读取的数据通过连接部50发送给MPU20。
接着，对半导体模块1的构造进行说明。
首先，如图3所示，准备具有电路面的MPU20。然后，如图4所示，在MPU20的电路面的两端形成连接部50的一部分。然后，如图5所示，在MPU20的电路面的中央部形成多个导电柱30。
另外，如图6所示，准备层叠了多个晶片的RAM部40。然后，如图7所示，在RAM部40的上表面(在图7中是纸面上方)的一端部形成连接部50的一部分。然后，如图8所示，在RAM部40的下表面形成多个微凸点M。
然后，如图9所示，准备支承体70。支承体70在层叠方向C反转上下方向而配置(在以下的图9～图12中，上下方向相反地表示)。然后，如图10所示，在支承体70的一个面(下表面)上载置MPU20。具体地，MPU20以使上表面相向于支承体70的一侧的面(下表面)的状态载置在支承体70。然后，如图11所示，隔片60以邻接于MPU20的状态载置在支承体70的一个面(下表面)上。然后，如图12所示，RAM部40载置于隔片60上。由此，RAM部40的上表面相向于隔片60的下表面。此时，以构成在RAM部40的连接部50的一部分与构成在MPU20的连接部50的一部分重叠的方式配置。然后，通过将中介层10的上表面连接到与MPU20连接的导电柱30以及在RAM部40构成的凸点，实现了如图2所示的半导体模块1的结构。
根据以上那样的一个实施方式的半导体模块1，起到以下的效果。
(1)一种半导体模块，具有：逻辑芯片；RAM部40，其为层叠型RAM模块；隔片60，其沿RAM部40的层叠方向重叠配置；中介层10，其连接于各逻辑芯片和RAM部40；连接部50，其将逻辑芯片与RAM部40能够通信地连接，逻辑芯片和隔片60在与RAM部40的层叠方向交叉的方向上邻接配置，RAM部40载置于中介层10，并且一端部与逻辑芯片的一端部在层叠方向重叠配置，连接部50将RAM部40的一端部与逻辑芯片的一端部能够通信地连接。由此，由于MPU20和一对RAM部40的各自能够通过连接部50直接连接，所以能够缩短MPU20和一对RAM部40各自之间的信号线(连接部50的长度)。由此，能够增大MPU20与一对RAM部40之间的带宽。
(2)在半导体模块中，RAM部40及隔片60夹着逻辑芯片成对设置，连接部50针对每个RAM部40设置。由此，由于各RAM部40通过连接部50单独地连接到MPU20，所以能够相对于MPU20容易地连接多个RAM部40，能够容易地增加RAM部40的容量。
(3)隔片60的厚度与逻辑芯片的厚度大致相等，或者比逻辑芯片的厚度厚。由此，能够将MPU20的下表面连接到RAM部40的上表面，同时稳定地配置支承体70。
(4)隔片60的端部中与逻辑芯片相向侧的相反侧的端部配置为，在与RAM部40的层叠方向交叉的方向上比RAM部40突出。由此，相比隔片60的侧面与RAM部40的侧面成为同一面的情况，隔片60的露出面积增加，因此能够提高在RAM部40中发生的热的散热性。另外，由于能够将用于层叠的粘接剂(paste)等涂敷到RAM部40的整个面，能够使结构稳定化，并能够防止RAM部40的倾斜。
(5)半导体模块还具有多个导电柱30，所述导电柱30将中介层10和逻辑芯片之间能够通信地连接，每个导电柱30比RAM部40在层叠方向的厚度长。由此，能够相对于中介层10的上表面以离开导电柱30的长度配置MPU20的位置。因此，能够使RAM40的上表面的一部分相向于MPU20的下表面的一部分，能够缩短信号线(连接部50的长度)。
以上，虽然对本发明的半导体模块的优选的一实施方式进行了说明，但本发明不限于所述的实施方式，并可适当变更。
例如，如图13所示，也可以MPU20相对于一个中介层10设置有多个，一对RAM部40及一对隔片60针对每个MPU20设置。由此，由于能够将RAM部40连接到多个MPU20的各个，能够缩短MPU20与RAM部40之间的信号线(连接部50的长度)，即使存在多个MPU20，也能够增大带宽。
此外，在所述实施方式中，说明了RAM部40和隔片60以夹着MPU20的方式成对设置，但不限于此。例如，RAM部40和隔片60可以仅配置在MPU20的一边。此外，RAM部40和隔片60可以被配置在MPU20的三边，也可以以围绕MPU20的方式在四边配置。
此外，运算装置不限于MPU20，可以广泛地应用于所有逻辑芯片，存储器不限于DRAM，可以广泛地应用于包括非易失性RAM(例如MRAM、ReRAM、FeRAM等)的所有RAM(RandomAccess Memory：随机访问存储器)。
附图标记说明
1：半导体模块
10：中介层
20：MPU
30：导电柱
40：RAM部
50：连接部
60：隔片
70：支承体

Claims (7)

1.一种半导体模块，具有：
逻辑芯片；
RAM部，其为层叠型RAM模块；
隔片，其沿所述RAM部的层叠方向重叠配置；
中介层，其电连接于各所述逻辑芯片和所述RAM部；以及，
连接部，其将所述逻辑芯片与所述RAM部之间能够通信地连接，
所述逻辑芯片和所述隔片在与所述RAM部的层叠方向交叉的方向邻接配置，
所述RAM部载置于所述中介层，并且一端部与所述逻辑芯片的一端部在层叠方向重叠配置，
所述连接部将所述RAM部的一端部和所述逻辑芯片的一端部能够通信地连接。
2.根据权利要求1所述的半导体模块，其中，
所述RAM部及所述隔片夹着所述逻辑芯片成对设置，
所述连接部针对每个所述RAM部设置。
3.根据权利要求1或2所述的半导体模块，其中，
所述隔片的厚度与所述逻辑芯片的厚度大致相等。
4.根据权利要求1或2所述的半导体模块，其中，
所述隔片的厚度比所述逻辑芯片的厚度厚。
5.根据权利要求1至4中任一项所述的半导体模块，其中，
所述隔片的端部中与所述逻辑芯片相向侧的相反侧的端部配置为，在与所述RAM部的层叠方向交叉的方向上比所述RAM部突出。
6.根据权利要求1至5中任一项所述的半导体模块，其中，
还具有多个导电柱，所述导电柱将所述中介层与所述逻辑芯片之间能够通信地连接，各所述导电柱比所述RAM部的层叠方向的厚度长。
7.根据权利要求1至6中任一项所述的半导体模块，其中，
所述逻辑芯片相对于一个所述中介层设置多个，
一对所述RAM部和一对所述隔片针对每个所述逻辑芯片设置。
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