WO2019102528A1 - 半導体モジュール - Google Patents

半導体モジュール Download PDF

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Publication number
WO2019102528A1
WO2019102528A1 PCT/JP2017/041887 JP2017041887W WO2019102528A1 WO 2019102528 A1 WO2019102528 A1 WO 2019102528A1 JP 2017041887 W JP2017041887 W JP 2017041887W WO 2019102528 A1 WO2019102528 A1 WO 2019102528A1
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Prior art keywords
ram
logic chip
mpu
spacer
semiconductor module
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PCT/JP2017/041887
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English (en)
French (fr)
Inventor
康二 越川
文武 奥津
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ウルトラメモリ株式会社
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Application filed by ウルトラメモリ株式会社 filed Critical ウルトラメモリ株式会社
Priority to US16/765,099 priority Critical patent/US20200357746A1/en
Priority to CN201780096913.XA priority patent/CN111357105A/zh
Priority to PCT/JP2017/041887 priority patent/WO2019102528A1/ja
Priority to JP2019555105A priority patent/JP7033332B2/ja
Publication of WO2019102528A1 publication Critical patent/WO2019102528A1/ja

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Definitions

  • the present invention relates to a semiconductor module.
  • RAM volatile memory
  • DRAM dynamic random access memory
  • logic chips arithmetic units
  • miniaturization of memory memory cell array, memory chip
  • increase in capacity by planar expansion of cells have been achieved.
  • this type of increase in capacity has reached the limit due to the vulnerability to noise due to miniaturization and the increase in die area.
  • An object of the present invention is to provide a semiconductor module capable of improving the bandwidth between a logic chip and a RAM.
  • the present invention is electrically connected to each of the logic chip and the RAM unit, a logic chip, a RAM unit which is a stacked RAM module, a spacer which is disposed to overlap along the stacking direction of the RAM unit, and the logic chip and the RAM unit.
  • An interposer and a connection portion communicably connecting the logic chip and the RAM unit, wherein the logic chip and the spacer are arranged adjacent to each other in a direction intersecting the stacking direction of the RAM unit,
  • the RAM portion is mounted on the interposer, and one end portion thereof is disposed to overlap with one end portion of the logic chip in the stacking direction, and the connection portion is one end portion of the RAM portion and one end portion of the logic chip.
  • the present invention relates to a semiconductor module communicably connected.
  • the RAM portion and the spacer are provided in a pair on both sides of the logic chip, and the connection portion is provided for each RAM portion.
  • the spacer is approximately equal to the thickness of the logic chip.
  • the spacer is thicker than the thickness of the logic chip.
  • the end portion on the side opposite to the side facing the logic chip may be disposed to protrude from the RAM portion in the direction intersecting the stacking direction of the RAM portion. preferable.
  • the semiconductor module further includes a plurality of pillars communicably connecting the interposer and the logic chip, each of the plurality of pillars being longer than a thickness of the RAM portion in the stacking direction. .
  • a plurality of logic chips are provided for one interposer, and a pair of the RAM units and a pair of the spacers are provided for each of the logic chips.
  • FIG. 2 is a schematic plan view showing a semiconductor module according to an embodiment of the present invention excluding a spacer and a support. It is a schematic side view of the semiconductor module of one embodiment. It is a schematic side view showing MPU at the time of producing a semiconductor module of one embodiment. It is the schematic side view which provided the connection part in MPU at the time of producing the semiconductor module of one Embodiment. It is the schematic side view which provided the pillar in MPU at the time of producing the semiconductor module of one Embodiment. It is a schematic side view which shows the RAM part at the time of producing the semiconductor module of one Embodiment. It is the schematic side view which provided the connection part in the RAM part at the time of producing the semiconductor module of one Embodiment.
  • the semiconductor module according to one embodiment is, for example, an SIP (system in a package) in which an arithmetic device (hereinafter, referred to as a logic chip) and a stacked RAM are disposed on an interposer.
  • the semiconductor module is disposed on another interposer or package substrate and electrically connected using micro bumps, solder bumps, and the like.
  • the semiconductor module is a device that obtains power from other interposers and can transmit and receive data to and from other interposers.
  • MPU will be described as an example of a logic chip.
  • the semiconductor module 1 is, as shown in FIGS. 1 and 2, an interposer 10, an MPU 20, a pillar 30, a RAM unit 40, a connection unit 50, a spacer 60, and a support 70. Equipped with
  • the interposer 10 is a plate-like body having a rectangular shape in a plan view, and an electric circuit is formed inside.
  • the interposer 10 is electrically connected to each of the MPU 20 and the RAM unit 40 described later.
  • the interposer 10 is disposed on another interposer (not shown) or a package substrate (not shown), and one surface (bottom surface) is, for example, a micro bump (not shown) or a solder bump (not shown) Are electrically connected to other interposers or package substrates.
  • the thickness direction of the interposer 10 is described as the stacking direction C. Further, in the stacking direction C, the side on which the MPU 20 and the RAM unit 40 are mounted is described as being upward. Further, in the stacking direction C, the direction opposite to the upper side is described as the lower side.
  • the MPU 20 is a plate-like body having a rectangular shape in plan view. As shown in FIGS. 1 and 2, the MPU 20 has a circuit surface (not shown) functioning as a power supply terminal, a communication terminal, and a ground terminal on the lower surface side. The circuit surface of the MPU 20 is disposed opposite to the top surface of the interposer 10.
  • a plurality of pillars 30 are arranged.
  • the pillars 30 communicably connect the interposer 10 and the MPU 20. Specifically, one end of the pillar 30 is connected to the interposer 10, and the other end is connected to the circuit surface of the MPU 20.
  • the pillars 30 are each longer than the thickness in the stacking direction C of the RAM portion 40 described later.
  • the RAM units 40 are each formed of a stacked RAM module having a rectangular shape in plan view.
  • the RAM unit 40 is mounted on the top surface of the interposer 10 as shown in FIG.
  • One end of the RAM unit 40 is disposed to overlap with one end of the MPU 20 in the stacking direction C via a connection unit 50 described later.
  • one end of the RAM unit 40 is disposed so as to be interposed between one end of the MPU 20 and the interposer 10.
  • the lower surface of the RAM portion 40 facing the upper surface of the interposer 10 is electrically connected to the interposer 10 using the microbumps M.
  • the RAM units 40 are not particularly limited, but may be provided in a pair so as to sandwich the MPU 20 in the direction intersecting the stacking direction C.
  • RAM units 40 may be disposed, and two each may be provided along one side of MPU 20 and the other side thereof.
  • the distance between the pair of RAM units 40 sandwiching the MPU 20 is shorter than the length of one side of the MPU 20 and the other side thereof.
  • the RAM unit 40 is formed by stacking memory circuits (not shown). Specifically, the RAM unit 40 is formed by stacking a plate-shaped die (not shown) having a rectangular shape in plan view and having a memory circuit on the upper surface in the stacking direction C.
  • the die is a Si substrate in which a circuit is formed, and each of the stacked dies is electrically connected to an adjacent die.
  • the power supply terminal and the ground terminal connecting between the dies to be stacked are formed by, for example, a bumpless TSV, and the signal line is formed by a TCI (ThruChip Interface).
  • TCI ThiChip Interface
  • the connection unit 50 is a communication interface that connects the MPU 20 and the RAM unit 40.
  • the connection unit 50 is configured of, for example, a TCI, a Cu pad, or the like.
  • the connection unit 50 communicably connects the MPU 20 and the RAM unit 40.
  • the connection unit 50 is connected to one end of the surface (upper surface) opposite to the surface (lower surface) to be mounted on the interposer 10 among the surfaces of the RAM unit 40.
  • the connection unit 50 is connected to one end of the surface (lower surface) of the MPU 20 facing the interposer 10.
  • the connection portion 50 is connected to a portion of the upper surface of the RAM portion 40 facing the MPU 20 and a portion of the lower surface of the MPU 20 facing the RAM portion 40.
  • connection unit 50 is disposed in each of the RAM units 40.
  • the connection unit 50 is disposed between each of the four RAM units 40 and the MPU 20.
  • the connection unit 50 is not limited to the physical connection between the MPU 20 and the RAM unit 40, and also includes a connection that allows both to be communicably connected using wireless (for example, TCI).
  • the spacer 60 is mounted on the upper surface of the RAM unit 40.
  • the spacer 60 is configured, for example, in a rectangular shape in plan view.
  • the spacer 60 is made of, for example, silicon.
  • the thickness of the spacer 60 is configured to be approximately equal to the thickness of the MPU 20 or greater than the thickness of the MPU 20. More preferably, the height from the top surface of interposer 10 to the top surface of spacer 60 is substantially the same as or the same height as the height from the top surface of interposer 10 to the top surface of MPU 20 connected to interposer 10 by pillar 30. Configured The spacer 60 is disposed adjacent to the MPU 20 in the direction intersecting the stacking direction C of the RAM unit 40.
  • the spacer 60 is disposed adjacent to the MPU 20 so as to sandwich the side surface of the MPU 20.
  • the end portion on the opposite side to the side facing the MPU 20 is disposed to protrude from the RAM portion 40 in the direction intersecting the stacking direction C of the RAM portion 40.
  • the end portion on the side opposite to the side facing the MPU 20 is disposed to project more than the RAM unit 40 in the direction opposite to the side facing the MPU 20.
  • the thickness of the spacer 60 is configured to be substantially equal to the thickness of the MPU 20.
  • the connection unit 50 is mounted on the RAM unit 40 and the MPU 20.
  • the connection unit 50 is a coil (not shown) disposed inside the RAM unit 40 and the MPU 20 or the upper surface of the RAM unit 40
  • the Cu pad (not shown) exposed on the lower surface of the MPU 20 are mounted on the RAM unit 40 and the MPU 20.
  • the support 70 is made of, for example, silicon.
  • the support 70 is formed, for example, in a substantially rectangular shape in a front view.
  • the support 70 is placed on the upper surface of the spacer 60 and the upper surface of the MPU 20.
  • the support 70 is formed in a size that can cover the spacer 60 and the MPU 20 in a front view.
  • power is supplied from the interposer 10 to the MPU 20. Further, power is supplied from the interposer 10 to the RAM unit 40. Also, the MPU 20 is connected to the interposer 10 at ground. The RAM unit 40 is grounded to the interposer 10. Note that power and ground may be supplied from the MPU 20 to the RAM unit 40 via the connection unit 50.
  • the data is sent from the interposer 10 to the MPU 20 via the pillars 30.
  • the MPU 20 sends the calculation result calculated based on the sent data to the RAM unit 40 as a store signal. That is, the store signal sent from the MPU 20 is sent to the RAM unit 40 through the circuit surface of the MPU 20 and the connection unit 50.
  • the RAM unit 40 stores data included in the store signal based on the address included in the store signal.
  • a load signal is sent from the interposer 10 to the MPU 20 via the pillar 30. That is, the load signal sent from the MPU 20 is sent to the RAM unit 40 through the circuit surface of the MPU 20 and the connection unit 50.
  • the RAM unit 40 loads data from the corresponding address based on the address included in the load signal.
  • the RAM unit 40 sends the loaded data to the MPU 20 via the connection unit 50.
  • an MPU 20 having a circuit surface is prepared.
  • a part of the connection portion 50 is formed at both ends of the circuit surface of the MPU 20.
  • a plurality of pillars 30 are formed at the center of the circuit surface of the MPU 20.
  • a RAM unit 40 in which a plurality of dies are stacked is prepared.
  • a part of the connection portion 50 is formed at one end of the upper surface (the upper side in the drawing of FIG. 7) of the RAM portion 40.
  • a plurality of micro bumps M are formed on the lower surface of the RAM unit 40.
  • a support 70 is prepared.
  • the support 70 is disposed upside down in the stacking direction C (the up and down directions are shown to be reversed in FIGS. 9 to 12 below).
  • the MPU 20 is placed on one surface (lower surface) of the support 70.
  • the MPU 20 is mounted on the support 70 with the upper surface facing the one surface (lower surface) of the support 70.
  • the spacer 60 is placed on one surface (lower surface) of the support 70 adjacent to the MPU 20.
  • the RAM unit 40 is placed on the spacer 60. Thereby, the upper surface of the RAM unit 40 faces the lower surface of the spacer 60.
  • connection portion 50 formed in the RAM portion 40 and a portion of the connection portion 50 formed in the MPU 20 are disposed so as to overlap each other. Then, the upper surface of the interposer 10 is connected to the pillars 30 connected to the MPU 20 and the bumps formed in the RAM unit 40, whereby the structure of the semiconductor module 1 as shown in FIG. 2 is realized.
  • the semiconductor module is electrically connected to each of the logic chip, the RAM unit 40 which is a stacked RAM module, the spacer 60 disposed in an overlapping manner along the stacking direction of the RAM unit 40, and the logic chip and the RAM unit 40.
  • a connection unit 50 communicably connecting the logic chip and the RAM unit 40.
  • the logic chip and the spacer 60 extend in the direction intersecting the stacking direction of the RAM unit 40. Adjacent to each other, the RAM unit 40 is placed on the interposer 10, and one end thereof is arranged to overlap with one end of the logic chip in the stacking direction, and the connection unit 50 is one end of the RAM 40 and one end of the logic chip Communicably connect the units.
  • connection unit 50 since the MPU 20 and each of the pair of RAM units 40 can be directly connected by the connection unit 50, the signal line (the length of the connection unit 50) between the MPU 20 and each of the pair of RAM units 40 Can be shortened. Thus, the bandwidth between the MPU 20 and the pair of RAM units 40 can be increased.
  • the RAM unit 40 and the spacer 60 are provided in a pair on both sides of the logic chip, and the connection unit 50 is provided for each RAM unit 40.
  • the thickness of the spacer 60 is approximately equal to or thicker than the thickness of the logic chip.
  • the support 70 can be stably disposed while the lower surface of the MPU 20 is connected to the upper surface of the RAM unit 40.
  • the end portion on the opposite side to the side facing the logic chip is disposed to protrude from the RAM portion 40 in the direction intersecting the stacking direction of the RAM portion 40.
  • the exposed area of the spacer 60 is increased as compared with the case where the side surface of the spacer 60 is flush with the side surface of the RAM portion 40, so that the heat dissipation of heat generated in the RAM portion 40 can be enhanced.
  • a paste or the like for laminating can be applied to the entire surface of the RAM section 40, the structure can be stabilized and the inclination of the RAM section 40 can be prevented.
  • the semiconductor module further includes a plurality of pillars 30 communicably connecting the interposer 10 and the logic chip, each of the plurality of pillars 30 being longer than the thickness in the stacking direction of the RAM unit 40.
  • the position of the MPU 20 can be spaced apart from the top surface of the interposer 10 by the length of the pillar 30. Therefore, a part of the upper surface of the RAM unit 40 can be made to face a part of the lower surface of the MPU 20, and the signal line (the length of the connecting portion 50) can be shortened.
  • a plurality of MPUs 20 may be provided for one interposer 10, and a pair of RAM units 40 and a pair of spacers 60 may be provided for each MPU 20.
  • the RAM unit 40 can be connected to each of the plurality of MPUs 20, the signal line (the length of the connecting unit 50) between the MPU 20 and the RAM unit 40 can be shortened. The bandwidth can be broadened, even in the presence of
  • the RAM unit 40 and the spacer 60 are described as being provided in a pair so as to sandwich the MPU 20 in the above embodiment, the present invention is not limited thereto.
  • the RAM unit 40 and the spacer 60 may be disposed on only one side of the MPU 20.
  • the RAM unit 40 and the spacer 60 may be disposed on three sides of the MPU 20, or may be disposed on four sides so as to surround the MPU 20.
  • the arithmetic device is not limited to the MPU 20, and may be widely applied to logic chips in general, and the memory is not limited to the DRAM, and RAM (Random Access Memory) including nonvolatile RAM (for example, MRAM, ReRAM, FeRAM, etc.) ) It may be applied to the whole.
  • RAM Random Access Memory
  • nonvolatile RAM for example, MRAM, ReRAM, FeRAM, etc.

Abstract

ＭＰＵ及びＤＲＡＭ間のバンド幅（帯域幅）を向上することが可能な半導体モジュールを提供すること。　半導体モジュール１は、論理チップ２０と、積層型ＲＡＭモジュールであるＲＡＭ部４０と、前記ＲＡＭ部４０の積層方向に沿って重ねて配置されるスペーサ６０と、前記論理チップ２０及び前記ＲＡＭ部４０のそれぞれに電気的に接続されるインタポーザ１０と、前記論理チップ２０と前記ＲＡＭ部４０の間とを通信可能に接続する接続部５０と、を備え、前記論理チップ２０及び前記スペーサ６０は、前記ＲＡＭ部４０の積層方向に交差する方向に隣接配置され、前記ＲＡＭ部４０は前記インタポーザ１０に載置されるとともに、一端部が前記論理チップ２０の一端部と積層方向で重なって配置され、前記接続部５０は、前記ＲＡＭ部４０の一端部及び前記論理チップ２０の一端部を接続する。

Description

半導体モジュール
　本発明は、半導体モジュールに関する。
　従来より、記憶装置としてＤＲＡＭ（Dynamic Random Access Memory）等の揮発性メモリ（ＲＡＭ）が知られている。ＤＲＡＭには、演算装置（以下、論理チップという）の高性能化やデータ量の増大に耐えうる大容量化が求められている。そこで、メモリ（メモリセルアレイ、メモリチップ）の微細化及びセルの平面的な増設による大容量化が図られてきた。一方で、微細化によるノイズへの惰弱性や、ダイ面積の増加等により、この種の大容量化は限界に達してきている。
　そこで、昨今では、平面的なメモリを複数積層して３次元化（３Ｄ化）して大容量化を実現する技術が開発されている。また、論理チップ及びＲＡＭを重ねて配置することで、論理チップ及びＲＡＭの設置面積を低減する半導体モジュールが提案されている（例えば、特許文献１及び２参照）。
特表２０１４－５１２６９１号公報 特開２０１０－２３２６５９号公報
　ところで、論理チップの高性能化やデータ量の増大により、論理チップ及びＲＡＭ間の通信速度の向上も大容量化とともに求められている。そこで、論理チップ及びＲＡＭ間のバンド幅（帯域幅）を向上することが可能な半導体モジュールを提供することができれば好ましい。
　本発明は、論理チップ及びＲＡＭ間のバンド幅（帯域幅）を向上することが可能な半導体モジュールを提供することを目的とする。
　本発明は、論理チップと、積層型ＲＡＭモジュールであるＲＡＭ部と、前記ＲＡＭ部の積層方向に沿って重ねて配置されるスペーサと、前記論理チップ及び前記ＲＡＭ部のそれぞれに電気的に接続されるインタポーザと、前記論理チップと前記ＲＡＭ部の間とを通信可能に接続する接続部と、を備え、前記論理チップ及び前記スペーサは、前記ＲＡＭ部の積層方向に交差する方向に隣接配置され、前記ＲＡＭ部は前記インタポーザに載置されるとともに、一端部が前記論理チップの一端部と積層方向で重なって配置され、前記接続部は、前記ＲＡＭ部の一端部及び前記論理チップの一端部を通信可能に接続する半導体モジュールに関する。
　また、前記ＲＡＭ部及び前記スペーサは、前記論理チップを挟んで一対に設けられ、前記接続部は、ＲＡＭ部ごとに設けられることが好ましい。
　また、前記スペーサは、前記論理チップの厚さとほぼ等しいことが好ましい。
　また、前記スペーサは、前記論理チップの厚さよりも厚いことが好ましい。
　また、前記スペーサの端部のうち、前記論理チップに対向する側とは逆側の端部は、前記ＲＡＭ部の積層方向に交差する方向において、前記ＲＡＭ部よりも突出して配置されることが好ましい。
　また、半導体モジュールは、前記インタポーザと前記論理チップとの間を通信可能に接続する複数のピラーであって、それぞれが前記ＲＡＭ部の積層方向の厚さよりも長い複数のピラーを更に備えることが好ましい。
　また、前記論理チップは、１つの前記インタポーザに対して複数設けられ、一対の前記ＲＡＭ部及び一対の前記スペーサは、前記論理チップごとに設けられることが好ましい。
　本発明によれば、論理チップ及びＲＡＭ間のバンド幅（帯域幅）を向上することが可能な半導体モジュールを提供することができる。
本発明の一実施形態に係る半導体モジュールを示し、スペーサ及び支持体を除いた概略平面図である。 一実施形態の半導体モジュールの概略側面図である。 一実施形態の半導体モジュールを作製する際のＭＰＵを示す概略側面図である。 一実施形態の半導体モジュールを作製する際のＭＰＵに接続部を設けた概略側面図である。 一実施形態の半導体モジュールを作製する際のＭＰＵにピラーを設けた概略側面図である。 一実施形態の半導体モジュールを作製する際のＲＡＭ部を示す概略側面図である。 一実施形態の半導体モジュールを作製する際のＲＡＭ部に接続部を設けた概略側面図である。 一実施形態の半導体モジュールを作製する際のＲＡＭ部にマイクロバンプを設けた概略側面図である。 一実施形態の半導体モジュールを作製する際の支持体を示す概略側面図である。 一実施形態の半導体モジュールを作製する際の支持体にＭＰＵを設けた概略側面図である。 一実施形態の半導体モジュールを作製する際の支持体にスペーサを設けた概略側面図である。 一実施形態の半導体モジュールを作製する際の支持体にＲＡＭ部を設けた概略側面図である。 本発明の変形例に係る半導体モジュールを示し、スペーサ及び支持体を除いた概略平面図である。
　以下、本発明に係る半導体モジュールの一実施形態について図１～図１３を参照して説明する。
　一実施形態に係る半導体モジュールは、例えば、演算装置（以下、論理チップという）と、積層型ＲＡＭとをインタポーザ上に配置したＳＩＰ（system in a package）である。半導体モジュールは、他のインタポーザ又はパッケージ基板上に配置され、マイクロバンプやはんだバンプ等を用いて電気的に接続される。半導体モジュールは、他のインタポーザから電源を得るとともに、他のインタポーザとの間でデータ送受信が可能な装置である。なお、以下の一実施形態において、ＭＰＵを論理チップの一例として説明する。
　本実施形態に係る半導体モジュール１は、図１及び図２に示すように、インタポーザ１０と、ＭＰＵ２０と、ピラー３０と、ＲＡＭ部４０と、接続部５０と、スペーサ６０と、支持体７０と、を備える。
　インタポーザ１０は、図１及び図２に示すように、平面視矩形の板状体であり、内部に電気回路が形成される。インタポーザ１０は、後述するＭＰＵ２０及びＲＡＭ部４０のそれぞれに電気的に接続される。インタポーザ１０は、他のインタポーザ（図示せず）又はパッケージ基板（図示せず）上に配置され、一方の面（下面）が、例えば、マイクロバンプ（図示せず）やはんだバンプ（図示せず）等を用いて他のインタポーザ又はパッケージ基板に電気的に接続される。なお、以下において、インタポーザ１０の厚さ方向は、積層方向Ｃとして説明される。また、積層方向Ｃのうち、ＭＰＵ２０及びＲＡＭ部４０が載置される面側は、上方として説明される。また、積層方向Ｃのうち、上方とは逆側の方向は、下方として説明される。
　ＭＰＵ２０は、平面視矩形の板状体である。ＭＰＵ２０は、図１及び図２に示すように、下面側に電源端子、通信端子、及びグラウンド端子として機能する回路面（図示せず）が配置される。ＭＰＵ２０の回路面は、インタポーザ１０の上面に対向配置される。
　ピラー３０は、複数配置される。ピラー３０は、インタポーザ１０とＭＰＵ２０との間を通信可能に接続する。具体的には、ピラー３０の一端は、インタポーザ１０に接続され、他端側がＭＰＵ２０の回路面に接続される。ピラー３０は、それぞれが後述するＲＡＭ部４０の積層方向Ｃの厚さよりも長い。
　ＲＡＭ部４０は、それぞれが平面視矩形の積層型ＲＡＭモジュールから構成される。ＲＡＭ部４０は、図２に示すように、インタポーザ１０の上面に載置される。ＲＡＭ部４０の一端部は、後述する接続部５０を介してＭＰＵ２０の一端部と積層方向Ｃで重なって配置される。具体的には、ＲＡＭ部４０の一端部は、ＭＰＵ２０の一端部とインタポーザ１０との間に介在するように配置される。ＲＡＭ部４０のインタポーザ１０の上面に対向する下面は、マイクロバンプＭを用いてインタポーザ１０と電気的に接続される。ＲＡＭ部４０は、特に制限されないが、積層方向Ｃに交差する方向でＭＰＵ２０を挟むように一対に設けられ得る。具体的には、本実施形態において、特に制限されないが、ＲＡＭ部４０は、４つ配置され、ＭＰＵ２０の一辺とその逆側の一辺とにそれぞれの辺に沿って２つずつ設けられ得る。これにより、ＭＰＵ２０を挟む一対のＲＡＭ部４０の間の距離は、ＭＰＵ２０の一辺及びその逆側の一辺との長さよりも短い距離で設けられる。
　ＲＡＭ部４０は、メモリ回路（図示せず）が積層されて形成される。具体的には、ＲＡＭ部４０は、上面にメモリ回路を有する平面視矩形の板状体のダイ（図示せず）が積層方向Ｃに積層されて形成される。ダイは内部に回路が形成されたＳｉ基板であり、積層されたダイのそれぞれは、隣接するダイと電気的に接続される。積層されるダイの間を接続する電源端子及びグラウンド端子は、例えば、バンプレスＴＳＶにより形成され、信号線がＴＣＩ（ThruChip Interface）により形成される。なお、「電気的に接続される」とは、直接接続されるものに限らず、ＴＣＩのように間接的に（例えば、磁界を用いて）接続されることを含む。
　接続部５０は、ＭＰＵ２０とＲＡＭ部４０とを接続する通信インタフェースである。接続部５０は、例えば、ＴＣＩやＣｕパッド等により構成される。接続部５０は、ＭＰＵ２０とＲＡＭ部４０との間を通信可能に接続する。接続部５０は、ＲＡＭ部４０の面のうち、インタポーザ１０に載置される面（下面）とは逆の面（上面）の一端部に接続される。また、接続部５０は、ＭＰＵ２０のインタポーザ１０に対向する面（下面）の一端部に接続される。具体的には、接続部５０は、ＲＡＭ部４０の上面のうちＭＰＵ２０に対向する部分と、ＭＰＵ２０の下面のうちＲＡＭ部４０に対向する部分とに接続される。接続部５０は、ＲＡＭ部４０のそれぞれに配置される。例えば、本実施形態において、接続部５０は、４つのＲＡＭ部４０と、ＭＰＵ２０との間のそれぞれに配置される。なお、接続部５０は、ＭＰＵ２０及びＲＡＭ部４０を物理的に接続するものに制限されず、無線（例えば、ＴＣＩ）を用いて両者を通信可能に接続するものも含む。
　スペーサ６０は、ＲＡＭ部４０の上面に載置される。スペーサ６０は、例えば、平面視矩形に構成される。スペーサ６０は、例えば、シリコンで構成される。スペーサ６０の厚さは、ＭＰＵ２０の厚さとほぼ等しく構成されるか、ＭＰＵ２０の厚さよりも厚く構成される。より好ましくは、インタポーザ１０の上面からスペーサ６０の上面までの高さは、インタポーザ１０の上面から、ピラー３０によってインタポーザ１０に接続されるＭＰＵ２０の上面までの高さと略同じ又は同じ高さとなるように構成される。スペーサ６０は、ＭＰＵ２０に対して、ＲＡＭ部４０の積層方向Ｃに交差する方向に隣接配置される。本実施形態において、スペーサ６０は、ＭＰＵ２０の側面を挟み込むようにＭＰＵ２０に隣接配置される。スペーサ６０の端部のうち、ＭＰＵ２０に対向する側とは逆側の端部は、ＲＡＭ部４０の積層方向Ｃに交差する方向において、ＲＡＭ部４０よりも突出して配置される。具体的には、スペーサ６０の端部のうち、ＭＰＵ２０に対向する側とは逆側の端部が、ＭＰＵ２０に向かう側とは逆側の方向において、ＲＡＭ部４０よりも突出して配置される。
　なお、ＭＰＵ２０及びＲＡＭ部４０の間に隙間が必要無い場合、スペーサ６０の厚さは、ＭＰＵ２０の厚さとほぼ等しく構成される。この場合、接続部５０は、ＲＡＭ部４０とＭＰＵ２０に実装される。例えば、ＭＰＵ２０及びＲＡＭ部４０がＴＣＩや、Ｃｕハイブリッドボンディング技術によって接続される場合、接続部５０は、ＲＡＭ部４０とＭＰＵ２０の内部に配置されるコイル（図示せず）やＲＡＭ部４０の上部表面とＭＰＵ２０の下部表面に露出するＣｕパッド（図示せず）としてＲＡＭ部４０とＭＰＵ２０に実装される。
　支持体７０は、例えば、シリコンで構成される。支持体７０は、例えば、正面視略矩形に形成される。支持体７０は、スペーサ６０の上面と、ＭＰＵ２０の上面とに載置される。支持体７０は、スペーサ６０及びＭＰＵ２０を正面視で覆うことが可能な大きさで形成される。
　次に、半導体モジュール１の動作について説明する。
　まず、インタポーザ１０から、ＭＰＵ２０に電源が供給される。また、インタポーザ１０から、ＲＡＭ部４０に電源が供給される。また、ＭＰＵ２０は、インタポーザ１０とグラウンド接続される。ＲＡＭ部４０は、インタポーザ１０とグラウンド接続される。なお、接続部５０を介してＭＰＵ２０からＲＡＭ部４０に電源とグラウンドを供給しても良い。
　ＲＡＭ部４０にデータがストアされる場合、まず、インタポーザ１０からピラー３０を介してＭＰＵ２０にデータが送られる。ＭＰＵ２０は、送られたデータに基づいて演算した演算結果をストア信号として、ＲＡＭ部４０に送る。即ち、ＭＰＵ２０から送られたストア信号は、ＭＰＵ２０の回路面と、接続部５０と、を通り、ＲＡＭ部４０に送られる。ＲＡＭ部４０は、ストア信号に含まれるアドレスに基づいて、ストア信号に含まれるデータをストアする。
　一方、ＲＡＭ部４０からデータがロードされる場合、まず、インタポーザ１０からピラー３０を介してＭＰＵ２０にロード信号が送られる。即ち、ＭＰＵ２０から送られたロード信号は、ＭＰＵ２０の回路面及び接続部５０を通り、ＲＡＭ部４０に送られる。
　ＲＡＭ部４０は、ロード信号に含まれるアドレスに基づいて、該当するアドレスからデータをロードする。ＲＡＭ部４０は、ロードしたデータについて接続部５０を介してＭＰＵ２０に送る。
　次に、半導体モジュール１の構造について説明する。
　まず、図３に示すように、回路面を有するＭＰＵ２０が用意される。次いで、図４に示すように、ＭＰＵ２０の回路面の両端に、接続部５０の一部が形成される。次いで、図５に示すように、ＭＰＵ２０の回路面の中央部に複数のピラー３０が形成される。
　また、図６に示すように、複数のダイを積層したＲＡＭ部４０が用意される。次いで、図７に示すように、ＲＡＭ部４０の上面（図７では紙面上方）の一端部に接続部５０の一部が形成される。次いで、図８に示すように、ＲＡＭ部４０の下面に複数のマイクロバンプＭが形成される。
　次いで、図９に示すように支持体７０が用意される。支持体７０は、積層方向Ｃにおいて、上下方向を反転して配置される（以下の図９～図１２では、上下方向が逆に示される）。次いで、図１０に示すように、支持体７０の一方の面（下面）上に、ＭＰＵ２０が載置される。具体的には、ＭＰＵ２０は、上面を支持体７０の一方の面（下面）に対向した状態で支持体７０に載置される。次いで、図１１に示すように、スペーサ６０が、支持体７０の一方の面（下面）上に、ＭＰＵ２０に隣接した状態で載置される。次いで、図１２に示すように、ＲＡＭ部４０が、スペーサ６０上に載置される。これにより、ＲＡＭ部４０の上面は、スペーサ６０の下面に対向する。このとき、ＲＡＭ部４０に構成された接続部５０の一部と、ＭＰＵ２０に構成された接続部５０の一部とが重なるようにして配置される。そして、ＭＰＵ２０に接続されたピラー３０と、ＲＡＭ部４０に構成されたバンプとに対してインタポーザ１０の上面が接続されることで、図２に示すような半導体モジュール１の構造が実現される。
　以上のような一実施形態に係る半導体モジュール１によれば、以下の効果を奏する。
（１）半導体モジュールは、論理チップと、積層型ＲＡＭモジュールであるＲＡＭ部４０と、ＲＡＭ部４０の積層方向に沿って重ねて配置されるスペーサ６０と、論理チップ及びＲＡＭ部４０のそれぞれに電気的に接続されるインタポーザ１０と、論理チップとＲＡＭ部４０の間とを通信可能に接続する接続部５０と、を備え、論理チップ及びスペーサ６０は、ＲＡＭ部４０の積層方向に交差する方向に隣接配置され、ＲＡＭ部４０はインタポーザ１０に載置されるとともに、一端部が論理チップの一端部と積層方向で重なって配置され、接続部５０は、ＲＡＭ部４０の一端部及び論理チップの一端部を通信可能に接続する。これにより、ＭＰＵ２０と一対のＲＡＭ部４０のそれぞれとを接続部５０により直接的に接続可能であるので、ＭＰＵ２０と一対のＲＡＭ部４０のそれぞれとの間の信号線（接続部５０の長さ）を短くすることができる。よって、ＭＰＵ２０と一対のＲＡＭ部４０との間のバンド幅を広くすることができる。
（２）半導体モジュールは、ＲＡＭ部４０及びスペーサ６０は、論理チップを挟んで一対に設けられ、接続部５０は、ＲＡＭ部４０ごとに設けられる。これにより、それぞれのＲＡＭ部４０が接続部５０によって個別にＭＰＵ２０に接続されるので、ＭＰＵ２０に対して複数のＲＡＭ部４０を容易に接続することができ、ＲＡＭ部４０の容量を容易に増やすことができる。
（３）スペーサ６０の厚さは、論理チップの厚さとほぼ等しいか、それよりも厚い。これにより、ＲＡＭ部４０の上面にＭＰＵ２０の下面を接続しつつ、支持体７０を安定して配置することができる。
（４）スペーサ６０の端部のうち、論理チップに対向する側とは逆側の端部は、ＲＡＭ部４０の積層方向に交差する方向において、ＲＡＭ部４０よりも突出して配置される。これにより、スペーサ６０の側面がＲＡＭ部４０の側面と面一となる場合に比べ、スペーサ６０の露出する面積が増えるので、ＲＡＭ部４０において発生した熱の放熱性を高めることができる。また、積層するためのペースト等をＲＡＭ部４０の全面に塗布できるため構造を安定化させ、ＲＡＭ部４０の傾きを防止することができる。
（５）半導体モジュールは、インタポーザ１０と論理チップとの間を通信可能に接続する複数のピラー３０であって、それぞれがＲＡＭ部４０の積層方向の厚さよりも長い複数のピラー３０を更に備える。これにより、インタポーザ１０の上面に対して、ＭＰＵ２０の位置をピラー３０の長さだけ離して配置することができる。したがって、ＲＡＭ部４０の上面の一部をＭＰＵ２０の下面の一部に対向させることが可能になり、信号線（接続部５０の長さ）を短くすることができる。
　以上、本発明の半導体モジュールの好ましい一実施形態につき説明したが、本発明は、上述の実施形態に制限されるものではなく、適宜変更が可能である。
　例えば、図１３に示すように、ＭＰＵ２０は、１つのインタポーザ１０に対して複数設けられ、一対のＲＡＭ部４０及び一対のスペーサ６０は、ＭＰＵ２０ごとに設けられてもよい。これにより、複数のＭＰＵ２０のそれぞれに対してＲＡＭ部４０を接続することができるので、ＭＰＵ２０及びＲＡＭ部４０の間の信号線（接続部５０の長さ）を短くすることができ、複数のＭＰＵ２０が存在する場合であっても、バンド幅を広くすることができる。
　また、上記実施形態において、ＲＡＭ部４０及びスペーサ６０は、ＭＰＵ２０を挟むように一対に設けられるとして説明されたが、これに制限されない。例えば、ＲＡＭ部４０及びスペーサ６０は、ＭＰＵ２０の一辺のみに配置されてもよい。また、ＲＡＭ部４０及びスペーサ６０は、ＭＰＵ２０の三辺に配置されてもよく、ＭＰＵ２０を囲繞するように四辺に配置されてもよい。
　また、演算装置はＭＰＵ２０に限定されず、広く論理チップ全般に適用されても良く、メモリはＤＲＡＭに限定されず、広く不揮発性ＲＡＭ（例えばＭＲＡＭ、ＲｅＲＡＭ、ＦｅＲＡＭ等）を含むＲＡＭ（Random Access Memory）全般に適用されても良い。
　１　半導体モジュール
　１０　インタポーザ
　２０　ＭＰＵ
　３０　ピラー
　４０　ＲＡＭ部
　５０　接続部
　６０　スペーサ
　７０　支持体

Claims (7)

  1. 　論理チップと、
    　積層型ＲＡＭモジュールであるＲＡＭ部と、
    　前記ＲＡＭ部の積層方向に沿って重ねて配置されるスペーサと、
    　前記論理チップ及び前記ＲＡＭ部のそれぞれに電気的に接続されるインタポーザと、
    　前記論理チップと前記ＲＡＭ部の間とを通信可能に接続する接続部と、
    を備え、
    　前記論理チップ及び前記スペーサは、前記ＲＡＭ部の積層方向に交差する方向に隣接配置され、
    　前記ＲＡＭ部は前記インタポーザに載置されるとともに、一端部が前記論理チップの一端部と積層方向で重なって配置され、
    　前記接続部は、前記ＲＡＭ部の一端部及び前記論理チップの一端部を通信可能に接続する半導体モジュール。
  2. 　前記ＲＡＭ部及び前記スペーサは、前記論理チップを挟んで一対に設けられ、
    　前記接続部は、前記ＲＡＭ部ごとに設けられる請求項１に記載の半導体モジュール。
  3. 　前記スペーサの厚さは、前記論理チップの厚さとほぼ等しい請求項１又は２に記載の半導体モジュール。
  4. 　前記スペーサの厚さは、前記論理チップの厚さよりも厚い請求項１又は２に記載の半導体モジュール。
  5. 　前記スペーサの端部のうち、前記論理チップに対向する側とは逆側の端部は、前記ＲＡＭ部の積層方向に交差する方向において、前記ＲＡＭ部よりも突出して配置される請求項１から４のいずれか一項に記載の半導体モジュール。
  6. 　前記インタポーザと前記論理チップとの間を通信可能に接続する複数のピラーであって、それぞれが前記ＲＡＭ部の積層方向の厚さよりも長い複数のピラーを更に備える請求項１から５のいずれか一項に記載の半導体モジュール。
  7. 　前記論理チップは、１つの前記インタポーザに対して複数設けられ、
    　一対の前記ＲＡＭ部及び一対の前記スペーサは、前記論理チップごとに設けられる請求項１から６のいずれか一項に記載の半導体モジュール。
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JP7033332B2 (ja) 2022-03-10
US20200357746A1 (en) 2020-11-12
JPWO2019102528A1 (ja) 2020-11-19

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