KR20250077466A - 프로그래밍 가능 집적 회로를 갖는 다이 상에 스택된 메모리 다이를 포함하는 다중-칩 구조 - Google Patents

프로그래밍 가능 집적 회로를 갖는 다이 상에 스택된 메모리 다이를 포함하는 다중-칩 구조 Download PDF

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Publication number
KR20250077466A
KR20250077466A KR1020257007052A KR20257007052A KR20250077466A KR 20250077466 A KR20250077466 A KR 20250077466A KR 1020257007052 A KR1020257007052 A KR 1020257007052A KR 20257007052 A KR20257007052 A KR 20257007052A KR 20250077466 A KR20250077466 A KR 20250077466A
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South Korea
Prior art keywords
die
memory
programmable
memory controller
control logic
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Pending
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KR1020257007052A
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English (en)
Korean (ko)
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매튜 에이치. 클라인
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자일링크스 인코포레이티드
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Publication of KR20250077466A publication Critical patent/KR20250077466A/ko
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    • H01L25/0657—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H01L23/481—
    • H01L24/17—
    • H01L25/18—
    • H01L25/50—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H01L2225/06513—
    • H01L2225/06517—
    • H01L2225/06541—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

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  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1020257007052A 2019-04-23 2020-03-31 프로그래밍 가능 집적 회로를 갖는 다이 상에 스택된 메모리 다이를 포함하는 다중-칩 구조 Pending KR20250077466A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US16/392,170 US11282824B2 (en) 2019-04-23 2019-04-23 Multi-chip structure including a memory die stacked on die having programmable integrated circuit
US16/392,170 2019-04-23
PCT/US2020/026032 WO2020219242A1 (en) 2019-04-23 2020-03-31 Multi-chip structure including a memory die stacked on a die having a programmable integrated circuit
KR1020217037840A KR102778388B1 (ko) 2019-04-23 2020-03-31 프로그래밍 가능 집적 회로를 갖는 다이 상에 스택된 메모리 다이를 포함하는 다중-칩 구조

Related Parent Applications (1)

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KR1020217037840A Division KR102778388B1 (ko) 2019-04-23 2020-03-31 프로그래밍 가능 집적 회로를 갖는 다이 상에 스택된 메모리 다이를 포함하는 다중-칩 구조

Publications (1)

Publication Number Publication Date
KR20250077466A true KR20250077466A (ko) 2025-05-30

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KR1020257007052A Pending KR20250077466A (ko) 2019-04-23 2020-03-31 프로그래밍 가능 집적 회로를 갖는 다이 상에 스택된 메모리 다이를 포함하는 다중-칩 구조
KR1020217037840A Active KR102778388B1 (ko) 2019-04-23 2020-03-31 프로그래밍 가능 집적 회로를 갖는 다이 상에 스택된 메모리 다이를 포함하는 다중-칩 구조

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Country Status (7)

Country Link
US (2) US11282824B2 (https=)
EP (1) EP3925001A1 (https=)
JP (2) JP7668745B2 (https=)
KR (2) KR20250077466A (https=)
CN (2) CN121751653A (https=)
TW (1) TWI836054B (https=)
WO (1) WO2020219242A1 (https=)

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JP2020145231A (ja) 2019-03-04 2020-09-10 キオクシア株式会社 半導体装置およびその製造方法
US11282824B2 (en) * 2019-04-23 2022-03-22 Xilinx, Inc. Multi-chip structure including a memory die stacked on die having programmable integrated circuit
CN113517271A (zh) * 2021-05-20 2021-10-19 浙江毫微米科技有限公司 一种带有堆叠存储器的集成电路结构
US11715731B2 (en) * 2021-08-29 2023-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
CN113722268B (zh) * 2021-09-02 2024-07-19 西安紫光国芯半导体有限公司 一种存算一体的堆叠芯片
CN113793632B (zh) * 2021-09-02 2024-05-28 西安紫光国芯半导体有限公司 非易失可编程芯片
CN113745197B (zh) * 2021-09-03 2024-08-30 西安紫光国芯半导体股份有限公司 一种三维异质集成的可编程阵列芯片结构和电子器件
US12489061B2 (en) 2022-06-27 2025-12-02 Texas Instruments Incorporated Semiconductor device with multiple dies
US12505068B2 (en) 2023-06-28 2025-12-23 Xilinx, Inc. Tiled compute and programmable logic array
CN117222234B (zh) * 2023-11-07 2024-02-23 北京奎芯集成电路设计有限公司 一种基于UCIe接口的半导体器件
CN118409997B (zh) * 2024-04-29 2025-04-15 清华大学 多芯片集成封装高密度算力模组的装置

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US8356138B1 (en) 2007-08-20 2013-01-15 Xilinx, Inc. Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
US7899983B2 (en) * 2007-08-31 2011-03-01 International Business Machines Corporation Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module
US7701251B1 (en) 2008-03-06 2010-04-20 Xilinx, Inc. Methods and apparatus for implementing a stacked memory programmable integrated circuit system in package
TW201225249A (en) * 2010-12-08 2012-06-16 Ind Tech Res Inst Stacked structure and stacked method for three-dimensional integrated circuit
KR20120119960A (ko) 2011-04-21 2012-11-01 삼성전자주식회사 마이크로 범프 연결성을 테스트할 수 있는 반도체 장치
CN104205234B (zh) * 2012-03-30 2017-07-11 英特尔公司 用于存储器电路测试引擎的通用数据加扰器
DE112012006161B4 (de) * 2012-03-30 2020-09-17 Intel Corporation Integrierter Selbsttest für Stapelspeicherarchitektur
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US9065722B2 (en) 2012-12-23 2015-06-23 Advanced Micro Devices, Inc. Die-stacked device with partitioned multi-hop network
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JP2018074065A (ja) * 2016-11-01 2018-05-10 富士通株式会社 半導体装置
KR102624199B1 (ko) 2016-11-17 2024-01-15 에스케이하이닉스 주식회사 관통 실리콘 비아 기술을 적용한 반도체 패키지
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Also Published As

Publication number Publication date
WO2020219242A1 (en) 2020-10-29
US20200343234A1 (en) 2020-10-29
CN121751653A (zh) 2026-03-27
KR20220002401A (ko) 2022-01-06
JP7668745B2 (ja) 2025-04-25
TWI836054B (zh) 2024-03-21
TW202101624A (zh) 2021-01-01
JP2025114585A (ja) 2025-08-05
CN113767471A (zh) 2021-12-07
US11282824B2 (en) 2022-03-22
US11670630B2 (en) 2023-06-06
JP2022529994A (ja) 2022-06-27
CN113767471B (zh) 2025-12-30
US20220199604A1 (en) 2022-06-23
EP3925001A1 (en) 2021-12-22
KR102778388B1 (ko) 2025-03-06

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