CN121751653A - 包括堆叠在具有可编程集成电路的管芯上的存储器管芯的多芯片结构 - Google Patents

包括堆叠在具有可编程集成电路的管芯上的存储器管芯的多芯片结构

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Publication number
CN121751653A
CN121751653A CN202511852682.3A CN202511852682A CN121751653A CN 121751653 A CN121751653 A CN 121751653A CN 202511852682 A CN202511852682 A CN 202511852682A CN 121751653 A CN121751653 A CN 121751653A
Authority
CN
China
Prior art keywords
die
memory
memory controller
programmable
package substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202511852682.3A
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English (en)
Chinese (zh)
Inventor
M·H·克莱因
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of CN121751653A publication Critical patent/CN121751653A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN202511852682.3A 2019-04-23 2020-03-31 包括堆叠在具有可编程集成电路的管芯上的存储器管芯的多芯片结构 Pending CN121751653A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US16/392,170 US11282824B2 (en) 2019-04-23 2019-04-23 Multi-chip structure including a memory die stacked on die having programmable integrated circuit
US16/392,170 2019-04-23
CN202080030688.1A CN113767471B (zh) 2019-04-23 2020-03-31 包括堆叠在具有可编程集成电路的管芯上的存储器管芯的多芯片结构
PCT/US2020/026032 WO2020219242A1 (en) 2019-04-23 2020-03-31 Multi-chip structure including a memory die stacked on a die having a programmable integrated circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN202080030688.1A Division CN113767471B (zh) 2019-04-23 2020-03-31 包括堆叠在具有可编程集成电路的管芯上的存储器管芯的多芯片结构

Publications (1)

Publication Number Publication Date
CN121751653A true CN121751653A (zh) 2026-03-27

Family

ID=70476331

Family Applications (2)

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CN202511852682.3A Pending CN121751653A (zh) 2019-04-23 2020-03-31 包括堆叠在具有可编程集成电路的管芯上的存储器管芯的多芯片结构
CN202080030688.1A Active CN113767471B (zh) 2019-04-23 2020-03-31 包括堆叠在具有可编程集成电路的管芯上的存储器管芯的多芯片结构

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Country Status (7)

Country Link
US (2) US11282824B2 (https=)
EP (1) EP3925001A1 (https=)
JP (2) JP7668745B2 (https=)
KR (2) KR20250077466A (https=)
CN (2) CN121751653A (https=)
TW (1) TWI836054B (https=)
WO (1) WO2020219242A1 (https=)

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JP2020145231A (ja) 2019-03-04 2020-09-10 キオクシア株式会社 半導体装置およびその製造方法
US11282824B2 (en) * 2019-04-23 2022-03-22 Xilinx, Inc. Multi-chip structure including a memory die stacked on die having programmable integrated circuit
CN113517271A (zh) * 2021-05-20 2021-10-19 浙江毫微米科技有限公司 一种带有堆叠存储器的集成电路结构
US11715731B2 (en) * 2021-08-29 2023-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
CN113722268B (zh) * 2021-09-02 2024-07-19 西安紫光国芯半导体有限公司 一种存算一体的堆叠芯片
CN113793632B (zh) * 2021-09-02 2024-05-28 西安紫光国芯半导体有限公司 非易失可编程芯片
CN113745197B (zh) * 2021-09-03 2024-08-30 西安紫光国芯半导体股份有限公司 一种三维异质集成的可编程阵列芯片结构和电子器件
US12489061B2 (en) 2022-06-27 2025-12-02 Texas Instruments Incorporated Semiconductor device with multiple dies
US12505068B2 (en) 2023-06-28 2025-12-23 Xilinx, Inc. Tiled compute and programmable logic array
CN117222234B (zh) * 2023-11-07 2024-02-23 北京奎芯集成电路设计有限公司 一种基于UCIe接口的半导体器件
CN118409997B (zh) * 2024-04-29 2025-04-15 清华大学 多芯片集成封装高密度算力模组的装置

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US8356138B1 (en) 2007-08-20 2013-01-15 Xilinx, Inc. Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
US7899983B2 (en) * 2007-08-31 2011-03-01 International Business Machines Corporation Buffered memory module supporting double the memory device data width in the same physical space as a conventional memory module
US7701251B1 (en) 2008-03-06 2010-04-20 Xilinx, Inc. Methods and apparatus for implementing a stacked memory programmable integrated circuit system in package
TW201225249A (en) * 2010-12-08 2012-06-16 Ind Tech Res Inst Stacked structure and stacked method for three-dimensional integrated circuit
KR20120119960A (ko) 2011-04-21 2012-11-01 삼성전자주식회사 마이크로 범프 연결성을 테스트할 수 있는 반도체 장치
CN104205234B (zh) * 2012-03-30 2017-07-11 英特尔公司 用于存储器电路测试引擎的通用数据加扰器
DE112012006161B4 (de) * 2012-03-30 2020-09-17 Intel Corporation Integrierter Selbsttest für Stapelspeicherarchitektur
US8737108B2 (en) * 2012-09-25 2014-05-27 Intel Corporation 3D memory configurable for performance and power
US9065722B2 (en) 2012-12-23 2015-06-23 Advanced Micro Devices, Inc. Die-stacked device with partitioned multi-hop network
US9135185B2 (en) 2012-12-23 2015-09-15 Advanced Micro Devices, Inc. Die-stacked memory device providing data translation
US9286948B2 (en) 2013-07-15 2016-03-15 Advanced Micro Devices, Inc. Query operations for stacked-die memory device
KR20230151553A (ko) * 2016-06-27 2023-11-01 애플 인크. 조합된 높은 밀도, 낮은 대역폭 및 낮은 밀도, 높은 대역폭 메모리들을 갖는 메모리 시스템
JP2018074065A (ja) * 2016-11-01 2018-05-10 富士通株式会社 半導体装置
KR102624199B1 (ko) 2016-11-17 2024-01-15 에스케이하이닉스 주식회사 관통 실리콘 비아 기술을 적용한 반도체 패키지
KR102650497B1 (ko) * 2017-02-28 2024-03-25 에스케이하이닉스 주식회사 적층형 반도체 장치
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US11282824B2 (en) * 2019-04-23 2022-03-22 Xilinx, Inc. Multi-chip structure including a memory die stacked on die having programmable integrated circuit

Also Published As

Publication number Publication date
WO2020219242A1 (en) 2020-10-29
US20200343234A1 (en) 2020-10-29
KR20220002401A (ko) 2022-01-06
KR20250077466A (ko) 2025-05-30
JP7668745B2 (ja) 2025-04-25
TWI836054B (zh) 2024-03-21
TW202101624A (zh) 2021-01-01
JP2025114585A (ja) 2025-08-05
CN113767471A (zh) 2021-12-07
US11282824B2 (en) 2022-03-22
US11670630B2 (en) 2023-06-06
JP2022529994A (ja) 2022-06-27
CN113767471B (zh) 2025-12-30
US20220199604A1 (en) 2022-06-23
EP3925001A1 (en) 2021-12-22
KR102778388B1 (ko) 2025-03-06

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