JP2022522012A5 - - Google Patents
Info
- Publication number
- JP2022522012A5 JP2022522012A5 JP2021550236A JP2021550236A JP2022522012A5 JP 2022522012 A5 JP2022522012 A5 JP 2022522012A5 JP 2021550236 A JP2021550236 A JP 2021550236A JP 2021550236 A JP2021550236 A JP 2021550236A JP 2022522012 A5 JP2022522012 A5 JP 2022522012A5
- Authority
- JP
- Japan
- Prior art keywords
- data clock
- memory
- command
- data
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024097486A JP7703748B2 (ja) | 2019-03-01 | 2024-06-17 | メモリにおける拡張データクロック動作 |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201962812689P | 2019-03-01 | 2019-03-01 | |
| US62/812,689 | 2019-03-01 | ||
| US16/803,977 US11175836B2 (en) | 2019-03-01 | 2020-02-27 | Enhanced data clock operations in memory |
| US16/803,977 | 2020-02-27 | ||
| PCT/US2020/020374 WO2020180677A1 (en) | 2019-03-01 | 2020-02-28 | Enhanced data clock operations in memory |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024097486A Division JP7703748B2 (ja) | 2019-03-01 | 2024-06-17 | メモリにおける拡張データクロック動作 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2022522012A JP2022522012A (ja) | 2022-04-13 |
| JP2022522012A5 true JP2022522012A5 (https=) | 2023-02-14 |
| JP7508470B2 JP7508470B2 (ja) | 2024-07-01 |
Family
ID=72236931
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021550236A Active JP7508470B2 (ja) | 2019-03-01 | 2020-02-28 | メモリにおける拡張データクロック動作 |
| JP2024097486A Active JP7703748B2 (ja) | 2019-03-01 | 2024-06-17 | メモリにおける拡張データクロック動作 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024097486A Active JP7703748B2 (ja) | 2019-03-01 | 2024-06-17 | メモリにおける拡張データクロック動作 |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US11175836B2 (https=) |
| EP (2) | EP4290521B1 (https=) |
| JP (2) | JP7508470B2 (https=) |
| KR (2) | KR102867872B1 (https=) |
| CN (2) | CN113519025B (https=) |
| ES (1) | ES2967120T3 (https=) |
| TW (2) | TWI856065B (https=) |
| WO (1) | WO2020180677A1 (https=) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11175836B2 (en) | 2019-03-01 | 2021-11-16 | Qualcomm Incorporated | Enhanced data clock operations in memory |
| US11587633B2 (en) * | 2020-06-23 | 2023-02-21 | Micron Technology, Inc. | Direct testing of in-package memory |
| US12061795B2 (en) * | 2021-05-07 | 2024-08-13 | Micron Technologies, Inc. | Repair element availability communication |
| US11914532B2 (en) * | 2021-08-31 | 2024-02-27 | Apple Inc. | Memory device bandwidth optimization |
| US12315551B2 (en) * | 2021-12-08 | 2025-05-27 | Advanced Micro Devices, Inc. | Read clock start and stop for synchronous memories |
| JP7799507B2 (ja) * | 2022-02-24 | 2026-01-15 | キヤノン株式会社 | メモリ制御装置、メモリ制御装置の制御方法およびプログラム |
| KR20230127856A (ko) | 2022-02-25 | 2023-09-01 | 에스케이하이닉스 주식회사 | 효율적으로 클럭 동기를 수행할 수 있는 메모리 시스템 |
| TWI846376B (zh) * | 2022-03-23 | 2024-06-21 | 南韓商三星電子股份有限公司 | 記憶體裝置、操作記憶體裝置的方法、操作記憶體控制器的方法 |
| US12456508B2 (en) | 2022-03-23 | 2025-10-28 | Samsung Electronics Co., Ltd. | Memory device, operation method of a memory device, and operation method of a memory controller |
| KR102897879B1 (ko) * | 2022-07-08 | 2025-12-08 | 창신 메모리 테크놀로지즈 아이엔씨 | 제어 장치, 메모리, 신호 처리 방법 및 전자 기기 |
| US12542165B2 (en) * | 2022-10-13 | 2026-02-03 | SK Hynix Inc. | Semiconductor system |
| WO2025085054A1 (en) * | 2023-10-17 | 2025-04-24 | Google Llc | Lpddr5 dram wck clock power saving through command buffering |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4060527B2 (ja) * | 2000-12-19 | 2008-03-12 | 富士通株式会社 | クロック同期型ダイナミックメモリ |
| US6898683B2 (en) | 2000-12-19 | 2005-05-24 | Fujitsu Limited | Clock synchronized dynamic memory and clock synchronized integrated circuit |
| US6781911B2 (en) | 2002-04-09 | 2004-08-24 | Intel Corporation | Early power-down digital memory device and method |
| US6650594B1 (en) * | 2002-07-12 | 2003-11-18 | Samsung Electronics Co., Ltd. | Device and method for selecting power down exit |
| KR100605606B1 (ko) * | 2003-05-29 | 2006-07-28 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 동기식 셀프 리프레쉬 제어 방법 및제어 회로 |
| TWI410970B (zh) * | 2005-07-29 | 2013-10-01 | Ibm | 控制記憶體的方法及記憶體系統 |
| US8964779B2 (en) * | 2007-11-30 | 2015-02-24 | Infineon Technologies Ag | Device and method for electronic controlling |
| JP4962396B2 (ja) * | 2008-04-23 | 2012-06-27 | 日本電気株式会社 | パケット処理装置 |
| JP5060574B2 (ja) * | 2010-03-16 | 2012-10-31 | 株式会社東芝 | メモリシステム |
| WO2012021380A2 (en) | 2010-08-13 | 2012-02-16 | Rambus Inc. | Fast-wake memory |
| JP5642524B2 (ja) | 2010-12-13 | 2014-12-17 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | 半導体装置 |
| WO2012122381A2 (en) | 2011-03-09 | 2012-09-13 | Rambus Inc. | Power-management for integrated circuits |
| JP5819678B2 (ja) * | 2011-08-30 | 2015-11-24 | ルネサスエレクトロニクス株式会社 | Ｕｓｂハブ及びｕｓｂハブの制御方法 |
| WO2013095551A1 (en) * | 2011-12-22 | 2013-06-27 | Intel Corporation | Mechanisms for clock gating |
| US9280614B1 (en) * | 2012-11-30 | 2016-03-08 | Cadence Design Systems, Inc. | Methods, systems, and apparatus for clock topology planning with reduced power consumption |
| US9658642B2 (en) | 2013-07-01 | 2017-05-23 | Intel Corporation | Timing control for unmatched signal receiver |
| KR102272259B1 (ko) | 2015-07-01 | 2021-07-06 | 삼성전자주식회사 | 커맨드 연동 클럭 생성 스키마를 갖는 반도체 메모리 장치 |
| US10169262B2 (en) | 2015-07-14 | 2019-01-01 | Qualcomm Incorporated | Low-power clocking for a high-speed memory interface |
| US10186309B2 (en) * | 2016-06-29 | 2019-01-22 | Samsung Electronics Co., Ltd. | Methods of operating semiconductor memory devices and semiconductor memory devices |
| KR20180034738A (ko) * | 2016-09-26 | 2018-04-05 | 삼성전자주식회사 | 메모리 장치 및 그것의 분주 클록 보정 방법 |
| WO2018081746A1 (en) | 2016-10-31 | 2018-05-03 | Intel Corporation | Applying chip select for memory device identification and power management control |
| KR20180069960A (ko) * | 2016-12-15 | 2018-06-26 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그의 동작 방법 |
| US10210918B2 (en) * | 2017-02-28 | 2019-02-19 | Micron Technology, Inc. | Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal |
| KR102679157B1 (ko) * | 2018-10-30 | 2024-06-27 | 삼성전자주식회사 | 모드 레지스터 쓰기 명령을 이용하여 쓰기 클럭의 듀티 사이클의 트레이닝을 수행하는 시스템 온 칩, 시스템 온 칩의 동작 방법, 및 시스템 온 칩을 포함하는 전자 장치 |
| US11175836B2 (en) | 2019-03-01 | 2021-11-16 | Qualcomm Incorporated | Enhanced data clock operations in memory |
-
2020
- 2020-02-27 US US16/803,977 patent/US11175836B2/en active Active
- 2020-02-28 EP EP23205327.2A patent/EP4290521B1/en active Active
- 2020-02-28 EP EP20715575.5A patent/EP3931830B1/en active Active
- 2020-02-28 ES ES20715575T patent/ES2967120T3/es active Active
- 2020-02-28 CN CN202080017983.3A patent/CN113519025B/zh active Active
- 2020-02-28 JP JP2021550236A patent/JP7508470B2/ja active Active
- 2020-02-28 WO PCT/US2020/020374 patent/WO2020180677A1/en not_active Ceased
- 2020-02-28 KR KR1020217026962A patent/KR102867872B1/ko active Active
- 2020-02-28 CN CN202511668146.8A patent/CN121300608A/zh active Pending
- 2020-02-28 KR KR1020257032361A patent/KR20250152104A/ko active Pending
- 2020-03-02 TW TW109106698A patent/TWI856065B/zh active
- 2020-03-02 TW TW113132304A patent/TWI895084B/zh active
-
2021
- 2021-10-05 US US17/494,089 patent/US11662919B2/en active Active
-
2024
- 2024-06-17 JP JP2024097486A patent/JP7703748B2/ja active Active
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