WO2020180677A1 - Enhanced data clock operations in memory - Google Patents

Enhanced data clock operations in memory Download PDF

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Publication number
WO2020180677A1
WO2020180677A1 PCT/US2020/020374 US2020020374W WO2020180677A1 WO 2020180677 A1 WO2020180677 A1 WO 2020180677A1 US 2020020374 W US2020020374 W US 2020020374W WO 2020180677 A1 WO2020180677 A1 WO 2020180677A1
Authority
WO
WIPO (PCT)
Prior art keywords
data clock
memory
command
host
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2020/020374
Other languages
English (en)
French (fr)
Inventor
Jungwon Suh
Dexter Tamio Chun
Michael Hawjing Lo
Shyamkumar Thoziyoor
Ravindra Kumar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to EP23205327.2A priority Critical patent/EP4290521B1/en
Priority to CN202511668146.8A priority patent/CN121300608A/zh
Priority to KR1020217026962A priority patent/KR102867872B1/ko
Priority to KR1020257032361A priority patent/KR20250152104A/ko
Priority to EP20715575.5A priority patent/EP3931830B1/en
Priority to ES20715575T priority patent/ES2967120T3/es
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Priority to BR112021016211-9A priority patent/BR112021016211B1/pt
Priority to CN202080017983.3A priority patent/CN113519025B/zh
Priority to JP2021550236A priority patent/JP7508470B2/ja
Publication of WO2020180677A1 publication Critical patent/WO2020180677A1/en
Anticipated expiration legal-status Critical
Priority to JP2024097486A priority patent/JP7703748B2/ja
Ceased legal-status Critical Current

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Classifications

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    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
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    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the memory may be embedded with the one processor on a semiconductor die or be part of a different semiconductor die.
  • the memory may perform various functions.
  • the memory may be used as cache, register file, or storage.
  • the memory may be of various kinds.
  • the memory may be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash, or NOR flash, etc.
  • the command decoder 173 may be configured to decode various commands provided by the host 110 (e.g., the memory controller 130) via the link 190.
  • the command decoder 173 may be configured to decode a read command, a write command, and the various WCK2CK commands presented above.
  • FIG. 3 illustrates waveforms of WCK synchronization with the WCK SUSPEND mode, in accordance with certain aspects of the present disclosure.
  • read operations are provided as examples. Write operations may be implemented in similar fashion.
  • the host 110 e.g., the memory controller 130
  • the host 110 issues a WCK2CK SYNC command to the memory 150 via the link 190, with WS_RD at logic one.
  • the host 110 e.g., the memory controller 130
  • WCK2CK data clock WCK synchronization
  • FIG. 6 illustrates portions of the memory I/O module 160 of FIG. 1 operating the data clock (WCK) suspend mode, in accordance with certain aspects of the present disclosure.
  • FIG. 6 illustrates that the memory I/O module 160 includes a WCK buffer 602, a CA buffer 606, and a DQ buffer 608 (the memory I/O module 160 may include multiple instances of these buffers).
  • FIG. 6 further illustrates that the memory I/O module 160 includes a clock tree 603 and the WCK suspend control module 605.
  • a data clock is received by the memory from a host via a link. See, for example, FIG. 1 and FIG. 6, the WCK buffer receives the data clock WCK from the host 110 via the link 190.
  • the data clock is synchronized by the memory with the host. See, for example, the synchronization cycles between T b o and T bi of FIG. 3 and 420 at FIG. 4.
  • a clock tree buffer of the memory is toggled based on the data clock to capture write data or to output read data. See, for example, the clock tree buffer 604 toggles based on the data clock WCK to capture write data or to output read data.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • Memory System (AREA)
  • Power Sources (AREA)
  • Dram (AREA)
  • Communication Control (AREA)
  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
PCT/US2020/020374 2019-03-01 2020-02-28 Enhanced data clock operations in memory Ceased WO2020180677A1 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
BR112021016211-9A BR112021016211B1 (pt) 2019-03-01 2020-02-28 Operações de relógio de dados melhorado na memória
CN202511668146.8A CN121300608A (zh) 2019-03-01 2020-02-28 存储器中的增强数据时钟操作
KR1020217026962A KR102867872B1 (ko) 2019-03-01 2020-02-28 메모리에서의 향상된 데이터 클럭 동작들
KR1020257032361A KR20250152104A (ko) 2019-03-01 2020-02-28 메모리에서의 향상된 데이터 클럭 동작들
EP20715575.5A EP3931830B1 (en) 2019-03-01 2020-02-28 Enhanced data clock operations in memory
EP23205327.2A EP4290521B1 (en) 2019-03-01 2020-02-28 Enhanced data clock operations in memory
JP2021550236A JP7508470B2 (ja) 2019-03-01 2020-02-28 メモリにおける拡張データクロック動作
ES20715575T ES2967120T3 (es) 2019-03-01 2020-02-28 Operaciones de reloj de datos potenciadas en la memoria
CN202080017983.3A CN113519025B (zh) 2019-03-01 2020-02-28 存储器中的增强数据时钟操作
JP2024097486A JP7703748B2 (ja) 2019-03-01 2024-06-17 メモリにおける拡張データクロック動作

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962812689P 2019-03-01 2019-03-01
US62/812,689 2019-03-01
US16/803,977 US11175836B2 (en) 2019-03-01 2020-02-27 Enhanced data clock operations in memory
US16/803,977 2020-02-27

Publications (1)

Publication Number Publication Date
WO2020180677A1 true WO2020180677A1 (en) 2020-09-10

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PCT/US2020/020374 Ceased WO2020180677A1 (en) 2019-03-01 2020-02-28 Enhanced data clock operations in memory

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US (2) US11175836B2 (https=)
EP (2) EP4290521B1 (https=)
JP (2) JP7508470B2 (https=)
KR (2) KR102867872B1 (https=)
CN (2) CN113519025B (https=)
ES (1) ES2967120T3 (https=)
TW (2) TWI856065B (https=)
WO (1) WO2020180677A1 (https=)

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JP2023122869A (ja) * 2022-02-24 2023-09-05 キヤノン株式会社 メモリ制御装置、メモリ制御装置の制御方法およびプログラム
JP7595228B1 (ja) 2021-12-08 2024-12-05 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 同期メモリのための読み取りクロック開始及び停止

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US11587633B2 (en) * 2020-06-23 2023-02-21 Micron Technology, Inc. Direct testing of in-package memory
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TWI846376B (zh) * 2022-03-23 2024-06-21 南韓商三星電子股份有限公司 記憶體裝置、操作記憶體裝置的方法、操作記憶體控制器的方法
US12456508B2 (en) 2022-03-23 2025-10-28 Samsung Electronics Co., Ltd. Memory device, operation method of a memory device, and operation method of a memory controller
KR102897879B1 (ko) * 2022-07-08 2025-12-08 창신 메모리 테크놀로지즈 아이엔씨 제어 장치, 메모리, 신호 처리 방법 및 전자 기기
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WO2025085054A1 (en) * 2023-10-17 2025-04-24 Google Llc Lpddr5 dram wck clock power saving through command buffering

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