JP2022500878A - 半導体の垂直ショットキーダイオード及びその製造方法 - Google Patents
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Abstract
Description
−寄生バイポーラトランジスタが存在せず(本ショットキーダイオードの電気的特性が、寄生バイポーラトランジスタの動作によって損なわれることはない)、
−基板電流が極めて小さく(完全な誘電体分離による)、
−逆方向バイアスでのエッジ部のリークが低減する(逆方向バイアスでの等電位面分布がほぼ平坦になり、このことが、ショットキー領域のエッジ部の電場を低減する助けとなっていることに起因して)、ということである。
Claims (13)
- 垂直ショットキーダイオードを備える半導体デバイス(300、400、500、600、700)であって、前記デバイスが、
表側面(101a)及び裏側面(101b’)を有する、半導体材料製の基板(101)と、
前記基板(101)の表面部分に形成され、前記表側面(101a)に対向し、かつ第1の導電型を有する低濃度にドープされた領域(102)と、
前記低濃度にドープされた領域(102)における前記基板(101)の前記表側面(101a)に形成され、ショットキー接点を確立している第1の電極(111)と、
前記基板(101)の前記裏側面(101b’)にあり、前記低濃度にドープされた領域(102)と接触しており、かつ第1の導電型を有する高濃度にドープされた領域(140)と、
前記高濃度にドープされた領域(140)における前記基板(101)の前記裏側面(101b’)と電気的に接触して、オーミック接点を確立している第2の電極(160a)と、を備え、
前記基板(101)の前記表側面(101a)にある金属間誘電体層(120)、及び前記金属間誘電体層(120)内で、前記表側面(101a)の上方に配置された少なくとも1つの第1の表側金属相互接続層(121)と、
前記第1の表側金属相互接続層(121)内に画定され、前記金属間誘電体層(120)を貫通して延在している接点(115)を介して、前記第1の電極(111)と電気的に接触している第1の相互接続パッド(121a)と、
前記第1の表側金属相互接続層(121)から前記基板(101)の前記裏側面(101b’)まで、前記基板(101)を貫通して延在しているシリコン貫通ビア構造(162)と、をさらに備える、
半導体デバイス(300、400、500、600、700)。 - 前記シリコン貫通ビア構造(162)が、誘電体ライナ(161b)及び導電性充填部(161a)を含み、かつ前記低濃度にドープされた領域(102)及び前記高濃度にドープされた領域(140)を横方向に包囲して、電気的分離をもたらしている、請求項1に記載のデバイス。
- 前記第1の相互接続パッド(121a)が、前記表側面(101a)で利用できる第1の電気接点をもたらし、また、前記第1の表側金属相互接続層(121)内に第2の相互接続パッド(121b)が画定されて、前記表側面(101a)で利用できる第2の電気接点をもたらし、また前記デバイスが、前記基板(101)の前記裏側面(101b’)の上方にあるさらに別の金属間誘電体層(180)、及び前記さらに別の金属間誘電体層(180)内に配置された少なくとも1つの第1の裏側金属相互接続層をさらに備え、前記シリコン貫通ビア構造(162)が前記第2の相互接続パッド(121b)から、前記第1の裏側金属相互接続層内に画定され、前記第2の電極(160a)と電気的接触している第1の相互接続領域(170a)まで延在し、前記シリコン貫通ビア構造(162)の前記導電性充填部(161a)が、前記第2の電極(160a)と前記第2の相互接続パッド(121b)との間の電気的接触を確立している、請求項2に記載のデバイス。
- 前記基板(101)の前記裏側面(101b’)の上方にあるさらに別の金属間誘電体層(180)、及び前記さらに別の金属間誘電体層(180)内に配置された少なくとも1つの第1の裏側金属相互接続層をさらに備え、
前記第1の裏側金属相互接続層内に第1の相互接続領域(170a)が、前記第2の電極(160a)と電気的に接触している状態で画定され、前記裏側面(101b’)で利用できる第2の電気接点をもたらし、また、前記第1の裏側金属相互接続層内に第2の相互接続領域(170b)が画定され、ここで、前記シリコン貫通ビア構造(162)が前記第1の相互接続パッド(121a)から前記第2の相互接続領域(170b)まで延在し、前記シリコン貫通ビア構造(162)の前記導電性充填部(161a)が、前記第1の電極(111)と前記第2の相互接続領域(170b)との間の電気的接触を確立しており、これによって前記裏側面(101b’)で利用できる第1の電気接点がもたらされている、請求項2に記載のデバイス。 - 前記金属間誘電体層(120)の上面(120a)に結合されたキャリアウェーハ(130)をさらに備える、請求項1から4のいずれか一項に記載のデバイス。
- 前記第1の電極(111)が金属シリサイド層から形成されている、請求項1から5のいずれか一項に記載のデバイス。
- 第1の導電型とは反対の第2の導電型によって構成され、前記低濃度にドープされた領域(102)の周辺領域における前記基板(101)の前記表側面(101a)に配置されたガードリング(108)をさらに備える、請求項1から6のいずれか一項に記載のデバイス。
- 前記ガードリング(108)が前記第1の電極(111)とオーバーラップし、かつ接触しているか、又は前記第1の電極(111)と接触しておらず、フローティングしている、請求項7に記載のデバイス。
- 前記低濃度にドープされた領域(102)における前記基板(101)の前記表側面(101a)に配置され、幅が同じであり、かつ等距離にある、前記第1の導電型とは反対の第2の導電型を有するドープされた領域(109)のグリッド(188)をさらに備える、請求項1から8のいずれか一項に記載のデバイス。
- 前記基板(101)の前記裏側面(101b’)から、前記低濃度にドープされた領域(102)における前記基板(101)の前記表側面(101a)に形成されたシャロー・トレンチ・アイソレーション(104)まで延在している、誘電体材料から形成されたディープ・トレンチ・アイソレーション領域(106)をさらに備え、前記シャロー・トレンチ・アイソレーション(104)と前記ディープ・トレンチ・アイソレーション領域(106)とが、前記低濃度にドープされた領域(102)及び前記高濃度にドープされた領域(140)を共に横方向に包囲して、誘電体分離をもたらしている、請求項1から9のいずれか一項に記載のデバイス。
- 垂直ショットキーダイオードを備える半導体デバイス(300、400、500、600、700)を製造するための方法であって、前記方法が、
上になる表側面(101a)、及び前記表側面(101a)に対向している裏側面(101b)を有する、半導体材料製の基板(101)を設け、前記基板(101)の表面部分に、前記表側面(101a)に対向し、かつ第1の導電型を有する、低濃度にドープされた領域(102)を形成するステップと、
ショットキー接点を確立するように、前記低濃度にドープされた領域(102)における前記基板(101)の前記表側面(101a)に第1の電極(111)を形成するステップと、
前記基板(101)の前記表側面(101a)に金属間誘電体層(120)を形成し、かつ前記金属間誘電体層(120)内で、前記表側面(101a)の上方に少なくとも1つの第1の表側金属相互接続層(121)を配置形成するステップと、
前記第1の表側金属相互接続層(121)内に、前記金属間誘電体層(120)を貫通して延在している接点(115)を介して、前記第1の電極(111)と電気的に接触している第1の相互接続パッド(121a)を画定するステップと、
前記基板(101)を反転させ、その結果、前記表側面(101a)に対向している前記基板(101)の前記裏側面(101b)が上になるようにするステップと、
前記基板(101)を前記裏側面(101b)から薄肉化するステップと、
前記基板(101)の前記薄肉化された裏側面(101b’)に、前記低濃度にドープされた領域(102)と接触し、かつ第1の導電型を有する高濃度にドープされた領域(140)を形成するステップと、
前記高濃度にドープされた領域(140)における前記基板(101)の前記薄肉化された裏側面(101b’)と電気的に接触して、オーミック接点を確立するように、第2の電極(160a)を形成するステップと、を含み、
前記基板(101)の前記薄肉化された裏側面(101b’)から前記第1の表側金属相互接続層(121)まで、前記基板(101)を貫通して延在しているシリコン貫通ビア構造(162)を形成するステップと、をさらに含む、
垂直ショットキーダイオードを備える半導体デバイス(300、400、500、600、700)を製造するための方法。 - 前記基板(101)を前記裏側面(101b)から薄肉化する前記ステップが、前記基板(101)の前記表側面(101a)にキャリアウェーハ(130)を結合するステップと、
前記基板(101)において、自身の前記裏側面(101b)を処理するステップと、
前記低濃度にドープされた領域(102)を露出させ、かつ前記裏側面(101b’)を画定するように、前記薄肉化するステップを実行するステップと、をさらに含む、
請求項11に記載の方法。 - 前記第2の電極(160a)を形成する前記ステップが、
前記裏側面(101b’)に誘電体層(150)を形成するステップと、
前記高濃度にドープされた領域(140)の当該領域で、前記誘電体層(150)に接点開口部(152)を貫通エッチングするステップと、
導電性領域で前記接点開口部(152)を充填することにより、前記第2の電極(160a)を構成するステップと、を含む、
請求項12に記載の方法。
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